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authorAndreas K. Hüttel <dilfridge@gentoo.org>2023-01-27 14:38:37 +0100
committerAndreas K. Hüttel <dilfridge@gentoo.org>2023-01-27 14:38:37 +0100
commitf34ca4ea06f249be19ea626c0e997e7b5060ac6e (patch)
tree0b08d3edf6024fbc8efa0bcea6ac893818c6510c
parentmipsel3-n32: update_seed yes for split-usr (diff)
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mips: parallelize better
Signed-off-by: Andreas K. Hüttel <dilfridge@gentoo.org>
-rw-r--r--tools/catalyst-auto-qemu-mips-1.conf4
-rw-r--r--tools/catalyst-auto-qemu-mips-2.conf4
-rw-r--r--tools/catalyst-auto-qemu-mips-3.conf4
-rw-r--r--tools/catalyst-auto-qemu-mips-4.conf4
-rw-r--r--tools/catalyst-auto-qemu-mips-common39
5 files changed, 55 insertions, 0 deletions
diff --git a/tools/catalyst-auto-qemu-mips-1.conf b/tools/catalyst-auto-qemu-mips-1.conf
new file mode 100644
index 00000000..bf7dee78
--- /dev/null
+++ b/tools/catalyst-auto-qemu-mips-1.conf
@@ -0,0 +1,4 @@
+
+source ${REPO_DIR}/tools/catalyst-auto-qemu-mips-common
+
+SETS=${SETS_O32}
diff --git a/tools/catalyst-auto-qemu-mips-2.conf b/tools/catalyst-auto-qemu-mips-2.conf
new file mode 100644
index 00000000..c40c6bc9
--- /dev/null
+++ b/tools/catalyst-auto-qemu-mips-2.conf
@@ -0,0 +1,4 @@
+
+source ${REPO_DIR}/tools/catalyst-auto-qemu-mips-common
+
+SETS=${SETS_N32}
diff --git a/tools/catalyst-auto-qemu-mips-3.conf b/tools/catalyst-auto-qemu-mips-3.conf
new file mode 100644
index 00000000..1321408b
--- /dev/null
+++ b/tools/catalyst-auto-qemu-mips-3.conf
@@ -0,0 +1,4 @@
+
+source ${REPO_DIR}/tools/catalyst-auto-qemu-mips-common
+
+SETS=${SETS_N64}
diff --git a/tools/catalyst-auto-qemu-mips-4.conf b/tools/catalyst-auto-qemu-mips-4.conf
new file mode 100644
index 00000000..690ca4f9
--- /dev/null
+++ b/tools/catalyst-auto-qemu-mips-4.conf
@@ -0,0 +1,4 @@
+
+source ${REPO_DIR}/tools/catalyst-auto-qemu-mips-common
+
+SETS=${SETS_MULTI}
diff --git a/tools/catalyst-auto-qemu-mips-common b/tools/catalyst-auto-qemu-mips-common
index 1c2e0592..51c0770e 100644
--- a/tools/catalyst-auto-qemu-mips-common
+++ b/tools/catalyst-auto-qemu-mips-common
@@ -39,6 +39,45 @@ SETS_LE="
mipsel3_multilib_systemd_mu
"
+SETS_O32="
+ mips2_o32_openrc
+ mips2_o32_systemd
+ mips2_o32_systemd_mu
+ mipsel2_o32_openrc
+ mipsel2_o32_systemd
+ mipsel2_o32_systemd_mu
+ mipsel3_o32_openrc
+ mipsel3_o32_systemd
+ mipsel3_o32_systemd_mu
+"
+
+SETS_N32="
+ mips3_n32_openrc
+ mips3_n32_systemd
+ mips3_n32_systemd_mu
+ mipsel3_n32_openrc
+ mipsel3_n32_systemd
+ mipsel3_n32_systemd_mu
+"
+
+SETS_N64="
+ mips3_n64_openrc
+ mips3_n64_systemd
+ mips3_n64_systemd_mu
+ mipsel3_n64_openrc
+ mipsel3_n64_systemd
+ mipsel3_n64_systemd_mu
+"
+
+SETS_MULTI="
+ mips3_multilib_openrc
+ mips3_multilib_systemd
+ mips3_multilib_systemd_mu
+ mipsel3_multilib_openrc
+ mipsel3_multilib_systemd
+ mipsel3_multilib_systemd_mu
+"
+
# SETS="${SETS_BE} ${SETS_LE}"
SET_mips2_o32_openrc_SPECS="stage1-mips2-o32-openrc.spec stage3-mips2-o32-openrc.spec"