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authorMichał Górny <mgorny@gentoo.org>2017-08-15 12:23:10 +0200
committerMichał Górny <mgorny@gentoo.org>2017-08-15 14:35:31 +0200
commit9deb7d08ae3d995842418b9171caef4dac1b6335 (patch)
treec9fde6609bb80d3447bac4e5c5b889260565f99d /profiles/desc
parentsys-devel/llvm: Disable RISCV following upstream (diff)
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profiles/desc: Include LLVM_TARGETS for all experimental targets
Diffstat (limited to 'profiles/desc')
-rw-r--r--profiles/desc/llvm_targets.desc7
1 files changed, 5 insertions, 2 deletions
diff --git a/profiles/desc/llvm_targets.desc b/profiles/desc/llvm_targets.desc
index f48ed646f4e..1c65ccad350 100644
--- a/profiles/desc/llvm_targets.desc
+++ b/profiles/desc/llvm_targets.desc
@@ -1,18 +1,21 @@
-# Copyright 1999-2016 Gentoo Foundation.
+# Copyright 1999-2017 Gentoo Foundation.
# Distributed under the terms of the GNU General Public License v2
AArch64 - AArch64 CPU target (arm64 in Gentoo)
AMDGPU - AMDGPU target (supports R600 and GCN GPUs)
ARM - ARM CPU target
+AVR - 8-bit Atmel AVR microcontroller target [EXPERIMENTAL]
BPF - Berkeley Packet Filter target
Hexagon - Qualcomm Hexagon DSP target
Lanai - Lanai CPU target
Mips - MIPS CPU target (includes MIPS64)
MSP430 - MSP430 CPU target (experimental)
+Nios2 - Nios2 CPU target [EXPERIMENTAL]
NVPTX - NVIDIA PTX (GPU) target (32-bit and 64-bit)
PowerPC - PowerPC CPU target (PPC32 and PPC64)
-RISCV - RISC-V CPU target
+RISCV - RISC-V CPU target [EXPERIMENTAL]
Sparc - Sparc CPU target
SystemZ - SystemZ (s390x) CPU target
+WebAssembly - WebAssembly backend [EXPERIMENTAL]
X86 - X86 CPU target (includes amd64)
XCore - XCore CPU target