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authorMichał Górny <mgorny@gentoo.org>2017-08-15 11:45:15 +0200
committerMichał Górny <mgorny@gentoo.org>2017-08-15 14:35:30 +0200
commit22c9919de2a41c7ef158c728ceb55ebc1662166c (patch)
treec39adc63f339ea48e860a0215fe2ce749a1a1cdc /sys-devel/llvm
parentdev-ml/llvm-ocaml: Disable RISCV following upstream (diff)
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sys-devel/llvm: Disable RISCV following upstream
The RISCV target is experimental and was only accidentally added to the main target list. Since it can no longer be enabled the usual way, remove it from the ebuilds for now.
Diffstat (limited to 'sys-devel/llvm')
-rw-r--r--sys-devel/llvm/llvm-5.0.9999.ebuild2
-rw-r--r--sys-devel/llvm/llvm-9999.ebuild2
2 files changed, 2 insertions, 2 deletions
diff --git a/sys-devel/llvm/llvm-5.0.9999.ebuild b/sys-devel/llvm/llvm-5.0.9999.ebuild
index 66aa02b23cc..1ee42880997 100644
--- a/sys-devel/llvm/llvm-5.0.9999.ebuild
+++ b/sys-devel/llvm/llvm-5.0.9999.ebuild
@@ -20,7 +20,7 @@ EGIT_BRANCH="release_50"
# Keep in sync with CMakeLists.txt
ALL_LLVM_TARGETS=( AArch64 AMDGPU ARM BPF Hexagon Lanai Mips MSP430
- NVPTX PowerPC RISCV Sparc SystemZ X86 XCore )
+ NVPTX PowerPC Sparc SystemZ X86 XCore )
ALL_LLVM_TARGETS=( "${ALL_LLVM_TARGETS[@]/#/llvm_targets_}" )
# Additional licenses:
diff --git a/sys-devel/llvm/llvm-9999.ebuild b/sys-devel/llvm/llvm-9999.ebuild
index d5e7da2b501..65914f3a340 100644
--- a/sys-devel/llvm/llvm-9999.ebuild
+++ b/sys-devel/llvm/llvm-9999.ebuild
@@ -19,7 +19,7 @@ EGIT_REPO_URI="https://git.llvm.org/git/llvm.git
# Keep in sync with CMakeLists.txt
ALL_LLVM_TARGETS=( AArch64 AMDGPU ARM BPF Hexagon Lanai Mips MSP430
- NVPTX PowerPC RISCV Sparc SystemZ X86 XCore )
+ NVPTX PowerPC Sparc SystemZ X86 XCore )
ALL_LLVM_TARGETS=( "${ALL_LLVM_TARGETS[@]/#/llvm_targets_}" )
# Additional licenses: