From 472224059f9b4847a78f8d3b92d0aa1ae203993d Mon Sep 17 00:00:00 2001 From: Joonas Niilola Date: Tue, 7 Jan 2020 08:18:43 +0200 Subject: sci-electronics/iverilog: use default phase on 9999 Signed-off-by: Joonas Niilola --- sci-electronics/iverilog/iverilog-9999.ebuild | 4 ---- 1 file changed, 4 deletions(-) diff --git a/sci-electronics/iverilog/iverilog-9999.ebuild b/sci-electronics/iverilog/iverilog-9999.ebuild index db4f4df26995..183ed6f2023f 100644 --- a/sci-electronics/iverilog/iverilog-9999.ebuild +++ b/sci-electronics/iverilog/iverilog-9999.ebuild @@ -54,10 +54,6 @@ src_prepare() { gperf -o -i 7 --ignore-case -C -k 1-4,6,9,\$ -H keyword_hash -N check_identifier -t ./lexor_keyword.gperf > lexor_keyword.cc || die } -src_compile() { - default -} - src_install() { local DOCS=( *.txt ) # Default build fails with parallel jobs, -- cgit v1.2.3-65-gdbad