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| author |   Huang Rui <vowstar@gmail.com> | 2020-02-23 14:51:23 +0800 |
|---|---|---|
| committer | Huang Rui <vowstar@gmail.com> | 2020-02-23 14:51:53 +0800 |
| commit | 03fda63eacc4df3eb7217a3e8d68dbb2c6754af7 (patch) | |
| tree | 832eecc76b02adf93bd193c82adb36de25925b32 | |
| parent | sys-cluster/er: new package (diff) | |
| download | guru-03fda63eacc4df3eb7217a3e8d68dbb2c6754af7.tar.gz guru-03fda63eacc4df3eb7217a3e8d68dbb2c6754af7.tar.bz2 guru-03fda63eacc4df3eb7217a3e8d68dbb2c6754af7.zip | |
sci-electronics/verilator: new package 4.026
The fast free Verilog/SystemVerilog simulator
Closes: https://bugs.gentoo.org/354957
Package-Manager: Portage-2.3.89, Repoman-2.3.20
Signed-off-by: Huang Rui <vowstar@gmail.com>
| -rw-r--r-- | sci-electronics/verilator/Manifest | 1 | ||||
| -rw-r--r-- | sci-electronics/verilator/metadata.xml | 19 | ||||
| -rw-r--r-- | sci-electronics/verilator/verilator-4.026.ebuild | 39 |
3 files changed, 59 insertions, 0 deletions
diff --git a/sci-electronics/verilator/Manifest b/sci-electronics/verilator/Manifest new file mode 100644 index 0000000000..a3d4eefb85 --- /dev/null +++ b/sci-electronics/verilator/Manifest @@ -0,0 +1 @@ +DIST verilator-4.026.tar.gz 2404465 BLAKE2B a861c16b706a26bb0d9f879a6ac129eca29cfd36c47d044ba8297ce2f4bfbc3d6a8f68f652a0b7db0542373416e975b2266bbf1ea11b0f949c12c1c5f6706b05 SHA512 cc91c44da39b5b0256adf1d43acad22d07bcdc56636336673916a7b01d39c5fc06603b87a9d9e214497a793d1e9ff198593f915f676c99a32f0853f4b74d0527 diff --git a/sci-electronics/verilator/metadata.xml b/sci-electronics/verilator/metadata.xml new file mode 100644 index 0000000000..94cd7b4e79 --- /dev/null +++ b/sci-electronics/verilator/metadata.xml @@ -0,0 +1,19 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!DOCTYPE pkgmetadata SYSTEM "http://www.gentoo.org/dtd/metadata.dtd"> +<pkgmetadata> + <maintainer type="person"> + <email>vowstar@gmail.com</email> + <name>Huang Rui</name> + </maintainer> + <maintainer type="project"> + <email>proxy-maint@gentoo.org</email> + <name>Proxy Maintainers</name> + </maintainer> + <longdescription> + Verilator, the fastest free Verilog HDL simulator. + Accepts synthesizable Verilog or SystemVerilog + Performs lint code-quality checks + Compiles into multithreaded C++, SystemC, or (soon) C++-under-Python + Creates XML to front-end your own tools + </longdescription> +</pkgmetadata> diff --git a/sci-electronics/verilator/verilator-4.026.ebuild b/sci-electronics/verilator/verilator-4.026.ebuild new file mode 100644 index 0000000000..80f4993cfb --- /dev/null +++ b/sci-electronics/verilator/verilator-4.026.ebuild @@ -0,0 +1,39 @@ +# Copyright 1999-2020 Gentoo Authors +# Distributed under the terms of the GNU General Public License v2 + +EAPI=7 + +inherit autotools + +DESCRIPTION="The fast free Verilog/SystemVerilog simulator" +HOMEPAGE="https://www.veripool.org/wiki/verilator" + +if [[ ${PV} == "9999" ]] ; then + inherit git-r3 + EGIT_REPO_URI="https://git.veripool.org/git/${PN}" +else + SRC_URI="http://www.veripool.org/ftp/${P}.tgz -> ${P}.tar.gz" + KEYWORDS="~alpha ~amd64 ~arm ~arm64 ~hppa ~ia64 ~m68k ~mips ~ppc ~ppc64 ~riscv ~s390 ~sh ~sparc ~x86" +fi + +LICENSE="|| ( Artistic-2 LGPL-3 )" +SLOT="0" + +DEPEND=" + dev-lang/perl + sys-libs/zlib +" + +RDEPEND=" + ${DEPEND} +" + +BDEPEND=" + sys-devel/bison + sys-devel/flex +" + +src_prepare() { + default + eautoconf --force +} |