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+<div class="col-xs-12 col-md-6">
+<h4>Stage archives (~riscv)</h4>
+<div class="list-group">
+ {% include partials/download-link.html type="stage3" arch="riscv" id="rv64_lp64d" title="Stage 3" tag="lp64d | openrc" %}
+ {% include partials/download-link.html type="stage3" arch="riscv" id="rv64_lp64d-systemd" title="Stage 3" tag="lp64d | systemd" %}
+ {% include partials/download-link.html type="stage3" arch="riscv" id="rv64_lp64" title="Stage 3" tag="lp64 | openrc" %}
+ {% include partials/download-link.html type="stage3" arch="riscv" id="rv64_lp64-systemd" title="Stage 3" tag="lp64 | systemd" %}
+</div>
+
+<h4>Details (contents, hashes, and signatures)</h4>
+<p>
+ <a href="https://bouncer.gentoo.org/fetch/root/all/releases/riscv/autobuilds/current-stage3-rv64_lp64d/">Stage 3</a>
+</p>
+</div>
+
+<div class="col-xs-12 col-md-6">
+<h4>Hardware compatibility</h4>
+ <div class="alert alert-info">
+ <strong><span class="fa fa-fw fa-info-circle"></span> Processor compatibility</strong>
+ <p>
+ The <em>lp64d</em> stages can be used on all 64-bit RISC-V processors supporting the <strong>double-precision floating point</strong> instruction set.
+ The <em>lp64</em> stages can be used on all 64-bit RISC-V processors; they require no hardware support for floating point arithmetics.
+ </p>
+ </div>
+ <p>
+ For an overview of the different instruction sets, see, e.g., the <a href="https://en.wikipedia.org/wiki/RISC-V" target="_blank">RISC-V wikipedia page</a>.
+ </p>
+ <p>
+ Additional Gentoo-specific information can be found on the web page of the <a href="https://wiki.gentoo.org/wiki/Project:RISC-V">Gentoo RISC-V project</a>.
+</div>