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authorPalmer Dabbelt <palmer@dabbelt.com>2014-12-09 14:44:28 -0800
committerPalmer Dabbelt <palmer@dabbelt.com>2014-12-09 14:44:28 -0800
commitcbe4633fdfb6dd43ad4005e519172b69cc045f93 (patch)
treefd313805442edbbaca4964f758616aa39ab1f91e
parentTypo in mhng (diff)
downloadpalmer-cbe4633fdfb6dd43ad4005e519172b69cc045f93.tar.gz
palmer-cbe4633fdfb6dd43ad4005e519172b69cc045f93.tar.bz2
palmer-cbe4633fdfb6dd43ad4005e519172b69cc045f93.zip
Update RISC-V ports
Diffstat
-rw-r--r--sys-devel/binutils/Manifest2
-rw-r--r--sys-devel/binutils/files/binutils-2.24-riscv.patch1884
-rw-r--r--sys-devel/gcc/Manifest2
-rw-r--r--sys-devel/gcc/files/gcc-4.9.0-riscv.patch3563
-rw-r--r--sys-libs/glibc/Manifest2
-rw-r--r--sys-libs/glibc/files/glibc-2.20-riscv.patch2716
6 files changed, 3433 insertions, 4736 deletions
diff --git a/sys-devel/binutils/Manifest b/sys-devel/binutils/Manifest
index 29be32d..c4bb39e 100644
--- a/sys-devel/binutils/Manifest
+++ b/sys-devel/binutils/Manifest
@@ -1,4 +1,4 @@
-AUX binutils-2.24-riscv.patch 362123 SHA256 846514e065e68b020fd103044408ed05c26f94ef985051d7149c837278fd3d19 SHA512 cc0c07cb765b01a868ad1540e2c882c327f3509c9226cd849e0470af3f8271f061b532e4951a4ba03745ce56f5ee51160109b211eb6978f0861ab05f32772e2d WHIRLPOOL 963cc3ae97ec5566b0a84e89203b568fea500199da12ffe5046ebf5d266c945100cf91db7b10bd88694bcc45ed6c50c8a2336a46e4b3d19af2686fcb05b53082
+AUX binutils-2.24-riscv.patch 331860 SHA256 3cddb9a64692e6d898e6073b9ede6f250f38930a7aeaee9cc3dec783812d48b6 SHA512 4356fba95e2fee46741ea691772fe8029621432f07cbdd8d2d685f5b384bda3a6a494905379d0585b6f36928e76b0efae509364c70b774b4c0d48f7373e056a8 WHIRLPOOL df98fe503e858f047f4dec80c3b448529cabbf1f0f80e8e0e86aa862385e71952c169b88d8875f7acd41e08ccbbfcf503d5c55faaea564fa696d84e8ca381c70
DIST binutils-2.24-patches-1.4.tar.xz 17488 SHA256 f018f140a52cddb1e4619b5caf4b4a37a27dfb29e8bf29ea5161ab13b33eed13 SHA512 dfd7c38cd978b7d6627579c338bf67641c799ce39936e3475dca3ecf5bade417e3f090253a2326582c64d5743a24f9078794f44e8fd41b6af728f1f375c91d3b WHIRLPOOL d6b414d5e5607fd8b2d0f52b508763110448cfbdcc08be6d7c1412043797bde8ed5fbd9a5ea4c141b7394b2cae0ac2ef24827f67813231129a507f49cbc40245
DIST binutils-2.24.tar.bz2 22716802 SHA256 e5e8c5be9664e7f7f96e0d09919110ab5ad597794f5b1809871177a0f0f14137 SHA512 5ec95ad47d49b12c4558a8db0ca2109d3ee1955e3776057f3330c4506f8f4d1cf5e505fbf8a16b98403a0fcdeaaf986fe0a22be6456247dbdace63ce1f776b12 WHIRLPOOL 619634dfdc73b8f6e9933b4642f5f9faf147c388a6d39283cd7639d83f3d7a601981cf49a787c43c17a942c563f24dc8dcc682138b5d3102a5650e1b9d15bd50
EBUILD binutils-2.24-r3.ebuild 454 SHA256 5e29c1d9976a9bf69f8bfd0e65ae658d11f016293a93c73e632b082745b6691c SHA512 f9ae2f18fb0ada6f4289378f05cb324531693adb367319a8c2202161a7d7bfd53673e385f07cba9fd10c3d3ea29ce259262f7b12e117a2ad670984f4016f3d4a WHIRLPOOL 6b9b9aef25cfbd6deb4eae5b3bc4b4cb5f8fb36d7ee54e92acac525ce7151bc94af20882c1d676dcde22237a2e4608ad5d06d8ba44f567671cc531ca52195a22
diff --git a/sys-devel/binutils/files/binutils-2.24-riscv.patch b/sys-devel/binutils/files/binutils-2.24-riscv.patch
index f99c77a..e20f308 100644
--- a/sys-devel/binutils/files/binutils-2.24-riscv.patch
+++ b/sys-devel/binutils/files/binutils-2.24-riscv.patch
@@ -1,150 +1,6 @@
-diff --git a/bfd/archures.c b/bfd/archures.c
-index 97c540a..9fcbaf7 100644
---- a/bfd/archures.c
-+++ b/bfd/archures.c
-@@ -583,6 +583,7 @@ extern const bfd_arch_info_type bfd_pj_arch;
- extern const bfd_arch_info_type bfd_plugin_arch;
- extern const bfd_arch_info_type bfd_powerpc_archs[];
- #define bfd_powerpc_arch bfd_powerpc_archs[0]
-+extern const bfd_arch_info_type bfd_riscv_arch;
- extern const bfd_arch_info_type bfd_rs6000_arch;
- extern const bfd_arch_info_type bfd_rl78_arch;
- extern const bfd_arch_info_type bfd_rx_arch;
-@@ -669,6 +670,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
- &bfd_or32_arch,
- &bfd_pdp11_arch,
- &bfd_powerpc_arch,
-+ &bfd_riscv_arch,
- &bfd_rs6000_arch,
- &bfd_rl78_arch,
- &bfd_rx_arch,
-diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
-index 756af87..fc2f690 100644
---- a/bfd/bfd-in2.h
-+++ b/bfd/bfd-in2.h
-@@ -2003,6 +2003,9 @@ enum bfd_architecture
- #define bfd_mach_ppc_e6500 5007
- #define bfd_mach_ppc_titan 83
- #define bfd_mach_ppc_vle 84
-+ bfd_arch_riscv, /* RISC-V */
-+#define bfd_mach_riscv32 132
-+#define bfd_mach_riscv64 164
- bfd_arch_rs6000, /* IBM RS/6000 */
- #define bfd_mach_rs6k 6000
- #define bfd_mach_rs6k_rs1 6001
-@@ -5227,6 +5230,40 @@ relative offset from _GLOBAL_OFFSET_TABLE_ */
- value in a word. The relocation is relative offset from */
- BFD_RELOC_MICROBLAZE_32_GOTOFF,
-
-+/* RISC-V relocations */
-+ BFD_RELOC_RISCV_HI20,
-+ BFD_RELOC_RISCV_PCREL_HI20,
-+ BFD_RELOC_RISCV_PCREL_LO12_I,
-+ BFD_RELOC_RISCV_PCREL_LO12_S,
-+ BFD_RELOC_RISCV_LO12_I,
-+ BFD_RELOC_RISCV_LO12_S,
-+ BFD_RELOC_RISCV_GPREL12_I,
-+ BFD_RELOC_RISCV_GPREL12_S,
-+ BFD_RELOC_RISCV_TPREL_HI20,
-+ BFD_RELOC_RISCV_TPREL_LO12_I,
-+ BFD_RELOC_RISCV_TPREL_LO12_S,
-+ BFD_RELOC_RISCV_TPREL_ADD,
-+ BFD_RELOC_RISCV_CALL,
-+ BFD_RELOC_RISCV_CALL_PLT,
-+ BFD_RELOC_RISCV_ADD8,
-+ BFD_RELOC_RISCV_ADD16,
-+ BFD_RELOC_RISCV_ADD32,
-+ BFD_RELOC_RISCV_ADD64,
-+ BFD_RELOC_RISCV_SUB8,
-+ BFD_RELOC_RISCV_SUB16,
-+ BFD_RELOC_RISCV_SUB32,
-+ BFD_RELOC_RISCV_SUB64,
-+ BFD_RELOC_RISCV_GOT_HI20,
-+ BFD_RELOC_RISCV_TLS_GOT_HI20,
-+ BFD_RELOC_RISCV_TLS_GD_HI20,
-+ BFD_RELOC_RISCV_JMP,
-+ BFD_RELOC_RISCV_TLS_DTPMOD32,
-+ BFD_RELOC_RISCV_TLS_DTPREL32,
-+ BFD_RELOC_RISCV_TLS_DTPMOD64,
-+ BFD_RELOC_RISCV_TLS_DTPREL64,
-+ BFD_RELOC_RISCV_TLS_TPREL32,
-+ BFD_RELOC_RISCV_TLS_TPREL64,
-+
- /* This is used to tell the dynamic linker to copy the value out of
- the dynamic object into the runtime process image. */
- BFD_RELOC_MICROBLAZE_COPY,
-diff --git a/bfd/config.bfd b/bfd/config.bfd
-index 5324d39..f15701f 100644
---- a/bfd/config.bfd
-+++ b/bfd/config.bfd
-@@ -114,6 +114,7 @@ or32*) targ_archs=bfd_or32_arch ;;
- pdp11*) targ_archs=bfd_pdp11_arch ;;
- pj*) targ_archs="bfd_pj_arch bfd_i386_arch";;
- powerpc*) targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;;
-+riscv*) targ_archs=bfd_riscv_arch ;;
- rs6000) targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;;
- s390*) targ_archs=bfd_s390_arch ;;
- sh*) targ_archs=bfd_sh_arch ;;
-@@ -1295,6 +1296,14 @@ case "${targ}" in
- targ_defvec=bfd_elf32_rl78_vec
- ;;
-
-+#ifdef BFD64
-+ riscv*-*-*)
-+ targ_defvec=bfd_elf64_riscv_vec
-+ targ_selvecs="bfd_elf32_riscv_vec bfd_elf64_riscv_vec"
-+ want64=true
-+ ;;
-+#endif
-+
- rx-*-elf)
- targ_defvec=bfd_elf32_rx_le_vec
- targ_selvecs="bfd_elf32_rx_be_vec bfd_elf32_rx_le_vec bfd_elf32_rx_be_ns_vec"
-diff --git a/bfd/configure b/bfd/configure
-index 90cd397..b186b60 100755
---- a/bfd/configure
-+++ b/bfd/configure
-@@ -15278,6 +15278,7 @@ do
- bfd_elf32_littlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
- bfd_elf32_littlemips_vxworks_vec)
- tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
-+ bfd_elf32_riscv_vec) tb="$tb elf32-riscv.lo elfxx-riscv.lo elf32.lo $elf" ;;
- bfd_elf32_littlemoxie_vec) tb="$tb elf32-moxie.lo elf32.lo $elf" ;;
- bfd_elf32_littlenios2_vec) tb="$tb elf32-nios2.lo elf32.lo $elf" ;;
- bfd_elf32_m32c_vec) tb="$tb elf32-m32c.lo elf32.lo $elf" ;;
-@@ -15384,6 +15385,7 @@ do
- bfd_elf32_littleaarch64_vec)tb="$tb elf32-aarch64.lo elfxx-aarch64.lo elf-ifunc.lo elf32.lo $elf"; target_size=64 ;;
- bfd_elf64_little_generic_vec) tb="$tb elf64-gen.lo elf64.lo $elf"; target_size=64 ;;
- bfd_elf64_littlemips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
-+ bfd_elf64_riscv_vec) tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf32.lo $elf"; target_size=64 ;;
- bfd_elf64_mmix_vec) tb="$tb elf64-mmix.lo elf64.lo $elf" target_size=64 ;;
- bfd_elf64_powerpc_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf"; target_size=64 ;;
- bfd_elf64_powerpcle_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf" target_size=64 ;;
-diff --git a/bfd/configure.in b/bfd/configure.in
-index 0e88d78..2d9d624 100644
---- a/bfd/configure.in
-+++ b/bfd/configure.in
-@@ -767,6 +767,7 @@ do
- bfd_elf32_littlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
- bfd_elf32_littlemips_vxworks_vec)
- tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
-+ bfd_elf32_riscv_vec) tb="$tb elf32-riscv.lo elfxx-riscv.lo elf32.lo $elf ecofflink.lo" ;;
- bfd_elf32_littlemoxie_vec) tb="$tb elf32-moxie.lo elf32.lo $elf" ;;
- bfd_elf32_littlenios2_vec) tb="$tb elf32-nios2.lo elf32.lo $elf" ;;
- bfd_elf32_m32c_vec) tb="$tb elf32-m32c.lo elf32.lo $elf" ;;
-@@ -873,6 +874,7 @@ do
- bfd_elf32_littleaarch64_vec)tb="$tb elf32-aarch64.lo elfxx-aarch64.lo elf-ifunc.lo elf32.lo $elf"; target_size=64 ;;
- bfd_elf64_little_generic_vec) tb="$tb elf64-gen.lo elf64.lo $elf"; target_size=64 ;;
- bfd_elf64_littlemips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
-+ bfd_elf64_riscv_vec) tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf32.lo $elf"; target_size=64 ;;
- bfd_elf64_mmix_vec) tb="$tb elf64-mmix.lo elf64.lo $elf" target_size=64 ;;
- bfd_elf64_powerpc_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf"; target_size=64 ;;
- bfd_elf64_powerpcle_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf" target_size=64 ;;
-diff --git a/bfd/cpu-riscv.c b/bfd/cpu-riscv.c
-new file mode 100644
-index 0000000..4dbc1a3
---- /dev/null
-+++ b/bfd/cpu-riscv.c
+diff -Nur original-binutils/bfd/cpu-riscv.c binutils/bfd/cpu-riscv.c
+--- original-binutils/bfd/cpu-riscv.c 1969-12-31 16:00:00.000000000 -0800
++++ binutils/bfd/cpu-riscv.c 2014-12-09 14:31:16.735857672 -0800
@@ -0,0 +1,80 @@
+/* BFD backend for RISC-V
+ Copyright 2011-2014 Free Software Foundation, Inc.
@@ -226,23 +82,9 @@ index 0000000..4dbc1a3
+
+const bfd_arch_info_type bfd_riscv_arch =
+N (64, 64, 0, "riscv", TRUE, &arch_info_struct[0]);
-diff --git a/bfd/elf-bfd.h b/bfd/elf-bfd.h
-index add80b3..94b7380 100644
---- a/bfd/elf-bfd.h
-+++ b/bfd/elf-bfd.h
-@@ -432,6 +432,7 @@ enum elf_target_id
- XGATE_ELF_DATA,
- TILEGX_ELF_DATA,
- TILEPRO_ELF_DATA,
-+ RISCV_ELF_DATA,
- GENERIC_ELF_DATA
- };
-
-diff --git a/bfd/elf32-riscv.c b/bfd/elf32-riscv.c
-new file mode 100644
-index 0000000..0dcf7d9
---- /dev/null
-+++ b/bfd/elf32-riscv.c
+diff -Nur original-binutils/bfd/elf32-riscv.c binutils/bfd/elf32-riscv.c
+--- original-binutils/bfd/elf32-riscv.c 1969-12-31 16:00:00.000000000 -0800
++++ binutils/bfd/elf32-riscv.c 2014-12-09 14:32:35.932301937 -0800
@@ -0,0 +1,81 @@
+/* RISC-V-specific support for 32-bit ELF.
+ Copyright 2011-2014 Free Software Foundation, Inc.
@@ -325,11 +167,9 @@ index 0000000..0dcf7d9
+#define elf_backend_default_execstack 0
+
+#include "elf32-target.h"
-diff --git a/bfd/elf64-riscv.c b/bfd/elf64-riscv.c
-new file mode 100644
-index 0000000..5272a6e
---- /dev/null
-+++ b/bfd/elf64-riscv.c
+diff -Nur original-binutils/bfd/elf64-riscv.c binutils/bfd/elf64-riscv.c
+--- original-binutils/bfd/elf64-riscv.c 1969-12-31 16:00:00.000000000 -0800
++++ binutils/bfd/elf64-riscv.c 2014-12-09 14:32:35.932301937 -0800
@@ -0,0 +1,82 @@
+/* RISC-V-specific support for 64-bit ELF.
+ Copyright 2011-2014 Free Software Foundation, Inc.
@@ -413,12 +253,10 @@ index 0000000..5272a6e
+#define elf_backend_default_execstack 0
+
+#include "elf64-target.h"
-diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
-new file mode 100644
-index 0000000..ba98d6a
---- /dev/null
-+++ b/bfd/elfxx-riscv.c
-@@ -0,0 +1,3705 @@
+diff -Nur original-binutils/bfd/elfxx-riscv.c binutils/bfd/elfxx-riscv.c
+--- original-binutils/bfd/elfxx-riscv.c 1969-12-31 16:00:00.000000000 -0800
++++ binutils/bfd/elfxx-riscv.c 2014-12-09 14:38:38.665778707 -0800
+@@ -0,0 +1,3699 @@
+/* RISC-V-specific support for ELF.
+ Copyright 2011-2014 Free Software Foundation, Inc.
+
@@ -1289,12 +1127,6 @@ index 0000000..ba98d6a
+ + (plt_index * GOT_ENTRY_SIZE (info));
+}
+
-+#define X_V0 16
-+#define X_V1 17
-+#define X_T0 26
-+#define X_T1 27
-+#define X_T2 28
-+
+#define MATCH_LREG(abfd) (ABI_64_P (abfd) ? MATCH_LD : MATCH_LW)
+#define MATCH_SREG(abfd) (ABI_64_P (abfd) ? MATCH_SD : MATCH_SW)
+
@@ -1307,22 +1139,22 @@ index 0000000..ba98d6a
+ int regbytes = ABI_64_P(abfd) ? 8 : 4;
+
+ /* auipc t2, %hi(.got.plt)
-+ sub v0, v0, v1 # shifted .got.plt offset + hdr size + 12
-+ l[w|d] v1, %lo(.got.plt)(t2) # _dl_runtime_resolve
-+ addi v0, v0, -(hdr size + 12) # shifted .got.plt offset
++ sub t1, t1, t0 # shifted .got.plt offset + hdr size + 12
++ l[w|d] t3, %lo(.got.plt)(t2) # _dl_runtime_resolve
++ addi t1, t1, -(hdr size + 12) # shifted .got.plt offset
+ addi t0, t2, %lo(.got.plt) # &.got.plt
-+ srli t1, v0, log2(16/PTRSIZE) # .got.plt offset
++ srli t1, t1, log2(16/PTRSIZE) # .got.plt offset
+ l[w|d] t0, PTRSIZE(t0) # link map
-+ jr v1 */
++ jr t3 */
+
+ entry[0] = RISCV_UTYPE(AUIPC, X_T2, RISCV_PCREL_HIGH_PART(gotplt_addr, addr));
-+ entry[1] = RISCV_RTYPE(SUB, X_V0, X_V0, X_V1);
-+ entry[2] = RISCV_ITYPE(LREG(abfd), X_V1, X_T2, RISCV_PCREL_LOW_PART(gotplt_addr, addr));
-+ entry[3] = RISCV_ITYPE(ADDI, X_V0, X_V0, -(PLT_HEADER_SIZE + 12));
++ entry[1] = RISCV_RTYPE(SUB, X_T1, X_T1, X_T0);
++ entry[2] = RISCV_ITYPE(LREG(abfd), X_T3, X_T2, RISCV_PCREL_LOW_PART(gotplt_addr, addr));
++ entry[3] = RISCV_ITYPE(ADDI, X_T1, X_T1, -(PLT_HEADER_SIZE + 12));
+ entry[4] = RISCV_ITYPE(ADDI, X_T0, X_T2, RISCV_PCREL_LOW_PART(gotplt_addr, addr));
-+ entry[5] = RISCV_ITYPE(SRLI, X_T1, X_V0, regbytes == 4 ? 2 : 1);
++ entry[5] = RISCV_ITYPE(SRLI, X_T1, X_T1, regbytes == 4 ? 2 : 1);
+ entry[6] = RISCV_ITYPE(LREG(abfd), X_T0, X_T0, regbytes);
-+ entry[7] = RISCV_ITYPE(JALR, 0, X_V1, 0);
++ entry[7] = RISCV_ITYPE(JALR, 0, X_T3, 0);
+}
+
+/* The format of subsequent PLT entries. */
@@ -1331,14 +1163,14 @@ index 0000000..ba98d6a
+riscv_make_plt_entry(bfd* abfd, bfd_vma got_address, bfd_vma addr,
+ uint32_t *entry)
+{
-+ /* auipc v0, %hi(.got.plt entry)
-+ l[w|d] v1, %lo(.got.plt entry)(v0)
-+ jalr v0, v1
++ /* auipc t1, %hi(.got.plt entry)
++ l[w|d] t0, %lo(.got.plt entry)(t1)
++ jalr t1, t0
+ nop */
+
-+ entry[0] = RISCV_UTYPE(AUIPC, X_V0, RISCV_PCREL_HIGH_PART(got_address, addr));
-+ entry[1] = RISCV_ITYPE(LREG(abfd), X_V1, X_V0, RISCV_PCREL_LOW_PART(got_address, addr));
-+ entry[2] = RISCV_ITYPE(JALR, X_V0, X_V1, 0);
++ entry[0] = RISCV_UTYPE (AUIPC, X_T1, RISCV_PCREL_HIGH_PART (got_address, addr));
++ entry[1] = RISCV_ITYPE(LREG(abfd), X_T0, X_T1, RISCV_PCREL_LOW_PART(got_address, addr));
++ entry[2] = RISCV_ITYPE(JALR, X_T1, X_T0, 0);
+ entry[3] = RISCV_NOP;
+}
+
@@ -3033,7 +2865,7 @@ index 0000000..ba98d6a
+ /* We can use tp as the base register. */
+ bfd_vma insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
+ insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
-+ insn |= TP_REG << OP_SH_RS1;
++ insn |= X_TP << OP_SH_RS1;
+ bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
+ }
+ break;
@@ -3049,7 +2881,7 @@ index 0000000..ba98d6a
+ bfd_vma insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
+ insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
+ if (gp != 0)
-+ insn |= GP_REG << OP_SH_RS1;
++ insn |= X_GP << OP_SH_RS1;
+ bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
+ }
+ break;
@@ -4124,11 +3956,9 @@ index 0000000..ba98d6a
+
+ return FALSE;
+}
-diff --git a/bfd/elfxx-riscv.h b/bfd/elfxx-riscv.h
-new file mode 100644
-index 0000000..59643c0
---- /dev/null
-+++ b/bfd/elfxx-riscv.h
+diff -Nur original-binutils/bfd/elfxx-riscv.h binutils/bfd/elfxx-riscv.h
+--- original-binutils/bfd/elfxx-riscv.h 1969-12-31 16:00:00.000000000 -0800
++++ binutils/bfd/elfxx-riscv.h 2014-12-09 14:32:35.932301937 -0800
@@ -0,0 +1,98 @@
+/* RISC-V ELF specific backend routines.
+ Copyright 2011-2014 Free Software Foundation, Inc.
@@ -4228,195 +4058,10 @@ index 0000000..59643c0
+extern bfd_boolean
+_bfd_riscv_relax_section (bfd *, asection *, struct bfd_link_info *,
+ bfd_boolean *);
-diff --git a/bfd/targets.c b/bfd/targets.c
-index b117bfe..f66f59f 100644
---- a/bfd/targets.c
-+++ b/bfd/targets.c
-@@ -681,6 +681,7 @@ extern const bfd_target bfd_elf32_powerpc_vec;
- extern const bfd_target bfd_elf32_powerpcle_vec;
- extern const bfd_target bfd_elf32_powerpc_freebsd_vec;
- extern const bfd_target bfd_elf32_powerpc_vxworks_vec;
-+extern const bfd_target bfd_elf32_riscv_vec;
- extern const bfd_target bfd_elf32_rl78_vec;
- extern const bfd_target bfd_elf32_rx_le_vec;
- extern const bfd_target bfd_elf32_rx_be_vec;
-@@ -751,6 +752,7 @@ extern const bfd_target bfd_elf64_mmix_vec;
- extern const bfd_target bfd_elf64_powerpc_vec;
- extern const bfd_target bfd_elf64_powerpcle_vec;
- extern const bfd_target bfd_elf64_powerpc_freebsd_vec;
-+extern const bfd_target bfd_elf64_riscv_vec;
- extern const bfd_target bfd_elf64_s390_vec;
- extern const bfd_target bfd_elf64_sh64_vec;
- extern const bfd_target bfd_elf64_sh64l_vec;
-diff --git a/binutils/readelf.c b/binutils/readelf.c
-index 61ea0ad..e68b363 100644
---- a/binutils/readelf.c
-+++ b/binutils/readelf.c
-@@ -125,6 +125,7 @@
- #include "elf/metag.h"
- #include "elf/microblaze.h"
- #include "elf/mips.h"
-+#include "elf/riscv.h"
- #include "elf/mmix.h"
- #include "elf/mn10200.h"
- #include "elf/mn10300.h"
-@@ -629,6 +630,7 @@ guess_is_rela (unsigned int e_machine)
- case EM_NIOS32:
- case EM_PPC64:
- case EM_PPC:
-+ case EM_RISCV:
- case EM_RL78:
- case EM_RX:
- case EM_S390:
-@@ -1157,6 +1159,10 @@ dump_relocations (FILE * file,
- rtype = elf_mips_reloc_type (type);
- break;
-
-+ case EM_RISCV:
-+ rtype = elf_riscv_reloc_type (type);
-+ break;
-+
- case EM_ALPHA:
- rtype = elf_alpha_reloc_type (type);
- break;
-@@ -2072,6 +2078,7 @@ get_machine_name (unsigned e_machine)
- case EM_CR16:
- case EM_MICROBLAZE:
- case EM_MICROBLAZE_OLD: return "Xilinx MicroBlaze";
-+ case EM_RISCV: return "RISC-V";
- case EM_RL78: return "Renesas RL78";
- case EM_RX: return "Renesas RX";
- case EM_METAG: return "Imagination Technologies Meta processor architecture";
-@@ -2649,6 +2656,14 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
- }
- break;
-
-+ case EM_RISCV:
-+ {
-+ unsigned int riscv_extension = EF_GET_RISCV_EXT(e_flags);
-+ strcat (buf, ", ");
-+ strcat (buf, riscv_elf_flag_to_name (riscv_extension));
-+ }
-+ break;
-+
- case EM_SH:
- switch ((e_flags & EF_SH_MACH_MASK))
- {
-@@ -10274,6 +10289,8 @@ is_32bit_abs_reloc (unsigned int reloc_type)
- return reloc_type == 1; /* R_PPC64_ADDR32. */
- case EM_PPC:
- return reloc_type == 1; /* R_PPC_ADDR32. */
-+ case EM_RISCV:
-+ return reloc_type == 1; /* R_RISCV_32. */
- case EM_RL78:
- return reloc_type == 1; /* R_RL78_DIR32. */
- case EM_RX:
-@@ -10407,6 +10424,8 @@ is_64bit_abs_reloc (unsigned int reloc_type)
- return reloc_type == 80; /* R_PARISC_DIR64. */
- case EM_PPC64:
- return reloc_type == 38; /* R_PPC64_ADDR64. */
-+ case EM_RISCV:
-+ return reloc_type == 2; /* R_RISCV_64. */
- case EM_SPARC32PLUS:
- case EM_SPARCV9:
- case EM_SPARC:
-@@ -10551,6 +10570,7 @@ is_none_reloc (unsigned int reloc_type)
- case EM_ADAPTEVA_EPIPHANY:
- case EM_PPC: /* R_PPC_NONE. */
- case EM_PPC64: /* R_PPC64_NONE. */
-+ case EM_RISCV: /* R_RISCV_NONE. */
- case EM_ARM: /* R_ARM_NONE. */
- case EM_IA_64: /* R_IA64_NONE. */
- case EM_SH: /* R_SH_NONE. */
-diff --git a/config.sub b/config.sub
-index 61cb4bc..d6e23cb 100755
---- a/config.sub
-+++ b/config.sub
-@@ -334,6 +334,9 @@ case $basic_machine in
- ms1)
- basic_machine=mt-unknown
- ;;
-+ riscv)
-+ basic_machine=riscv-ucb
-+ ;;
-
- strongarm | thumb | xscale)
- basic_machine=arm-unknown
-diff --git a/gas/Makefile.am b/gas/Makefile.am
-index b85755d..15bf781 100644
---- a/gas/Makefile.am
-+++ b/gas/Makefile.am
-@@ -171,6 +171,7 @@ TARGET_CPU_CFILES = \
- config/tc-pdp11.c \
- config/tc-pj.c \
- config/tc-ppc.c \
-+ config/tc-riscv.c \
- config/tc-rl78.c \
- config/tc-rx.c \
- config/tc-s390.c \
-@@ -242,6 +243,7 @@ TARGET_CPU_HFILES = \
- config/tc-pdp11.h \
- config/tc-pj.h \
- config/tc-ppc.h \
-+ config/tc-riscv.h \
- config/tc-rl78.h \
- config/tc-rx.h \
- config/tc-s390.h \
-diff --git a/gas/Makefile.in b/gas/Makefile.in
-index 89ce4f5..c8919b9 100644
---- a/gas/Makefile.in
-+++ b/gas/Makefile.in
-@@ -440,6 +440,7 @@ TARGET_CPU_CFILES = \
- config/tc-pdp11.c \
- config/tc-pj.c \
- config/tc-ppc.c \
-+ config/tc-riscv.c \
- config/tc-rl78.c \
- config/tc-rx.c \
- config/tc-s390.c \
-@@ -511,6 +512,7 @@ TARGET_CPU_HFILES = \
- config/tc-pdp11.h \
- config/tc-pj.h \
- config/tc-ppc.h \
-+ config/tc-riscv.h \
- config/tc-rl78.h \
- config/tc-rx.h \
- config/tc-s390.h \
-@@ -861,6 +863,7 @@ distclean-compile:
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-pdp11.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-pj.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-ppc.Po@am__quote@
-+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-riscv.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-rl78.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-rx.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-s390.Po@am__quote@
-@@ -1566,6 +1569,20 @@ tc-ppc.obj: config/tc-ppc.c
- @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
- @am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-ppc.obj `if test -f 'config/tc-ppc.c'; then $(CYGPATH_W) 'config/tc-ppc.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-ppc.c'; fi`
-
-+tc-riscv.o: config/tc-riscv.c
-+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-riscv.o -MD -MP -MF $(DEPDIR)/tc-riscv.Tpo -c -o tc-riscv.o `test -f 'config/tc-riscv.c' || echo '$(srcdir)/'`config/tc-riscv.c
-+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-riscv.Tpo $(DEPDIR)/tc-riscv.Po
-+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-riscv.c' object='tc-riscv.o' libtool=no @AMDEPBACKSLASH@
-+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
-+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-riscv.o `test -f 'config/tc-riscv.c' || echo '$(srcdir)/'`config/tc-riscv.c
-+
-+tc-riscv.obj: config/tc-riscv.c
-+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-riscv.obj -MD -MP -MF $(DEPDIR)/tc-riscv.Tpo -c -o tc-riscv.obj `if test -f 'config/tc-riscv.c'; then $(CYGPATH_W) 'config/tc-riscv.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-riscv.c'; fi`
-+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-riscv.Tpo $(DEPDIR)/tc-riscv.Po
-+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-riscv.c' object='tc-riscv.obj' libtool=no @AMDEPBACKSLASH@
-+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
-+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-riscv.obj `if test -f 'config/tc-riscv.c'; then $(CYGPATH_W) 'config/tc-riscv.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-riscv.c'; fi`
-+
- tc-rl78.o: config/tc-rl78.c
- @am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-rl78.o -MD -MP -MF $(DEPDIR)/tc-rl78.Tpo -c -o tc-rl78.o `test -f 'config/tc-rl78.c' || echo '$(srcdir)/'`config/tc-rl78.c
- @am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-rl78.Tpo $(DEPDIR)/tc-rl78.Po
-diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
-new file mode 100644
-index 0000000..1016819
---- /dev/null
-+++ b/gas/config/tc-riscv.c
-@@ -0,0 +1,2425 @@
+diff -Nur original-binutils/gas/config/tc-riscv.c binutils/gas/config/tc-riscv.c
+--- original-binutils/gas/config/tc-riscv.c 1969-12-31 16:00:00.000000000 -0800
++++ binutils/gas/config/tc-riscv.c 2014-12-09 14:38:38.665778707 -0800
+@@ -0,0 +1,2177 @@
+/* tc-riscv.c -- RISC-V assembler
+ Copyright 2011-2014 Free Software Foundation, Inc.
+
@@ -4455,9 +4100,6 @@ index 0000000..1016819
+#include <execinfo.h>
+#include <stdint.h>
+
-+#define ZERO 0
-+#define SP 14
-+
+/* Information about an instruction, including its format, operands
+ and fixups. */
+struct riscv_cl_insn
@@ -4825,278 +4467,42 @@ index 0000000..1016819
+ unsigned int num;
+};
+
-+#define RNUM_MASK 0x000fff
-+#define RTYPE_NUM 0x001000
-+#define RTYPE_FPU 0x002000
-+#define RTYPE_VEC 0x004000
-+#define RTYPE_GP 0x008000
-+#define RTYPE_CP0 0x010000
-+#define RTYPE_VGR_REG 0x020000
-+#define RTYPE_VFP_REG 0x040000
-+
-+#define X_REGISTER_NUMBERS \
-+ {"x0", RTYPE_NUM | 0}, \
-+ {"x1", RTYPE_NUM | 1}, \
-+ {"x2", RTYPE_NUM | 2}, \
-+ {"x3", RTYPE_NUM | 3}, \
-+ {"x4", RTYPE_NUM | 4}, \
-+ {"x5", RTYPE_NUM | 5}, \
-+ {"x6", RTYPE_NUM | 6}, \
-+ {"x7", RTYPE_NUM | 7}, \
-+ {"x8", RTYPE_NUM | 8}, \
-+ {"x9", RTYPE_NUM | 9}, \
-+ {"x10", RTYPE_NUM | 10}, \
-+ {"x11", RTYPE_NUM | 11}, \
-+ {"x12", RTYPE_NUM | 12}, \
-+ {"x13", RTYPE_NUM | 13}, \
-+ {"x14", RTYPE_NUM | 14}, \
-+ {"x15", RTYPE_NUM | 15}, \
-+ {"x16", RTYPE_NUM | 16}, \
-+ {"x17", RTYPE_NUM | 17}, \
-+ {"x18", RTYPE_NUM | 18}, \
-+ {"x19", RTYPE_NUM | 19}, \
-+ {"x20", RTYPE_NUM | 20}, \
-+ {"x21", RTYPE_NUM | 21}, \
-+ {"x22", RTYPE_NUM | 22}, \
-+ {"x23", RTYPE_NUM | 23}, \
-+ {"x24", RTYPE_NUM | 24}, \
-+ {"x25", RTYPE_NUM | 25}, \
-+ {"x26", RTYPE_NUM | 26}, \
-+ {"x27", RTYPE_NUM | 27}, \
-+ {"x28", RTYPE_NUM | 28}, \
-+ {"x29", RTYPE_NUM | 29}, \
-+ {"x30", RTYPE_NUM | 30}, \
-+ {"x31", RTYPE_NUM | 31}
-+
-+#define F_REGISTER_NUMBERS \
-+ {"f0", RTYPE_FPU | 0}, \
-+ {"f1", RTYPE_FPU | 1}, \
-+ {"f2", RTYPE_FPU | 2}, \
-+ {"f3", RTYPE_FPU | 3}, \
-+ {"f4", RTYPE_FPU | 4}, \
-+ {"f5", RTYPE_FPU | 5}, \
-+ {"f6", RTYPE_FPU | 6}, \
-+ {"f7", RTYPE_FPU | 7}, \
-+ {"f8", RTYPE_FPU | 8}, \
-+ {"f9", RTYPE_FPU | 9}, \
-+ {"f10", RTYPE_FPU | 10}, \
-+ {"f11", RTYPE_FPU | 11}, \
-+ {"f12", RTYPE_FPU | 12}, \
-+ {"f13", RTYPE_FPU | 13}, \
-+ {"f14", RTYPE_FPU | 14}, \
-+ {"f15", RTYPE_FPU | 15}, \
-+ {"f16", RTYPE_FPU | 16}, \
-+ {"f17", RTYPE_FPU | 17}, \
-+ {"f18", RTYPE_FPU | 18}, \
-+ {"f19", RTYPE_FPU | 19}, \
-+ {"f20", RTYPE_FPU | 20}, \
-+ {"f21", RTYPE_FPU | 21}, \
-+ {"f22", RTYPE_FPU | 22}, \
-+ {"f23", RTYPE_FPU | 23}, \
-+ {"f24", RTYPE_FPU | 24}, \
-+ {"f25", RTYPE_FPU | 25}, \
-+ {"f26", RTYPE_FPU | 26}, \
-+ {"f27", RTYPE_FPU | 27}, \
-+ {"f28", RTYPE_FPU | 28}, \
-+ {"f29", RTYPE_FPU | 29}, \
-+ {"f30", RTYPE_FPU | 30}, \
-+ {"f31", RTYPE_FPU | 31}
-+
-+/* Remaining symbolic register names */
-+#define X_REGISTER_NAMES \
-+ { "zero", 0 | RTYPE_GP }, \
-+ { "ra", 1 | RTYPE_GP }, \
-+ { "s0", 2 | RTYPE_GP }, \
-+ { "s1", 3 | RTYPE_GP }, \
-+ { "s2", 4 | RTYPE_GP }, \
-+ { "s3", 5 | RTYPE_GP }, \
-+ { "s4", 6 | RTYPE_GP }, \
-+ { "s5", 7 | RTYPE_GP }, \
-+ { "s6", 8 | RTYPE_GP }, \
-+ { "s7", 9 | RTYPE_GP }, \
-+ { "s8", 10 | RTYPE_GP }, \
-+ { "s9", 11 | RTYPE_GP }, \
-+ { "s10", 12 | RTYPE_GP }, \
-+ { "s11", 13 | RTYPE_GP }, \
-+ { "sp", 14 | RTYPE_GP }, \
-+ { "tp", 15 | RTYPE_GP }, \
-+ { "v0", 16 | RTYPE_GP }, \
-+ { "v1", 17 | RTYPE_GP }, \
-+ { "a0", 18 | RTYPE_GP }, \
-+ { "a1", 19 | RTYPE_GP }, \
-+ { "a2", 20 | RTYPE_GP }, \
-+ { "a3", 21 | RTYPE_GP }, \
-+ { "a4", 22 | RTYPE_GP }, \
-+ { "a5", 23 | RTYPE_GP }, \
-+ { "a6", 24 | RTYPE_GP }, \
-+ { "a7", 25 | RTYPE_GP }, \
-+ { "t0", 26 | RTYPE_GP }, \
-+ { "t1", 27 | RTYPE_GP }, \
-+ { "t2", 28 | RTYPE_GP }, \
-+ { "t3", 29 | RTYPE_GP }, \
-+ { "t4", 30 | RTYPE_GP }, \
-+ { "gp", 31 | RTYPE_GP }
-+
-+#define F_REGISTER_NAMES \
-+ { "fs0", 0 | RTYPE_FPU }, \
-+ { "fs1", 1 | RTYPE_FPU }, \
-+ { "fs2", 2 | RTYPE_FPU }, \
-+ { "fs3", 3 | RTYPE_FPU }, \
-+ { "fs4", 4 | RTYPE_FPU }, \
-+ { "fs5", 5 | RTYPE_FPU }, \
-+ { "fs6", 6 | RTYPE_FPU }, \
-+ { "fs7", 7 | RTYPE_FPU }, \
-+ { "fs8", 8 | RTYPE_FPU }, \
-+ { "fs9", 9 | RTYPE_FPU }, \
-+ { "fs10", 10 | RTYPE_FPU }, \
-+ { "fs11", 11 | RTYPE_FPU }, \
-+ { "fs12", 12 | RTYPE_FPU }, \
-+ { "fs13", 13 | RTYPE_FPU }, \
-+ { "fs14", 14 | RTYPE_FPU }, \
-+ { "fs15", 15 | RTYPE_FPU }, \
-+ { "fv0", 16 | RTYPE_FPU }, \
-+ { "fv1", 17 | RTYPE_FPU }, \
-+ { "fa0", 18 | RTYPE_FPU }, \
-+ { "fa1", 19 | RTYPE_FPU }, \
-+ { "fa2", 20 | RTYPE_FPU }, \
-+ { "fa3", 21 | RTYPE_FPU }, \
-+ { "fa4", 22 | RTYPE_FPU }, \
-+ { "fa5", 23 | RTYPE_FPU }, \
-+ { "fa6", 24 | RTYPE_FPU }, \
-+ { "fa7", 25 | RTYPE_FPU }, \
-+ { "ft0", 26 | RTYPE_FPU }, \
-+ { "ft1", 27 | RTYPE_FPU }, \
-+ { "ft2", 28 | RTYPE_FPU }, \
-+ { "ft3", 29 | RTYPE_FPU }, \
-+ { "ft4", 30 | RTYPE_FPU }, \
-+ { "ft5", 31 | RTYPE_FPU }
-+
-+#define RISCV_VEC_GR_REGISTER_NAMES \
-+ {"vx0", RTYPE_VGR_REG | 0}, \
-+ {"vx1", RTYPE_VGR_REG | 1}, \
-+ {"vx2", RTYPE_VGR_REG | 2}, \
-+ {"vx3", RTYPE_VGR_REG | 3}, \
-+ {"vx4", RTYPE_VGR_REG | 4}, \
-+ {"vx5", RTYPE_VGR_REG | 5}, \
-+ {"vx6", RTYPE_VGR_REG | 6}, \
-+ {"vx7", RTYPE_VGR_REG | 7}, \
-+ {"vx8", RTYPE_VGR_REG | 8}, \
-+ {"vx9", RTYPE_VGR_REG | 9}, \
-+ {"vx10", RTYPE_VGR_REG | 10}, \
-+ {"vx11", RTYPE_VGR_REG | 11}, \
-+ {"vx12", RTYPE_VGR_REG | 12}, \
-+ {"vx13", RTYPE_VGR_REG | 13}, \
-+ {"vx14", RTYPE_VGR_REG | 14}, \
-+ {"vx15", RTYPE_VGR_REG | 15}, \
-+ {"vx16", RTYPE_VGR_REG | 16}, \
-+ {"vx17", RTYPE_VGR_REG | 17}, \
-+ {"vx18", RTYPE_VGR_REG | 18}, \
-+ {"vx19", RTYPE_VGR_REG | 19}, \
-+ {"vx20", RTYPE_VGR_REG | 20}, \
-+ {"vx21", RTYPE_VGR_REG | 21}, \
-+ {"vx22", RTYPE_VGR_REG | 22}, \
-+ {"vx23", RTYPE_VGR_REG | 23}, \
-+ {"vx24", RTYPE_VGR_REG | 24}, \
-+ {"vx25", RTYPE_VGR_REG | 25}, \
-+ {"vx26", RTYPE_VGR_REG | 26}, \
-+ {"vx27", RTYPE_VGR_REG | 27}, \
-+ {"vx28", RTYPE_VGR_REG | 28}, \
-+ {"vx29", RTYPE_VGR_REG | 29}, \
-+ {"vx30", RTYPE_VGR_REG | 30}, \
-+ {"vx31", RTYPE_VGR_REG | 31}
-+
-+#define RISCV_VEC_GR_SYMBOLIC_REGISTER_NAMES \
-+ {"vzero", RTYPE_VGR_REG | 0}, \
-+ {"vra", RTYPE_VGR_REG | 1}, \
-+ {"vs0", RTYPE_VGR_REG | 2}, \
-+ {"vs1", RTYPE_VGR_REG | 3}, \
-+ {"vs2", RTYPE_VGR_REG | 4}, \
-+ {"vs3", RTYPE_VGR_REG | 5}, \
-+ {"vs4", RTYPE_VGR_REG | 6}, \
-+ {"vs5", RTYPE_VGR_REG | 7}, \
-+ {"vs6", RTYPE_VGR_REG | 8}, \
-+ {"vs7", RTYPE_VGR_REG | 9}, \
-+ {"vs8", RTYPE_VGR_REG | 10}, \
-+ {"vs9", RTYPE_VGR_REG | 11}, \
-+ {"vs10", RTYPE_VGR_REG | 12}, \
-+ {"vs11", RTYPE_VGR_REG | 13}, \
-+ {"vsp", RTYPE_VGR_REG | 14}, \
-+ {"vtp", RTYPE_VGR_REG | 15}, \
-+ {"vv0", RTYPE_VGR_REG | 16}, \
-+ {"vv1", RTYPE_VGR_REG | 17}, \
-+ {"va0", RTYPE_VGR_REG | 18}, \
-+ {"va1", RTYPE_VGR_REG | 19}, \
-+ {"va2", RTYPE_VGR_REG | 20}, \
-+ {"va3", RTYPE_VGR_REG | 21}, \
-+ {"va4", RTYPE_VGR_REG | 22}, \
-+ {"va5", RTYPE_VGR_REG | 23}, \
-+ {"va6", RTYPE_VGR_REG | 24}, \
-+ {"va7", RTYPE_VGR_REG | 25}, \
-+ {"vt0", RTYPE_VGR_REG | 26}, \
-+ {"vt1", RTYPE_VGR_REG | 27}, \
-+ {"vt2", RTYPE_VGR_REG | 28}, \
-+ {"vt3", RTYPE_VGR_REG | 29}, \
-+ {"vt4", RTYPE_VGR_REG | 30}, \
-+ {"vgp", RTYPE_VGR_REG | 31}
-+
-+#define RISCV_VEC_FP_REGISTER_NAMES \
-+ {"vf0", RTYPE_VFP_REG | 0}, \
-+ {"vf1", RTYPE_VFP_REG | 1}, \
-+ {"vf2", RTYPE_VFP_REG | 2}, \
-+ {"vf3", RTYPE_VFP_REG | 3}, \
-+ {"vf4", RTYPE_VFP_REG | 4}, \
-+ {"vf5", RTYPE_VFP_REG | 5}, \
-+ {"vf6", RTYPE_VFP_REG | 6}, \
-+ {"vf7", RTYPE_VFP_REG | 7}, \
-+ {"vf8", RTYPE_VFP_REG | 8}, \
-+ {"vf9", RTYPE_VFP_REG | 9}, \
-+ {"vf10", RTYPE_VFP_REG | 10}, \
-+ {"vf11", RTYPE_VFP_REG | 11}, \
-+ {"vf12", RTYPE_VFP_REG | 12}, \
-+ {"vf13", RTYPE_VFP_REG | 13}, \
-+ {"vf14", RTYPE_VFP_REG | 14}, \
-+ {"vf15", RTYPE_VFP_REG | 15}, \
-+ {"vf16", RTYPE_VFP_REG | 16}, \
-+ {"vf17", RTYPE_VFP_REG | 17}, \
-+ {"vf18", RTYPE_VFP_REG | 18}, \
-+ {"vf19", RTYPE_VFP_REG | 19}, \
-+ {"vf20", RTYPE_VFP_REG | 20}, \
-+ {"vf21", RTYPE_VFP_REG | 21}, \
-+ {"vf22", RTYPE_VFP_REG | 22}, \
-+ {"vf23", RTYPE_VFP_REG | 23}, \
-+ {"vf24", RTYPE_VFP_REG | 24}, \
-+ {"vf25", RTYPE_VFP_REG | 25}, \
-+ {"vf26", RTYPE_VFP_REG | 26}, \
-+ {"vf27", RTYPE_VFP_REG | 27}, \
-+ {"vf28", RTYPE_VFP_REG | 28}, \
-+ {"vf29", RTYPE_VFP_REG | 29}, \
-+ {"vf30", RTYPE_VFP_REG | 30}, \
-+ {"vf31", RTYPE_VFP_REG | 31}
-+
-+static const struct regname reg_names[] = {
-+ X_REGISTER_NUMBERS,
-+ X_REGISTER_NAMES,
-+
-+ F_REGISTER_NUMBERS,
-+ F_REGISTER_NAMES,
-+
-+#define DECLARE_CSR(name, num) {#name, RTYPE_CP0 | num},
-+#include "opcode/riscv-opc.h"
-+#undef DECLARE_CSR
-+
-+ RISCV_VEC_GR_REGISTER_NAMES,
-+ RISCV_VEC_FP_REGISTER_NAMES,
-+ RISCV_VEC_GR_SYMBOLIC_REGISTER_NAMES,
-+
-+ {0, 0}
++enum reg_class {
++ RCLASS_GPR,
++ RCLASS_FPR,
++ RCLASS_CSR,
++ RCLASS_VEC_GPR,
++ RCLASS_VEC_FPR,
++ RCLASS_MAX
+};
+
+static struct hash_control *reg_names_hash = NULL;
+
++#define ENCODE_REG_HASH(cls, n) (void*)(uintptr_t)((n)*RCLASS_MAX + (cls) + 1)
++#define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
++#define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
++
++static void
++hash_reg_name (enum reg_class class, const char *name, unsigned n)
++{
++ void *hash = ENCODE_REG_HASH (class, n);
++ const char *retval = hash_insert (reg_names_hash, name, hash);
++ if (retval != NULL)
++ as_fatal (_("internal error: can't hash `%s': %s"), name, retval);
++}
++
++static void
++hash_reg_names (enum reg_class class, const char * const names[], unsigned n)
++{
++ unsigned i;
++ for (i = 0; i < n; i++)
++ hash_reg_name (class, names[i], i);
++}
++
+static int
-+reg_lookup (char **s, unsigned int types, unsigned int *regnop)
++reg_lookup (char **s, enum reg_class class, unsigned int *regnop)
+{
-+ struct regname *r;
++ void *r;
+ char *e;
+ char save_c;
+ int reg = -1;
@@ -5113,9 +4519,9 @@ index 0000000..1016819
+ *e = '\0';
+
+ /* Look for the register. */
-+ r = (struct regname *) hash_find (reg_names_hash, *s);
-+ if (r != NULL && (r->num & types))
-+ reg = r->num & RNUM_MASK;
++ r = hash_find (reg_names_hash, *s);
++ if (r != NULL && DECODE_REG_CLASS (r) == class)
++ reg = DECODE_REG_NUM (r);
+
+ /* Advance to next token if a register was recognised. */
+ if (reg >= 0)
@@ -5128,11 +4534,12 @@ index 0000000..1016819
+}
+
+static unsigned int
-+reg_lookup_assert (const char *s, unsigned int types)
++reg_lookup_assert (const char *s, enum reg_class class)
+{
+ struct regname *r = (struct regname *) hash_find (reg_names_hash, s);
-+ gas_assert (r != NULL && (r->num & types));
-+ return r->num & RNUM_MASK;
++ if (r == NULL || DECODE_REG_CLASS (r) != class)
++ as_bad (_("unknown register `%s'"), s);
++ return DECODE_REG_NUM (r);
+}
+
+static int
@@ -5297,18 +4704,16 @@ index 0000000..1016819
+ }
+
+ reg_names_hash = hash_new ();
-+ for (i = 0; reg_names[i].name; i++)
-+ {
-+ retval = hash_insert (reg_names_hash, reg_names[i].name,
-+ (void*) &reg_names[i]);
-+ if (retval != NULL)
-+ {
-+ fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
-+ reg_names[i].name, retval);
-+ /* Probably a memory allocation problem? Give up now. */
-+ as_fatal (_("Broken assembler. No assembly attempted."));
-+ }
-+ }
++ hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR);
++ hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
++ hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
++ hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
++ hash_reg_names (RCLASS_VEC_GPR, riscv_vec_gpr_names, NVGPR);
++ hash_reg_names (RCLASS_VEC_FPR, riscv_vec_fpr_names, NVFPR);
++
++#define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num);
++#include "opcode/riscv-opc.h"
++#undef DECLARE_CSR
+
+ /* set the default alignment for the text section (2**2) */
+ record_alignment (text_section, 2);
@@ -5573,7 +4978,7 @@ index 0000000..1016819
+ }
+ else
+ {
-+ int hi_reg = ZERO;
++ int hi_reg = 0;
+
+ if (upper.X_add_number != 0)
+ {
@@ -5581,7 +4986,7 @@ index 0000000..1016819
+ hi_reg = reg;
+ }
+
-+ if (lower.X_add_number != 0 || hi_reg == ZERO)
++ if (lower.X_add_number != 0 || hi_reg == 0)
+ macro_build (ep, ADD32_INSN, "d,s,j", reg, hi_reg,
+ BFD_RELOC_RISCV_LO12_I);
+ }
@@ -5715,9 +5120,9 @@ index 0000000..1016819
+ rd = 0;
+ goto do_call;
+ case M_CALL:
-+ rd = LINK_REG;
++ rd = X_RA;
+do_call:
-+ rs1 = reg_lookup_assert ("t0", RTYPE_GP);
++ rs1 = reg_lookup_assert ("t0", RCLASS_GPR);
+ riscv_call (rd, rs1, &offset_expr, offset_reloc);
+ break;
+
@@ -5871,7 +5276,6 @@ index 0000000..1016819
+ unsigned int regno;
+ char save_c = 0;
+ int argnum;
-+ unsigned int rtype;
+ const struct percent_op_match *p;
+
+ insn_error = NULL;
@@ -6007,49 +5411,49 @@ index 0000000..1016819
+ s = expr_end;
+ continue;
+ case 'd':
-+ ok = reg_lookup( &s, RTYPE_NUM|RTYPE_VGR_REG, &regno );
++ ok = reg_lookup( &s, RCLASS_VEC_GPR, &regno );
+ if ( !ok )
+ as_bad( _( "Invalid vector register" ) );
+ INSERT_OPERAND( VRD, *ip, regno );
+ continue;
+ case 's':
-+ ok = reg_lookup( &s, RTYPE_NUM|RTYPE_VGR_REG, &regno );
++ ok = reg_lookup( &s, RCLASS_VEC_GPR, &regno );
+ if ( !ok )
+ as_bad( _( "Invalid vector register" ) );
+ INSERT_OPERAND( VRS, *ip, regno );
+ continue;
+ case 't':
-+ ok = reg_lookup( &s, RTYPE_NUM|RTYPE_VGR_REG, &regno );
++ ok = reg_lookup( &s, RCLASS_VEC_GPR, &regno );
+ if ( !ok )
+ as_bad( _( "Invalid vector register" ) );
+ INSERT_OPERAND( VRT, *ip, regno );
+ continue;
+ case 'r':
-+ ok = reg_lookup( &s, RTYPE_NUM|RTYPE_VGR_REG, &regno );
++ ok = reg_lookup( &s, RCLASS_VEC_GPR, &regno );
+ if ( !ok )
+ as_bad( _( "Invalid vector register" ) );
+ INSERT_OPERAND( VRR, *ip, regno );
+ continue;
+ case 'D':
-+ ok = reg_lookup( &s, RTYPE_NUM|RTYPE_VFP_REG, &regno );
++ ok = reg_lookup( &s, RCLASS_VEC_FPR, &regno );
+ if ( !ok )
+ as_bad( _( "Invalid vector register" ) );
+ INSERT_OPERAND( VFD, *ip, regno );
+ continue;
+ case 'S':
-+ ok = reg_lookup( &s, RTYPE_NUM|RTYPE_VFP_REG, &regno );
++ ok = reg_lookup( &s, RCLASS_VEC_FPR, &regno );
+ if ( !ok )
+ as_bad( _( "Invalid vector register" ) );
+ INSERT_OPERAND( VFS, *ip, regno );
+ continue;
+ case 'T':
-+ ok = reg_lookup( &s, RTYPE_NUM|RTYPE_VFP_REG, &regno );
++ ok = reg_lookup( &s, RCLASS_VEC_FPR, &regno );
+ if ( !ok )
+ as_bad( _( "Invalid vector register" ) );
+ INSERT_OPERAND( VFT, *ip, regno );
+ continue;
+ case 'R':
-+ ok = reg_lookup( &s, RTYPE_NUM|RTYPE_VFP_REG, &regno );
++ ok = reg_lookup( &s, RCLASS_VEC_FPR, &regno );
+ if ( !ok )
+ as_bad( _( "Invalid vector register" ) );
+ INSERT_OPERAND( VFR, *ip, regno );
@@ -6106,7 +5510,7 @@ index 0000000..1016819
+ continue;
+
+ case 'E': /* Control register. */
-+ ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, &regno);
++ ok = reg_lookup (&s, RCLASS_CSR, &regno);
+ INSERT_OPERAND (CSR, *ip, regno);
+ if (ok)
+ continue;
@@ -6136,7 +5540,7 @@ index 0000000..1016819
+ case 'd': /* destination register */
+ case 's': /* source register */
+ case 't': /* target register */
-+ ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &regno);
++ ok = reg_lookup (&s, RCLASS_GPR, &regno);
+ if (ok)
+ {
+ c = *args;
@@ -6166,8 +5570,7 @@ index 0000000..1016819
+ case 'T': /* floating point rs2 */
+ case 'U': /* floating point rs1 and rs2 */
+ case 'R': /* floating point rs3 */
-+ rtype = RTYPE_FPU;
-+ if (reg_lookup (&s, rtype, &regno))
++ if (reg_lookup (&s, RCLASS_FPR, &regno))
+ {
+ c = *args;
+ if (*s == ' ')
@@ -6780,19 +6183,13 @@ index 0000000..1016819
+void
+riscv_cfi_frame_initial_instructions (void)
+{
-+ cfi_add_CFA_def_cfa_register (SP);
++ cfi_add_CFA_def_cfa_register (X_SP);
+}
+
+int
+tc_riscv_regname_to_dw2regnum (char *regname)
+{
-+ unsigned int regnum = -1;
-+ unsigned int reg;
-+
-+ if (reg_lookup (&regname, RTYPE_GP | RTYPE_NUM, &reg))
-+ regnum = reg;
-+
-+ return regnum;
++ return reg_lookup_assert (regname, RCLASS_GPR);
+}
+
+void
@@ -6842,11 +6239,9 @@ index 0000000..1016819
+
+ pop_insert (riscv_pseudo_table);
+}
-diff --git a/gas/config/tc-riscv.h b/gas/config/tc-riscv.h
-new file mode 100644
-index 0000000..2cd7c78
---- /dev/null
-+++ b/gas/config/tc-riscv.h
+diff -Nur original-binutils/gas/config/tc-riscv.h binutils/gas/config/tc-riscv.h
+--- original-binutils/gas/config/tc-riscv.h 1969-12-31 16:00:00.000000000 -0800
++++ binutils/gas/config/tc-riscv.h 2014-12-09 14:38:38.665778707 -0800
@@ -0,0 +1,105 @@
+/* tc-riscv.h -- header file for tc-riscv.c.
+ Copyright 2011-2014 Free Software Foundation, Inc.
@@ -6946,71 +6341,16 @@ index 0000000..2cd7c78
+#define tc_regname_to_dw2regnum tc_riscv_regname_to_dw2regnum
+extern int tc_riscv_regname_to_dw2regnum (char *regname);
+
-+#define DWARF2_DEFAULT_RETURN_COLUMN LINK_REG
++#define DWARF2_DEFAULT_RETURN_COLUMN X_RA
+#define DWARF2_CIE_DATA_ALIGNMENT (-4)
+
+#define elf_tc_final_processing riscv_elf_final_processing
+extern void riscv_elf_final_processing (void);
+
+#endif /* TC_RISCV */
-diff --git a/gas/configure.tgt b/gas/configure.tgt
-index 77c1d9b..2961470 100644
---- a/gas/configure.tgt
-+++ b/gas/configure.tgt
-@@ -84,6 +84,7 @@ case ${cpu} in
- pj*) cpu_type=pj endian=big ;;
- powerpc*le*) cpu_type=ppc endian=little ;;
- powerpc*) cpu_type=ppc endian=big ;;
-+ riscv*) cpu_type=riscv endian=little ;;
- rs6000*) cpu_type=ppc ;;
- rl78*) cpu_type=rl78 ;;
- rx) cpu_type=rx ;;
-@@ -375,6 +376,8 @@ case ${generic_target} in
- ppc-*-kaos*) fmt=elf ;;
- ppc-*-lynxos*) fmt=elf em=lynx ;;
-
-+ riscv*-*-*) fmt=elf endian=little em=linux bfd_gas=yes ;;
-+
- s390-*-linux-*) fmt=elf em=linux ;;
- s390-*-tpf*) fmt=elf ;;
-
-diff --git a/include/dis-asm.h b/include/dis-asm.h
-index 78e9fc0..0c21ecd 100644
---- a/include/dis-asm.h
-+++ b/include/dis-asm.h
-@@ -257,6 +257,7 @@ extern int print_insn_little_mips (bfd_vma, disassemble_info *);
- extern int print_insn_little_nios2 (bfd_vma, disassemble_info *);
- extern int print_insn_little_or32 (bfd_vma, disassemble_info *);
- extern int print_insn_little_powerpc (bfd_vma, disassemble_info *);
-+extern int print_insn_riscv (bfd_vma, disassemble_info *);
- extern int print_insn_little_score (bfd_vma, disassemble_info *);
- extern int print_insn_lm32 (bfd_vma, disassemble_info *);
- extern int print_insn_m32c (bfd_vma, disassemble_info *);
-@@ -315,6 +316,7 @@ extern void print_aarch64_disassembler_options (FILE *);
- extern void print_i386_disassembler_options (FILE *);
- extern void print_mips_disassembler_options (FILE *);
- extern void print_ppc_disassembler_options (FILE *);
-+extern void print_riscv_disassembler_options (FILE *);
- extern void print_arm_disassembler_options (FILE *);
- extern void parse_arm_disassembler_option (char *);
- extern void print_s390_disassembler_options (FILE *);
-diff --git a/include/elf/common.h b/include/elf/common.h
-index cd3bcdd..426201e 100644
---- a/include/elf/common.h
-+++ b/include/elf/common.h
-@@ -301,6 +301,7 @@
- #define EM_INTEL207 207 /* Reserved by Intel */
- #define EM_INTEL208 208 /* Reserved by Intel */
- #define EM_INTEL209 209 /* Reserved by Intel */
-+#define EM_RISCV 243 /* Reserved by Intel */
-
- /* If it is necessary to assign new unofficial EM_* values, please pick large
- random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision
-diff --git a/include/elf/riscv.h b/include/elf/riscv.h
-new file mode 100644
-index 0000000..607269e
---- /dev/null
-+++ b/include/elf/riscv.h
+diff -Nur original-binutils/include/elf/riscv.h binutils/include/elf/riscv.h
+--- original-binutils/include/elf/riscv.h 1969-12-31 16:00:00.000000000 -0800
++++ binutils/include/elf/riscv.h 2014-12-09 14:32:35.932301937 -0800
@@ -0,0 +1,137 @@
+/* RISC-V ELF support for BFD.
+ Copyright 2011-2014 Free Software Foundation, Inc.
@@ -7149,11 +6489,334 @@ index 0000000..607269e
+}
+
+#endif /* _ELF_RISCV_H */
-diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
-new file mode 100644
-index 0000000..eb29d3e
---- /dev/null
-+++ b/include/opcode/riscv-opc.h
+diff -Nur original-binutils/include/opcode/riscv.h binutils/include/opcode/riscv.h
+--- original-binutils/include/opcode/riscv.h 1969-12-31 16:00:00.000000000 -0800
++++ binutils/include/opcode/riscv.h 2014-12-09 14:38:38.665778707 -0800
+@@ -0,0 +1,321 @@
++/* riscv.h. RISC-V opcode list for GDB, the GNU debugger.
++ Copyright 2011
++ Free Software Foundation, Inc.
++ Contributed by Andrew Waterman
++
++This file is part of GDB, GAS, and the GNU binutils.
++
++GDB, GAS, and the GNU binutils are free software; you can redistribute
++them and/or modify them under the terms of the GNU General Public
++License as published by the Free Software Foundation; either version
++1, or (at your option) any later version.
++
++GDB, GAS, and the GNU binutils are distributed in the hope that they
++will be useful, but WITHOUT ANY WARRANTY; without even the implied
++warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
++the GNU General Public License for more details.
++
++You should have received a copy of the GNU General Public License
++along with this file; see the file COPYING. If not, write to the Free
++Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
++
++#ifndef _RISCV_H_
++#define _RISCV_H_
++
++#include "riscv-opc.h"
++#include <stdlib.h>
++#include <stdint.h>
++
++/* RVC fields */
++
++#define OP_MASK_CRD 0x1f
++#define OP_SH_CRD 5
++#define OP_MASK_CRS2 0x1f
++#define OP_SH_CRS2 5
++#define OP_MASK_CRS1 0x1f
++#define OP_SH_CRS1 10
++#define OP_MASK_CRDS 0x7
++#define OP_SH_CRDS 13
++#define OP_MASK_CRS2S 0x7
++#define OP_SH_CRS2S 13
++#define OP_MASK_CRS2BS 0x7
++#define OP_SH_CRS2BS 5
++#define OP_MASK_CRS1S 0x7
++#define OP_SH_CRS1S 10
++#define OP_MASK_CIMM6 0x3f
++#define OP_SH_CIMM6 10
++#define OP_MASK_CIMM5 0x1f
++#define OP_SH_CIMM5 5
++#define OP_MASK_CIMM10 0x3ff
++#define OP_SH_CIMM10 5
++
++static const char rvc_rs1_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 };
++#define rvc_rd_regmap rvc_rs1_regmap
++#define rvc_rs2b_regmap rvc_rs1_regmap
++static const char rvc_rs2_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 0 };
++
++typedef uint64_t insn_t;
++
++static inline unsigned int riscv_insn_length (insn_t insn)
++{
++ if ((insn & 0x3) != 3) /* RVC */
++ return 2;
++ if ((insn & 0x1f) != 0x1f) /* base ISA and extensions in 32-bit space */
++ return 4;
++ if ((insn & 0x3f) == 0x1f) /* 48-bit extensions */
++ return 6;
++ if ((insn & 0x7f) == 0x3f) /* 64-bit extensions */
++ return 8;
++ /* longer instructions not supported at the moment */
++ return 2;
++}
++
++static const char * const riscv_rm[8] = {
++ "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn"
++};
++static const char* const riscv_pred_succ[16] = {
++ 0, "w", "r", "rw", "o", "ow", "or", "orw",
++ "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw",
++};
++
++#define RVC_JUMP_BITS 10
++#define RVC_JUMP_ALIGN_BITS 1
++#define RVC_JUMP_ALIGN (1 << RVC_JUMP_ALIGN_BITS)
++#define RVC_JUMP_REACH ((1ULL<<RVC_JUMP_BITS)*RVC_JUMP_ALIGN)
++
++#define RVC_BRANCH_BITS 5
++#define RVC_BRANCH_ALIGN_BITS RVC_JUMP_ALIGN_BITS
++#define RVC_BRANCH_ALIGN (1 << RVC_BRANCH_ALIGN_BITS)
++#define RVC_BRANCH_REACH ((1ULL<<RVC_BRANCH_BITS)*RVC_BRANCH_ALIGN)
++
++#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1))
++#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
++
++#define EXTRACT_ITYPE_IMM(x) \
++ (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))
++#define EXTRACT_STYPE_IMM(x) \
++ (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12))
++#define EXTRACT_SBTYPE_IMM(x) \
++ ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12))
++#define EXTRACT_UTYPE_IMM(x) \
++ ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32))
++#define EXTRACT_UJTYPE_IMM(x) \
++ ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20))
++
++#define ENCODE_ITYPE_IMM(x) \
++ (RV_X(x, 0, 12) << 20)
++#define ENCODE_STYPE_IMM(x) \
++ ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25))
++#define ENCODE_SBTYPE_IMM(x) \
++ ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31))
++#define ENCODE_UTYPE_IMM(x) \
++ (RV_X(x, 12, 20) << 12)
++#define ENCODE_UJTYPE_IMM(x) \
++ ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31))
++
++#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
++#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
++#define VALID_SBTYPE_IMM(x) (EXTRACT_SBTYPE_IMM(ENCODE_SBTYPE_IMM(x)) == (x))
++#define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x))
++#define VALID_UJTYPE_IMM(x) (EXTRACT_UJTYPE_IMM(ENCODE_UJTYPE_IMM(x)) == (x))
++
++#define RISCV_RTYPE(insn, rd, rs1, rs2) \
++ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
++#define RISCV_ITYPE(insn, rd, rs1, imm) \
++ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm))
++#define RISCV_STYPE(insn, rs1, rs2, imm) \
++ ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm))
++#define RISCV_SBTYPE(insn, rs1, rs2, target) \
++ ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_SBTYPE_IMM(target))
++#define RISCV_UTYPE(insn, rd, bigimm) \
++ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm))
++#define RISCV_UJTYPE(insn, rd, target) \
++ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UJTYPE_IMM(target))
++
++#define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0)
++
++#define RISCV_CONST_HIGH_PART(VALUE) \
++ (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
++#define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE))
++#define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC))
++#define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC))
++
++/* RV fields */
++
++#define OP_MASK_OP 0x7f
++#define OP_SH_OP 0
++#define OP_MASK_RS2 0x1f
++#define OP_SH_RS2 20
++#define OP_MASK_RS1 0x1f
++#define OP_SH_RS1 15
++#define OP_MASK_RS3 0x1f
++#define OP_SH_RS3 27
++#define OP_MASK_RD 0x1f
++#define OP_SH_RD 7
++#define OP_MASK_SHAMT 0x3f
++#define OP_SH_SHAMT 20
++#define OP_MASK_SHAMTW 0x1f
++#define OP_SH_SHAMTW 20
++#define OP_MASK_RM 0x7
++#define OP_SH_RM 12
++#define OP_MASK_PRED 0xf
++#define OP_SH_PRED 24
++#define OP_MASK_SUCC 0xf
++#define OP_SH_SUCC 20
++#define OP_MASK_AQ 0x1
++#define OP_SH_AQ 26
++#define OP_MASK_RL 0x1
++#define OP_SH_RL 25
++
++#define OP_MASK_VRD 0x1f
++#define OP_SH_VRD 7
++#define OP_MASK_VRS 0x1f
++#define OP_SH_VRS 15
++#define OP_MASK_VRT 0x1f
++#define OP_SH_VRT 20
++#define OP_MASK_VRR 0x1f
++#define OP_SH_VRR 27
++
++#define OP_MASK_VFD 0x1f
++#define OP_SH_VFD 7
++#define OP_MASK_VFS 0x1f
++#define OP_SH_VFS 15
++#define OP_MASK_VFT 0x1f
++#define OP_SH_VFT 20
++#define OP_MASK_VFR 0x1f
++#define OP_SH_VFR 27
++
++#define OP_MASK_IMMNGPR 0x3f
++#define OP_SH_IMMNGPR 20
++#define OP_MASK_IMMNFPR 0x3f
++#define OP_SH_IMMNFPR 26
++#define OP_MASK_IMMSEGNELM 0x7
++#define OP_SH_IMMSEGNELM 29
++#define OP_MASK_CUSTOM_IMM 0x7f
++#define OP_SH_CUSTOM_IMM 25
++#define OP_MASK_CSR 0xfff
++#define OP_SH_CSR 20
++
++#define X_RA 1
++#define X_SP 2
++#define X_GP 3
++#define X_TP 4
++#define X_T0 5
++#define X_T1 6
++#define X_T2 7
++#define X_T3 28
++
++#define NGPR 32
++#define NFPR 32
++#define NVGPR 32
++#define NVFPR 32
++
++#define RISCV_JUMP_BITS RISCV_BIGIMM_BITS
++#define RISCV_JUMP_ALIGN_BITS 1
++#define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS)
++#define RISCV_JUMP_REACH ((1ULL<<RISCV_JUMP_BITS)*RISCV_JUMP_ALIGN)
++
++#define RISCV_IMM_BITS 12
++#define RISCV_BIGIMM_BITS (32-RISCV_IMM_BITS)
++#define RISCV_IMM_REACH (1LL<<RISCV_IMM_BITS)
++#define RISCV_BIGIMM_REACH (1LL<<RISCV_BIGIMM_BITS)
++#define RISCV_BRANCH_BITS RISCV_IMM_BITS
++#define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS
++#define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS)
++#define RISCV_BRANCH_REACH (RISCV_IMM_REACH*RISCV_BRANCH_ALIGN)
++
++/* This structure holds information for a particular instruction. */
++
++struct riscv_opcode
++{
++ /* The name of the instruction. */
++ const char *name;
++ /* The ISA subset name (I, M, A, F, D, Xextension). */
++ const char *subset;
++ /* A string describing the arguments for this instruction. */
++ const char *args;
++ /* The basic opcode for the instruction. When assembling, this
++ opcode is modified by the arguments to produce the actual opcode
++ that is used. If pinfo is INSN_MACRO, then this is 0. */
++ insn_t match;
++ /* If pinfo is not INSN_MACRO, then this is a bit mask for the
++ relevant portions of the opcode when disassembling. If the
++ actual opcode anded with the match field equals the opcode field,
++ then we have found the correct instruction. If pinfo is
++ INSN_MACRO, then this field is the macro identifier. */
++ insn_t mask;
++ /* A function to determine if a word corresponds to this instruction.
++ Usually, this computes ((word & mask) == match). */
++ int (*match_func)(const struct riscv_opcode *op, insn_t word);
++ /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
++ of bits describing the instruction, notably any relevant hazard
++ information. */
++ unsigned long pinfo;
++};
++
++#define INSN_WRITE_GPR_D 0x00000001
++#define INSN_WRITE_GPR_RA 0x00000004
++#define INSN_WRITE_FPR_D 0x00000008
++#define INSN_READ_GPR_S 0x00000040
++#define INSN_READ_GPR_T 0x00000080
++#define INSN_READ_FPR_S 0x00000100
++#define INSN_READ_FPR_T 0x00000200
++#define INSN_READ_FPR_R 0x00000400
++/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
++#define INSN_ALIAS 0x00001000
++/* Instruction is actually a macro. It should be ignored by the
++ disassembler, and requires special treatment by the assembler. */
++#define INSN_MACRO 0xffffffff
++
++/* This is a list of macro expanded instructions.
++
++ _I appended means immediate
++ _A appended means address
++ _AB appended means address with base register
++ _D appended means 64 bit floating point constant
++ _S appended means 32 bit floating point constant. */
++
++enum
++{
++ M_LA,
++ M_LLA,
++ M_LA_TLS_GD,
++ M_LA_TLS_IE,
++ M_LB,
++ M_LBU,
++ M_LH,
++ M_LHU,
++ M_LW,
++ M_LWU,
++ M_LD,
++ M_SB,
++ M_SH,
++ M_SW,
++ M_SD,
++ M_FLW,
++ M_FLD,
++ M_FSW,
++ M_FSD,
++ M_CALL,
++ M_JUMP,
++ M_J,
++ M_LI,
++ M_VF,
++ M_NUM_MACROS
++};
++
++
++extern const char * const riscv_gpr_names_numeric[NGPR];
++extern const char * const riscv_gpr_names_abi[NGPR];
++extern const char * const riscv_fpr_names_numeric[NFPR];
++extern const char * const riscv_fpr_names_abi[NFPR];
++extern const char * const riscv_vec_gpr_names[NVGPR];
++extern const char * const riscv_vec_fpr_names[NVFPR];
++
++extern const struct riscv_opcode riscv_builtin_opcodes[];
++extern const int bfd_riscv_num_builtin_opcodes;
++extern struct riscv_opcode *riscv_opcodes;
++extern int bfd_riscv_num_opcodes;
++#define NUMOPCODES bfd_riscv_num_opcodes
++
++#endif /* _RISCV_H_ */
+diff -Nur original-binutils/include/opcode/riscv-opc.h binutils/include/opcode/riscv-opc.h
+--- original-binutils/include/opcode/riscv-opc.h 1969-12-31 16:00:00.000000000 -0800
++++ binutils/include/opcode/riscv-opc.h 2014-12-09 14:31:16.735857672 -0800
@@ -0,0 +1,1216 @@
+/* Automatically generated by parse-opcodes */
+#ifndef RISCV_ENCODING_H
@@ -8371,449 +8034,9 @@ index 0000000..eb29d3e
+DECLARE_CAUSE("timeh", CAUSE_TIMEH)
+DECLARE_CAUSE("instreth", CAUSE_INSTRETH)
+#endif
-diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
-new file mode 100644
-index 0000000..91aa07f
---- /dev/null
-+++ b/include/opcode/riscv.h
-@@ -0,0 +1,316 @@
-+/* riscv.h. RISC-V opcode list for GDB, the GNU debugger.
-+ Copyright 2011
-+ Free Software Foundation, Inc.
-+ Contributed by Andrew Waterman
-+
-+This file is part of GDB, GAS, and the GNU binutils.
-+
-+GDB, GAS, and the GNU binutils are free software; you can redistribute
-+them and/or modify them under the terms of the GNU General Public
-+License as published by the Free Software Foundation; either version
-+1, or (at your option) any later version.
-+
-+GDB, GAS, and the GNU binutils are distributed in the hope that they
-+will be useful, but WITHOUT ANY WARRANTY; without even the implied
-+warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
-+the GNU General Public License for more details.
-+
-+You should have received a copy of the GNU General Public License
-+along with this file; see the file COPYING. If not, write to the Free
-+Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
-+
-+#ifndef _RISCV_H_
-+#define _RISCV_H_
-+
-+#include "riscv-opc.h"
-+#include <stdlib.h>
-+#include <stdint.h>
-+
-+/* RVC fields */
-+
-+#define OP_MASK_COP 0x1f
-+#define OP_SH_COP 0
-+#define OP_MASK_CRD 0x1f
-+#define OP_SH_CRD 5
-+#define OP_MASK_CRS2 0x1f
-+#define OP_SH_CRS2 5
-+#define OP_MASK_CRS1 0x1f
-+#define OP_SH_CRS1 10
-+#define OP_MASK_CRDS 0x7
-+#define OP_SH_CRDS 13
-+#define OP_MASK_CRS2S 0x7
-+#define OP_SH_CRS2S 13
-+#define OP_MASK_CRS2BS 0x7
-+#define OP_SH_CRS2BS 5
-+#define OP_MASK_CRS1S 0x7
-+#define OP_SH_CRS1S 10
-+#define OP_MASK_CIMM6 0x3f
-+#define OP_SH_CIMM6 10
-+#define OP_MASK_CIMM5 0x1f
-+#define OP_SH_CIMM5 5
-+#define OP_MASK_CIMM10 0x3ff
-+#define OP_SH_CIMM10 5
-+
-+static const char rvc_rs1_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 };
-+#define rvc_rd_regmap rvc_rs1_regmap
-+#define rvc_rs2b_regmap rvc_rs1_regmap
-+static const char rvc_rs2_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 0 };
-+
-+typedef uint64_t insn_t;
-+
-+static inline unsigned int riscv_insn_length (insn_t insn)
-+{
-+ if ((insn & 0x3) != 3) /* RVC */
-+ return 2;
-+ if ((insn & 0x1f) != 0x1f) /* base ISA and extensions in 32-bit space */
-+ return 4;
-+ if ((insn & 0x3f) == 0x1f) /* 48-bit extensions */
-+ return 6;
-+ if ((insn & 0x7f) == 0x3f) /* 64-bit extensions */
-+ return 8;
-+ /* longer instructions not supported at the moment */
-+ return 2;
-+}
-+
-+static const char * const riscv_rm[8] = {
-+ "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn"
-+};
-+static const char* const riscv_pred_succ[16] = {
-+ 0, "w", "r", "rw", "o", "ow", "or", "orw",
-+ "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw",
-+};
-+
-+#define RVC_JUMP_BITS 10
-+#define RVC_JUMP_ALIGN_BITS 1
-+#define RVC_JUMP_ALIGN (1 << RVC_JUMP_ALIGN_BITS)
-+#define RVC_JUMP_REACH ((1ULL<<RVC_JUMP_BITS)*RVC_JUMP_ALIGN)
-+
-+#define RVC_BRANCH_BITS 5
-+#define RVC_BRANCH_ALIGN_BITS RVC_JUMP_ALIGN_BITS
-+#define RVC_BRANCH_ALIGN (1 << RVC_BRANCH_ALIGN_BITS)
-+#define RVC_BRANCH_REACH ((1ULL<<RVC_BRANCH_BITS)*RVC_BRANCH_ALIGN)
-+
-+#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1))
-+#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
-+
-+#define EXTRACT_ITYPE_IMM(x) \
-+ (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))
-+#define EXTRACT_STYPE_IMM(x) \
-+ (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12))
-+#define EXTRACT_SBTYPE_IMM(x) \
-+ ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12))
-+#define EXTRACT_UTYPE_IMM(x) \
-+ ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32))
-+#define EXTRACT_UJTYPE_IMM(x) \
-+ ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20))
-+
-+#define ENCODE_ITYPE_IMM(x) \
-+ (RV_X(x, 0, 12) << 20)
-+#define ENCODE_STYPE_IMM(x) \
-+ ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25))
-+#define ENCODE_SBTYPE_IMM(x) \
-+ ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31))
-+#define ENCODE_UTYPE_IMM(x) \
-+ (RV_X(x, 12, 20) << 12)
-+#define ENCODE_UJTYPE_IMM(x) \
-+ ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31))
-+
-+#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
-+#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
-+#define VALID_SBTYPE_IMM(x) (EXTRACT_SBTYPE_IMM(ENCODE_SBTYPE_IMM(x)) == (x))
-+#define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x))
-+#define VALID_UJTYPE_IMM(x) (EXTRACT_UJTYPE_IMM(ENCODE_UJTYPE_IMM(x)) == (x))
-+
-+#define RISCV_RTYPE(insn, rd, rs1, rs2) \
-+ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
-+#define RISCV_ITYPE(insn, rd, rs1, imm) \
-+ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm))
-+#define RISCV_STYPE(insn, rs1, rs2, imm) \
-+ ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm))
-+#define RISCV_SBTYPE(insn, rs1, rs2, target) \
-+ ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_SBTYPE_IMM(target))
-+#define RISCV_UTYPE(insn, rd, bigimm) \
-+ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm))
-+#define RISCV_UJTYPE(insn, rd, target) \
-+ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UJTYPE_IMM(target))
-+
-+#define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0)
-+
-+#define RISCV_CONST_HIGH_PART(VALUE) \
-+ (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
-+#define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE))
-+#define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC))
-+#define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC))
-+
-+/* RV fields */
-+
-+#define OP_MASK_OP 0x7f
-+#define OP_SH_OP 0
-+#define OP_MASK_RS2 0x1f
-+#define OP_SH_RS2 20
-+#define OP_MASK_RS1 0x1f
-+#define OP_SH_RS1 15
-+#define OP_MASK_RS3 0x1f
-+#define OP_SH_RS3 27
-+#define OP_MASK_RD 0x1f
-+#define OP_SH_RD 7
-+#define OP_MASK_SHAMT 0x3f
-+#define OP_SH_SHAMT 20
-+#define OP_MASK_SHAMTW 0x1f
-+#define OP_SH_SHAMTW 20
-+#define OP_MASK_RM 0x7
-+#define OP_SH_RM 12
-+#define OP_MASK_PRED 0xf
-+#define OP_SH_PRED 24
-+#define OP_MASK_SUCC 0xf
-+#define OP_SH_SUCC 20
-+#define OP_MASK_AQ 0x1
-+#define OP_SH_AQ 26
-+#define OP_MASK_RL 0x1
-+#define OP_SH_RL 25
-+
-+#define OP_MASK_VRD 0x1f
-+#define OP_SH_VRD 7
-+#define OP_MASK_VRS 0x1f
-+#define OP_SH_VRS 15
-+#define OP_MASK_VRT 0x1f
-+#define OP_SH_VRT 20
-+#define OP_MASK_VRR 0x1f
-+#define OP_SH_VRR 27
-+
-+#define OP_MASK_VFD 0x1f
-+#define OP_SH_VFD 7
-+#define OP_MASK_VFS 0x1f
-+#define OP_SH_VFS 15
-+#define OP_MASK_VFT 0x1f
-+#define OP_SH_VFT 20
-+#define OP_MASK_VFR 0x1f
-+#define OP_SH_VFR 27
-+
-+#define OP_MASK_IMMNGPR 0x3f
-+#define OP_SH_IMMNGPR 20
-+#define OP_MASK_IMMNFPR 0x3f
-+#define OP_SH_IMMNFPR 26
-+#define OP_MASK_IMMSEGNELM 0x7
-+#define OP_SH_IMMSEGNELM 29
-+#define OP_MASK_CUSTOM_IMM 0x7f
-+#define OP_SH_CUSTOM_IMM 25
-+#define OP_MASK_CSR 0xfff
-+#define OP_SH_CSR 20
-+
-+#define LINK_REG 1
-+#define TP_REG 15
-+#define GP_REG 31
-+
-+#define RISCV_JUMP_BITS RISCV_BIGIMM_BITS
-+#define RISCV_JUMP_ALIGN_BITS 1
-+#define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS)
-+#define RISCV_JUMP_REACH ((1ULL<<RISCV_JUMP_BITS)*RISCV_JUMP_ALIGN)
-+
-+#define RISCV_IMM_BITS 12
-+#define RISCV_BIGIMM_BITS (32-RISCV_IMM_BITS)
-+#define RISCV_IMM_REACH (1LL<<RISCV_IMM_BITS)
-+#define RISCV_BIGIMM_REACH (1LL<<RISCV_BIGIMM_BITS)
-+#define RISCV_BRANCH_BITS RISCV_IMM_BITS
-+#define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS
-+#define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS)
-+#define RISCV_BRANCH_REACH (RISCV_IMM_REACH*RISCV_BRANCH_ALIGN)
-+
-+/* This structure holds information for a particular instruction. */
-+
-+struct riscv_opcode
-+{
-+ /* The name of the instruction. */
-+ const char *name;
-+ /* The ISA subset name (I, M, A, F, D, Xextension). */
-+ const char *subset;
-+ /* A string describing the arguments for this instruction. */
-+ const char *args;
-+ /* The basic opcode for the instruction. When assembling, this
-+ opcode is modified by the arguments to produce the actual opcode
-+ that is used. If pinfo is INSN_MACRO, then this is 0. */
-+ insn_t match;
-+ /* If pinfo is not INSN_MACRO, then this is a bit mask for the
-+ relevant portions of the opcode when disassembling. If the
-+ actual opcode anded with the match field equals the opcode field,
-+ then we have found the correct instruction. If pinfo is
-+ INSN_MACRO, then this field is the macro identifier. */
-+ insn_t mask;
-+ /* A function to determine if a word corresponds to this instruction.
-+ Usually, this computes ((word & mask) == match). */
-+ int (*match_func)(const struct riscv_opcode *op, insn_t word);
-+ /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
-+ of bits describing the instruction, notably any relevant hazard
-+ information. */
-+ unsigned long pinfo;
-+};
-+
-+#define INSN_WRITE_GPR_D 0x00000001
-+#define INSN_WRITE_GPR_RA 0x00000004
-+#define INSN_WRITE_FPR_D 0x00000008
-+#define INSN_READ_GPR_S 0x00000040
-+#define INSN_READ_GPR_T 0x00000080
-+#define INSN_READ_FPR_S 0x00000100
-+#define INSN_READ_FPR_T 0x00000200
-+#define INSN_READ_FPR_R 0x00000400
-+/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
-+#define INSN_ALIAS 0x00001000
-+/* Instruction is actually a macro. It should be ignored by the
-+ disassembler, and requires special treatment by the assembler. */
-+#define INSN_MACRO 0xffffffff
-+
-+/* This is a list of macro expanded instructions.
-+
-+ _I appended means immediate
-+ _A appended means address
-+ _AB appended means address with base register
-+ _D appended means 64 bit floating point constant
-+ _S appended means 32 bit floating point constant. */
-+
-+enum
-+{
-+ M_LA,
-+ M_LLA,
-+ M_LA_TLS_GD,
-+ M_LA_TLS_IE,
-+ M_LB,
-+ M_LBU,
-+ M_LH,
-+ M_LHU,
-+ M_LW,
-+ M_LWU,
-+ M_LD,
-+ M_SB,
-+ M_SH,
-+ M_SW,
-+ M_SD,
-+ M_FLW,
-+ M_FLD,
-+ M_FSW,
-+ M_FSD,
-+ M_CALL,
-+ M_JUMP,
-+ M_J,
-+ M_LI,
-+ M_VF,
-+ M_NUM_MACROS
-+};
-+
-+
-+/* The order of overloaded instructions matters. Label arguments and
-+ register arguments look the same. Instructions that can have either
-+ for arguments must apear in the correct order in this table for the
-+ assembler to pick the right one. In other words, entries with
-+ immediate operands must apear after the same instruction with
-+ registers.
-+
-+ Many instructions are short hand for other instructions (i.e., The
-+ jal <register> instruction is short for jalr <register>). */
-+
-+extern const struct riscv_opcode riscv_builtin_opcodes[];
-+extern const int bfd_riscv_num_builtin_opcodes;
-+extern struct riscv_opcode *riscv_opcodes;
-+extern int bfd_riscv_num_opcodes;
-+#define NUMOPCODES bfd_riscv_num_opcodes
-+
-+#endif /* _RISCV_H_ */
-diff --git a/ld/Makefile.am b/ld/Makefile.am
-index b2b2a6e..521aa7c 100644
---- a/ld/Makefile.am
-+++ b/ld/Makefile.am
-@@ -251,6 +251,7 @@ ALL_EMULATION_SOURCES = \
- eelf32ppcsim.c \
- eelf32ppcvxworks.c \
- eelf32ppcwindiss.c \
-+ eelf32lriscv.c \
- eelf32rl78.c \
- eelf32rx.c \
- eelf32tilegx.c \
-@@ -510,6 +511,7 @@ ALL_64_EMULATION_SOURCES = \
- eelf64btsmip_fbsd.c \
- eelf64hppa.c \
- eelf64lppc.c \
-+ eelf64lriscv.c \
- eelf64ltsmip.c \
- eelf64ltsmip_fbsd.c \
- eelf64mmix.c \
-@@ -1123,6 +1125,10 @@ eelf32lppcsim.c: $(srcdir)/emulparams/elf32lppcsim.sh \
- ldemul-list.h \
- $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
- ${GENSCRIPTS} elf32lppcsim "$(tdir_elf32lppcsim)"
-+eelf32lriscv.c: $(srcdir)/emulparams/elf32lriscv.sh \
-+ $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \
-+ $(srcdir)/emultempl/riscvelf.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
-+ ${GENSCRIPTS} elf32lriscv "$(tdir_elf32lriscv)"
- eelf32lsmip.c: $(srcdir)/emulparams/elf32lsmip.sh \
- $(srcdir)/emulparams/elf32lmip.sh $(srcdir)/emulparams/elf32bmip.sh \
- $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \
-@@ -2088,6 +2094,11 @@ eelf64lppc.c: $(srcdir)/emulparams/elf64lppc.sh \
- ldemul-list.h \
- $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
- ${GENSCRIPTS} elf64lppc "$(tdir_elf64lppc)"
-+eelf64lriscv.c: $(srcdir)/emulparams/elf64lriscv.sh \
-+ $(srcdir)/emulparams/elf64lriscv-defs.sh \
-+ $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \
-+ $(srcdir)/emultempl/riscvelf.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
-+ ${GENSCRIPTS} elf64lriscv "$(tdir_elf64lriscv)"
- eelf64ltsmip.c: $(srcdir)/emulparams/elf64ltsmip.sh \
- $(srcdir)/emulparams/elf64btsmip.sh $(srcdir)/emulparams/elf64bmip-defs.sh \
- $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \
-diff --git a/ld/Makefile.in b/ld/Makefile.in
-index b95a3d1..c76fa85 100644
---- a/ld/Makefile.in
-+++ b/ld/Makefile.in
-@@ -542,6 +542,7 @@ ALL_EMULATION_SOURCES = \
- eelf32lppclinux.c \
- eelf32lppcnto.c \
- eelf32lppcsim.c \
-+ eelf32lriscv.c \
- eelf32m32c.c \
- eelf32mb_linux.c \
- eelf32mcore.c \
-@@ -817,6 +818,7 @@ ALL_64_EMULATION_SOURCES = \
- eelf64btsmip_fbsd.c \
- eelf64hppa.c \
- eelf64lppc.c \
-+ eelf64lriscv.c \
- eelf64ltsmip.c \
- eelf64ltsmip_fbsd.c \
- eelf64mmix.c \
-@@ -1194,6 +1196,7 @@ distclean-compile:
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lppclinux.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lppcnto.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lppcsim.Po@am__quote@
-+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lriscv.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lr5900.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lr5900n32.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lsmip.Po@am__quote@
-@@ -1246,6 +1249,7 @@ distclean-compile:
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64btsmip_fbsd.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64hppa.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lppc.Po@am__quote@
-+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ltsmip.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ltsmip_fbsd.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64mmix.Po@am__quote@
-@@ -2607,6 +2611,10 @@ eelf32lppcsim.c: $(srcdir)/emulparams/elf32lppcsim.sh \
- ldemul-list.h \
- $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
- ${GENSCRIPTS} elf32lppcsim "$(tdir_elf32lppcsim)"
-+eelf32lriscv.c: $(srcdir)/emulparams/elf32lriscv.sh \
-+ $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \
-+ $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
-+ ${GENSCRIPTS} elf32lriscv "$(tdir_elf32lriscv)"
- eelf32lsmip.c: $(srcdir)/emulparams/elf32lsmip.sh \
- $(srcdir)/emulparams/elf32lmip.sh $(srcdir)/emulparams/elf32bmip.sh \
- $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \
-@@ -3572,6 +3580,11 @@ eelf64lppc.c: $(srcdir)/emulparams/elf64lppc.sh \
- ldemul-list.h \
- $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
- ${GENSCRIPTS} elf64lppc "$(tdir_elf64lppc)"
-+eelf64lriscv.c: $(srcdir)/emulparams/elf64lriscv.sh \
-+ $(srcdir)/emulparams/elf64lriscv-defs.sh \
-+ $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \
-+ $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
-+ ${GENSCRIPTS} elf64lriscv "$(tdir_elf64lriscv)"
- eelf64ltsmip.c: $(srcdir)/emulparams/elf64ltsmip.sh \
- $(srcdir)/emulparams/elf64btsmip.sh $(srcdir)/emulparams/elf64bmip-defs.sh \
- $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \
-diff --git a/ld/configure.tgt b/ld/configure.tgt
-index c50730b..b882e29 100644
---- a/ld/configure.tgt
-+++ b/ld/configure.tgt
-@@ -592,6 +592,9 @@ powerpc-*-aix*) targ_emul=aixppc ;;
- powerpc-*-beos*) targ_emul=aixppc ;;
- powerpc-*-windiss*) targ_emul=elf32ppcwindiss ;;
- powerpc-*-lynxos*) targ_emul=ppclynx ;;
-+riscv*-*-*) targ_emul=elf64lriscv
-+ targ_extra_emuls="elf32lriscv"
-+ targ_extra_libpath=$targ_extra_emuls ;;
- rs6000-*-aix[5-9]*) targ_emul=aix5rs6 ;;
- rs6000-*-aix*) targ_emul=aixrs6
- ;;
-diff --git a/ld/emulparams/elf32lriscv-defs.sh b/ld/emulparams/elf32lriscv-defs.sh
-new file mode 100644
-index 0000000..c7e1719
---- /dev/null
-+++ b/ld/emulparams/elf32lriscv-defs.sh
+diff -Nur original-binutils/ld/emulparams/elf32lriscv-defs.sh binutils/ld/emulparams/elf32lriscv-defs.sh
+--- original-binutils/ld/emulparams/elf32lriscv-defs.sh 1969-12-31 16:00:00.000000000 -0800
++++ binutils/ld/emulparams/elf32lriscv-defs.sh 2014-12-09 14:31:16.735857672 -0800
@@ -0,0 +1,41 @@
+# This is an ELF platform.
+SCRIPT_NAME=elf
@@ -8856,11 +8079,9 @@ index 0000000..c7e1719
+fi
+
+TEXT_DYNAMIC=
-diff --git a/ld/emulparams/elf32lriscv.sh b/ld/emulparams/elf32lriscv.sh
-new file mode 100644
-index 0000000..11ef663
---- /dev/null
-+++ b/ld/emulparams/elf32lriscv.sh
+diff -Nur original-binutils/ld/emulparams/elf32lriscv.sh binutils/ld/emulparams/elf32lriscv.sh
+--- original-binutils/ld/emulparams/elf32lriscv.sh 1969-12-31 16:00:00.000000000 -0800
++++ binutils/ld/emulparams/elf32lriscv.sh 2014-12-09 14:31:16.735857672 -0800
@@ -0,0 +1,9 @@
+. ${srcdir}/emulparams/elf32lriscv-defs.sh
+OUTPUT_FORMAT="elf32-littleriscv"
@@ -8871,27 +8092,21 @@ index 0000000..11ef663
+ .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
+ .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
+'
-diff --git a/ld/emulparams/elf64lriscv-defs.sh b/ld/emulparams/elf64lriscv-defs.sh
-new file mode 100644
-index 0000000..abaf766
---- /dev/null
-+++ b/ld/emulparams/elf64lriscv-defs.sh
+diff -Nur original-binutils/ld/emulparams/elf64lriscv-defs.sh binutils/ld/emulparams/elf64lriscv-defs.sh
+--- original-binutils/ld/emulparams/elf64lriscv-defs.sh 1969-12-31 16:00:00.000000000 -0800
++++ binutils/ld/emulparams/elf64lriscv-defs.sh 2014-12-09 14:31:16.735857672 -0800
@@ -0,0 +1,2 @@
+. ${srcdir}/emulparams/elf32lriscv-defs.sh
+COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)"
-diff --git a/ld/emulparams/elf64lriscv.sh b/ld/emulparams/elf64lriscv.sh
-new file mode 100644
-index 0000000..3a6a652
---- /dev/null
-+++ b/ld/emulparams/elf64lriscv.sh
+diff -Nur original-binutils/ld/emulparams/elf64lriscv.sh binutils/ld/emulparams/elf64lriscv.sh
+--- original-binutils/ld/emulparams/elf64lriscv.sh 1969-12-31 16:00:00.000000000 -0800
++++ binutils/ld/emulparams/elf64lriscv.sh 2014-12-09 14:31:16.735857672 -0800
@@ -0,0 +1,2 @@
+. ${srcdir}/emulparams/elf64lriscv-defs.sh
+OUTPUT_FORMAT="elf64-littleriscv"
-diff --git a/ld/emultempl/riscvelf.em b/ld/emultempl/riscvelf.em
-new file mode 100644
-index 0000000..a19899d
---- /dev/null
-+++ b/ld/emultempl/riscvelf.em
+diff -Nur original-binutils/ld/emultempl/riscvelf.em binutils/ld/emultempl/riscvelf.em
+--- original-binutils/ld/emultempl/riscvelf.em 1969-12-31 16:00:00.000000000 -0800
++++ binutils/ld/emultempl/riscvelf.em 2014-12-09 14:32:35.932301937 -0800
@@ -0,0 +1,42 @@
+# This shell script emits a C file. -*- C -*-
+# Copyright 2004, 2006, 2007, 2008 Free Software Foundation, Inc.
@@ -8935,62 +8150,10 @@ index 0000000..a19899d
+EOF
+
+LDEMUL_BEFORE_ALLOCATION=riscv_before_allocation
-diff --git a/opcodes/configure b/opcodes/configure
-index 47bc29b..29105d2 100755
---- a/opcodes/configure
-+++ b/opcodes/configure
-@@ -12555,6 +12555,7 @@ if test x${all_targets} = xfalse ; then
- bfd_powerpc_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;;
- bfd_powerpc_64_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;;
- bfd_pyramid_arch) ;;
-+ bfd_riscv_arch) ta="$ta riscv-dis.lo riscv-opc.lo" ;;
- bfd_romp_arch) ;;
- bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;;
- bfd_rl78_arch) ta="$ta rl78-dis.lo rl78-decode.lo";;
-diff --git a/opcodes/configure.in b/opcodes/configure.in
-index 8309373..7b7872e 100644
---- a/opcodes/configure.in
-+++ b/opcodes/configure.in
-@@ -302,6 +302,7 @@ if test x${all_targets} = xfalse ; then
- bfd_powerpc_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;;
- bfd_powerpc_64_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;;
- bfd_pyramid_arch) ;;
-+ bfd_riscv_arch) ta="$ta riscv-dis.lo riscv-opc.lo" ;;
- bfd_romp_arch) ;;
- bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;;
- bfd_rl78_arch) ta="$ta rl78-dis.lo rl78-decode.lo";;
-diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
-index 55a44ec..6c336c7 100644
---- a/opcodes/disassemble.c
-+++ b/opcodes/disassemble.c
-@@ -378,6 +378,11 @@ disassembler (abfd)
- disassemble = print_insn_little_powerpc;
- break;
- #endif
-+#ifdef ARCH_riscv
-+ case bfd_arch_riscv:
-+ disassemble = print_insn_riscv;
-+ break;
-+#endif
- #ifdef ARCH_rs6000
- case bfd_arch_rs6000:
- if (bfd_get_mach (abfd) == bfd_mach_ppc_620)
-@@ -550,6 +555,9 @@ disassembler_usage (stream)
- #ifdef ARCH_powerpc
- print_ppc_disassembler_options (stream);
- #endif
-+#ifdef ARCH_riscv
-+ print_riscv_disassembler_options (stream);
-+#endif
- #ifdef ARCH_i386
- print_i386_disassembler_options (stream);
- #endif
-diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
-new file mode 100644
-index 0000000..e8f463d
---- /dev/null
-+++ b/opcodes/riscv-dis.c
-@@ -0,0 +1,537 @@
+diff -Nur original-binutils/opcodes/riscv-dis.c binutils/opcodes/riscv-dis.c
+--- original-binutils/opcodes/riscv-dis.c 1969-12-31 16:00:00.000000000 -0800
++++ binutils/opcodes/riscv-dis.c 2014-12-09 14:38:38.665778707 -0800
+@@ -0,0 +1,488 @@
+/* RISC-V disassembler
+ Copyright 2011-2014 Free Software Foundation, Inc.
+
@@ -9025,55 +8188,6 @@ index 0000000..e8f463d
+#include <stdint.h>
+#include <assert.h>
+
-+/* FIXME: These should be shared with gdb somehow. */
-+
-+static const char * const riscv_gpr_names_numeric[32] =
-+{
-+ "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
-+ "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
-+ "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
-+ "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31"
-+};
-+
-+static const char * const riscv_gpr_names_abi[32] = {
-+ "zero", "ra", "s0", "s1", "s2", "s3", "s4", "s5",
-+ "s6", "s7", "s8", "s9", "s10", "s11", "sp", "tp",
-+ "v0", "v1", "a0", "a1", "a2", "a3", "a4", "a5",
-+ "a6", "a7", "t0", "t1", "t2", "t3", "t4", "gp"
-+};
-+
-+
-+static const char * const riscv_fpr_names_numeric[32] =
-+{
-+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
-+ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
-+ "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
-+ "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
-+};
-+
-+static const char * const riscv_fpr_names_abi[32] = {
-+ "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
-+ "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
-+ "fv0", "fv1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
-+ "fa6", "fa7", "ft0", "ft1", "ft2", "ft3", "ft4", "ft5"
-+};
-+
-+static const char * const riscv_vgr_reg_names_riscv[32] =
-+{
-+ "vx0", "vx1", "vx2", "vx3", "vx4", "vx5", "vx6", "vx7",
-+ "vx8", "vx9", "vx10", "vx11", "vx12", "vx13", "vx14", "vx15",
-+ "vx16", "vx17", "vx18", "vx19", "vx20", "vx21", "vx22", "vx23",
-+ "vx24", "vx25", "vx26", "vx27", "vx28", "vx29", "vx30", "vx31"
-+};
-+
-+static const char * const riscv_vfp_reg_names_riscv[32] =
-+{
-+ "vf0", "vf1", "vf2", "vf3", "vf4", "vf5", "vf6", "vf7",
-+ "vf8", "vf9", "vf10", "vf11", "vf12", "vf13", "vf14", "vf15",
-+ "vf16", "vf17", "vf18", "vf19", "vf20", "vf21", "vf22", "vf23",
-+ "vf24", "vf25", "vf26", "vf27", "vf28", "vf29", "vf30", "vf31"
-+};
-+
+struct riscv_private_data
+{
+ bfd_vma gp;
@@ -9145,9 +8259,9 @@ index 0000000..e8f463d
+ pd->print_addr = pd->hi_addr[base_reg] + offset;
+ pd->hi_addr[base_reg] = -1;
+ }
-+ else if (base_reg == GP_REG && pd->gp != (bfd_vma)-1)
++ else if (base_reg == X_GP && pd->gp != (bfd_vma)-1)
+ pd->print_addr = pd->gp + offset;
-+ else if (base_reg == TP_REG)
++ else if (base_reg == X_TP)
+ pd->print_addr = offset;
+}
+
@@ -9214,42 +8328,42 @@ index 0000000..e8f463d
+ case 'd':
+ (*info->fprintf_func)
+ ( info->stream, "%s",
-+ riscv_vgr_reg_names_riscv[(l >> OP_SH_VRD) & OP_MASK_VRD]);
++ riscv_vec_gpr_names[(l >> OP_SH_VRD) & OP_MASK_VRD]);
+ break;
+ case 's':
+ (*info->fprintf_func)
+ ( info->stream, "%s",
-+ riscv_vgr_reg_names_riscv[(l >> OP_SH_VRS) & OP_MASK_VRS]);
++ riscv_vec_gpr_names[(l >> OP_SH_VRS) & OP_MASK_VRS]);
+ break;
+ case 't':
+ (*info->fprintf_func)
+ ( info->stream, "%s",
-+ riscv_vgr_reg_names_riscv[(l >> OP_SH_VRT) & OP_MASK_VRT]);
++ riscv_vec_gpr_names[(l >> OP_SH_VRT) & OP_MASK_VRT]);
+ break;
+ case 'r':
+ (*info->fprintf_func)
+ ( info->stream, "%s",
-+ riscv_vgr_reg_names_riscv[(l >> OP_SH_VRR) & OP_MASK_VRR]);
++ riscv_vec_gpr_names[(l >> OP_SH_VRR) & OP_MASK_VRR]);
+ break;
+ case 'D':
+ (*info->fprintf_func)
+ ( info->stream, "%s",
-+ riscv_vfp_reg_names_riscv[(l >> OP_SH_VFD) & OP_MASK_VFD]);
++ riscv_vec_fpr_names[(l >> OP_SH_VFD) & OP_MASK_VFD]);
+ break;
+ case 'S':
+ (*info->fprintf_func)
+ ( info->stream, "%s",
-+ riscv_vfp_reg_names_riscv[(l >> OP_SH_VFS) & OP_MASK_VFS]);
++ riscv_vec_fpr_names[(l >> OP_SH_VFS) & OP_MASK_VFS]);
+ break;
+ case 'T':
+ (*info->fprintf_func)
+ ( info->stream, "%s",
-+ riscv_vfp_reg_names_riscv[(l >> OP_SH_VFT) & OP_MASK_VFT]);
++ riscv_vec_fpr_names[(l >> OP_SH_VFT) & OP_MASK_VFT]);
+ break;
+ case 'R':
+ (*info->fprintf_func)
+ ( info->stream, "%s",
-+ riscv_vfp_reg_names_riscv[(l >> OP_SH_VFR) & OP_MASK_VFR]);
++ riscv_vec_fpr_names[(l >> OP_SH_VFR) & OP_MASK_VFR]);
+ break;
+ }
+ break;
@@ -9528,12 +8642,10 @@ index 0000000..e8f463d
+
+ fprintf (stream, _("\n"));
+}
-diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
-new file mode 100644
-index 0000000..c4aece8
---- /dev/null
-+++ b/opcodes/riscv-opc.c
-@@ -0,0 +1,683 @@
+diff -Nur original-binutils/opcodes/riscv-opc.c binutils/opcodes/riscv-opc.c
+--- original-binutils/opcodes/riscv-opc.c 1969-12-31 16:00:00.000000000 -0800
++++ binutils/opcodes/riscv-opc.c 2014-12-09 14:38:38.665778707 -0800
+@@ -0,0 +1,729 @@
+/* RISC-V opcode list
+ Copyright 2011-2014 Free Software Foundation, Inc.
+
@@ -9561,7 +8673,53 @@ index 0000000..c4aece8
+#include "opcode/riscv.h"
+#include <stdio.h>
+
-+/* Short hand so the lines aren't too long. */
++/* Register names used by gas and objdump. */
++
++const char * const riscv_gpr_names_numeric[32] =
++{
++ "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
++ "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
++ "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
++ "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31"
++};
++
++const char * const riscv_gpr_names_abi[32] = {
++ "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2",
++ "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5",
++ "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7",
++ "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"
++};
++
++const char * const riscv_fpr_names_numeric[32] =
++{
++ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
++ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
++ "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
++ "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
++};
++
++const char * const riscv_fpr_names_abi[32] = {
++ "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",
++ "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
++ "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
++ "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
++};
++
++const char * const riscv_vec_gpr_names[32] =
++{
++ "vx0", "vx1", "vx2", "vx3", "vx4", "vx5", "vx6", "vx7",
++ "vx8", "vx9", "vx10", "vx11", "vx12", "vx13", "vx14", "vx15",
++ "vx16", "vx17", "vx18", "vx19", "vx20", "vx21", "vx22", "vx23",
++ "vx24", "vx25", "vx26", "vx27", "vx28", "vx29", "vx30", "vx31"
++};
++
++const char * const riscv_vec_fpr_names[32] =
++{
++ "vf0", "vf1", "vf2", "vf3", "vf4", "vf5", "vf6", "vf7",
++ "vf8", "vf9", "vf10", "vf11", "vf12", "vf13", "vf14", "vf15",
++ "vf16", "vf17", "vf18", "vf19", "vf20", "vf21", "vf22", "vf23",
++ "vf24", "vf25", "vf26", "vf27", "vf28", "vf29", "vf30", "vf31"
++};
+
+/* The order of overloaded instructions matters. Label arguments and
+ register arguments look the same. Instructions that can have either
@@ -9661,16 +8819,16 @@ index 0000000..c4aece8
+{"sra", "I", "d,s,t", MATCH_SRA, MASK_SRA, match_opcode, WR_xd|RD_xs1|RD_xs2 },
+{"sra", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 },
+{"sub", "I", "d,s,t", MATCH_SUB, MASK_SUB, match_opcode, WR_xd|RD_xs1|RD_xs2 },
-+{"ret", "I", "", MATCH_JALR | (LINK_REG << OP_SH_RS1), MASK_JALR | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 },
++{"ret", "I", "", MATCH_JALR | (X_RA << OP_SH_RS1), MASK_JALR | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 },
+{"j", "I", "a", MATCH_JAL, MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS },
-+{"jal", "I", "a", MATCH_JAL | (LINK_REG << OP_SH_RD), MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS|WR_xd },
++{"jal", "I", "a", MATCH_JAL | (X_RA << OP_SH_RD), MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS|WR_xd },
+{"jal", "I", "d,a", MATCH_JAL, MASK_JAL, match_opcode, WR_xd },
+{"call", "I", "c", 0, (int) M_CALL, match_never, INSN_MACRO },
+{"jump", "I", "c", 0, (int) M_JUMP, match_never, INSN_MACRO },
+{"jr", "I", "s", MATCH_JALR, MASK_JALR | MASK_RD | MASK_IMM, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 },
+{"jr", "I", "s,j", MATCH_JALR, MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 },
-+{"jalr", "I", "s", MATCH_JALR | (LINK_REG << OP_SH_RD), MASK_JALR | MASK_RD | MASK_IMM, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 },
-+{"jalr", "I", "s,j", MATCH_JALR | (LINK_REG << OP_SH_RD), MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 },
++{"jalr", "I", "s", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD | MASK_IMM, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 },
++{"jalr", "I", "s,j", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 },
+{"jalr", "I", "d,s", MATCH_JALR, MASK_JALR | MASK_IMM, match_opcode, INSN_ALIAS|WR_xd|RD_xs1 },
+{"jalr", "I", "d,s,j", MATCH_JALR, MASK_JALR, match_opcode, WR_xd|RD_xs1 },
+{"lb", "I", "d,o(s)", MATCH_LB, MASK_LB, match_opcode, WR_xd|RD_xs1 },
diff --git a/sys-devel/gcc/Manifest b/sys-devel/gcc/Manifest
index c1fed6f..063d2d8 100644
--- a/sys-devel/gcc/Manifest
+++ b/sys-devel/gcc/Manifest
@@ -4,7 +4,7 @@ AUX c89 412 SHA256 29ad5dd697135c2892067e780447894dc1cd071708157e46d21773ab99c50
AUX c99 446 SHA256 057b348cf5be9b4fb9db99a4549f6433c89d21e5f91dc5e46b0b4dc6b70432f5 SHA512 bf3b0eb1125d5e89b433954fcbf805cd86dec5a6eeb23df685ebf3ff83a610573f2ffcec65d893244c845936a73918387cba026710c65c854b2c94a78b007989 WHIRLPOOL b888038b96615c7a0363555b407a3de2c1f17e34428fa16dfbf56fcf68875d6bcdecbc61b545d7f71842ff1909a3ffeff17165fa7f56b48f95adae22f5f8bff1
AUX fix_libtool_files.sh 1636 SHA256 d2b5d275f08030a94b4186475020fc5a8b6d56ec76d2902ceb12399d5a04d8e8 SHA512 69b3834e43716b62bb878950f19a0efaa1957780e9ba05017ed03e3e7c0c1bc88bf4081c3a777cf06f2dd135d62642c7d9292754797b9c2886d43b82bf25a45e WHIRLPOOL b2ca64313433f3566ee9b2893d5913e9791dbefdd6500d513ddb32a40107892e23d6ad833067841e25000de4e52caff6a14f3b8e2de64cacfe7a147d29d817c8
AUX gcc-4.6.1-riscv.patch 380760 SHA256 2faaf88dd86164b93d9fd0be6922d8793e4202ca74d960210b854159a73c474f SHA512 f458a716d14308ab53426af50bdd50a0f5fb639712ae095f63942a36a9fe30292cbe86fa345213065113f478489fa610705a45dd4ba96355c440160c14a60e26 WHIRLPOOL dd77ae5c0da7bd8f2117893e19d9f6565e62f089bc7d2d64c2feb4140fd3cef1cb12e655190689ec601cfea588f4bdc7a613927d67ce5315c44772370247ab7f
-AUX gcc-4.9.0-riscv.patch 358603 SHA256 2c8149c44f2c768c0ac82f2465d4c273ca4e2f926a1d2261a6e9461c976ce43d SHA512 52a9f2abbb9d6268b624f23a35a972bdfe42a99df52c4a559cb885212705e092815fbfbe348dd1a309727f4d782cf9bdab40b9447ecfc4985e83ab6eb027f699 WHIRLPOOL 765d64a72d2d92a9e0d726db7ad8f28a06de61c016a54dd7a58a308f53517ae1ac2bb9200aee8788f2ee3ee2716f637000675ba66f5d4b28d10326c87b022d03
+AUX gcc-4.9.0-riscv.patch 361082 SHA256 1829026a4ef3caaa204dc71be89a54b3803537ad4396ff407ece44c57788e5b6 SHA512 173427a1e7f36675cc87265f2c72bab9195111e73f7183c9c0e4fdacc3affb9c628a2a340db5da919c03471ddfcd3746afe8c142f8bd7df380059b8399499bc2 WHIRLPOOL 7ef1f2dd91c728cee562f8de607fe5aa964d583a3956f105740b59deeaf3f380ddf923c81793f00a589464b965f86c55a4daccacba87bece75068a05d3634d77
AUX gcc-configure-LANG.patch 2052 SHA256 63de6d2dcfe14f21d147abeb1390405b9220c03f8e968f482d4b4c1cf279c88b SHA512 a694c7ac2f45cc657097ff5b0cf1356ac88a9c06035c9ba15167e9d444844d0d8a478eb1b9b62195dd063774f79697b9148b9cdb6c261640b472c291061b2129 WHIRLPOOL 3cc1ec912fb192ff1058de5b93e49a994ba30d1501a932290dd5b3df1cd783875621cda56edeb41894cd5fa10c04917e693a40a60be8d742ddd7992bf5d8afeb
AUX gcc-configure-texinfo.patch 337 SHA256 74b73a7ecec2d88889876b4db480cd173632f49d5396bb8e5b3c93673f9b5b98 SHA512 a15fba8bf2ff02bdeca54d6f186bfa08c1079c6a8ba0a3beef154483ce5c1b8c497e7ffeec32371968f0037e0ff8384609eb0c367d0155a4e5a7eef8aad084d5 WHIRLPOOL 39d008aad06f7621e4e5db15f5e85a59e583b43f8d247029bd4944466bb60a9795bda157d185c45c329294078e282703a243aad5c468d90c77665dd6336870d4
AUX gcc-spec-env-r1.patch 3148 SHA256 da0a6442eb42bce58cbdc7858b110a2e65fc5bd5b4b780b9b491033de6e302fa SHA512 ecae71577543772cfe1711f1b4a8815c0b5d706ebd01edacd1f07586637d4805e25771f970a6e6d1bb696d4b1b5ef3e0036088a96a9f6beff7ddaee704175d16 WHIRLPOOL 3535605998eabccdee71ba396ed5cefbb8b0a8cb073101f6444c7d01233f3b3904c1b29f4daf0a3417c68de8dbd62a0b7dc367cacfcbfa0c4ee1b69b7df8c6fb
diff --git a/sys-devel/gcc/files/gcc-4.9.0-riscv.patch b/sys-devel/gcc/files/gcc-4.9.0-riscv.patch
index 1957c28..3941677 100644
--- a/sys-devel/gcc/files/gcc-4.9.0-riscv.patch
+++ b/sys-devel/gcc/files/gcc-4.9.0-riscv.patch
@@ -1,8 +1,7 @@
-diff --git a/config.sub b/config.sub
-index 61cb4bc..d6e23cb 100755
---- a/config.sub
-+++ b/config.sub
-@@ -334,6 +334,9 @@ case $basic_machine in
+diff -Nur original-gcc/config.sub gcc/config.sub
+--- original-gcc/config.sub 2013-10-01 09:50:56.000000000 -0700
++++ gcc/config.sub 2014-12-09 14:38:51.655180307 -0800
+@@ -334,6 +334,9 @@
ms1)
basic_machine=mt-unknown
;;
@@ -12,11 +11,9 @@ index 61cb4bc..d6e23cb 100755
strongarm | thumb | xscale)
basic_machine=arm-unknown
-diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
-new file mode 100644
-index 0000000..e3cc55a
---- /dev/null
-+++ b/gcc/common/config/riscv/riscv-common.c
+diff -Nur original-gcc/gcc/common/config/riscv/riscv-common.c gcc/gcc/common/config/riscv/riscv-common.c
+--- original-gcc/gcc/common/config/riscv/riscv-common.c 1969-12-31 16:00:00.000000000 -0800
++++ gcc/gcc/common/config/riscv/riscv-common.c 2014-12-09 14:31:16.745857225 -0800
@@ -0,0 +1,59 @@
+/* Common hooks for RISC-V.
+ Copyright (C) 1989-2014 Free Software Foundation, Inc.
@@ -77,78 +74,9 @@ index 0000000..e3cc55a
+#define TARGET_HANDLE_OPTION riscv_handle_option
+
+struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
-diff --git a/gcc/config.gcc b/gcc/config.gcc
-index 63e1222..830533e 100644
---- a/gcc/config.gcc
-+++ b/gcc/config.gcc
-@@ -447,6 +447,9 @@ powerpc*-*-*)
- esac
- extra_options="${extra_options} g.opt fused-madd.opt rs6000/rs6000-tables.opt"
- ;;
-+riscv*)
-+ cpu_type=riscv
-+ ;;
- rs6000*-*-*)
- need_64bit_hwint=yes
- extra_options="${extra_options} g.opt fused-madd.opt rs6000/rs6000-tables.opt"
-@@ -1944,6 +1947,20 @@ microblaze*-*-elf)
- cxx_target_objs="${cxx_target_objs} microblaze-c.o"
- tmake_file="${tmake_file} microblaze/t-microblaze"
- ;;
-+riscv*-*-linux*) # Linux RISC-V
-+ tm_file="elfos.h gnu-user.h linux.h glibc-stdint.h ${tm_file} riscv/linux.h riscv/linux64.h"
-+ tmake_file="${tmake_file} riscv/t-linux64"
-+ gnu_ld=yes
-+ gas=yes
-+ gcc_cv_initfini_array=yes
-+ ;;
-+riscv*-*-elf*) # Linux RISC-V
-+ tm_file="elfos.h newlib-stdint.h ${tm_file} riscv/elf.h"
-+ tmake_file="${tmake_file} riscv/t-elf"
-+ gnu_ld=yes
-+ gas=yes
-+ gcc_cv_initfini_array=yes
-+ ;;
- mips*-*-netbsd*) # NetBSD/mips, either endian.
- target_cpu_default="MASK_ABICALLS"
- tm_file="elfos.h ${tm_file} mips/elf.h netbsd.h netbsd-elf.h mips/netbsd.h"
-@@ -3750,6 +3767,31 @@ case "${target}" in
- done
- ;;
-
-+ riscv*-*-*)
-+ supported_defaults="abi arch arch_32 arch_64 float tune tune_32 tune_64"
-+
-+ case ${with_float} in
-+ "" | soft | hard)
-+ # OK
-+ ;;
-+ *)
-+ echo "Unknown floating point type used in --with-float=$with_float" 1>&2
-+ exit 1
-+ ;;
-+ esac
-+
-+ case ${with_abi} in
-+ "" | 32 | 64)
-+ # OK
-+ ;;
-+ *)
-+ echo "Unknown ABI used in --with-abi=$with_abi" 1>&2
-+ exit 1
-+ ;;
-+ esac
-+
-+ ;;
-+
- mips*-*-*)
- supported_defaults="abi arch arch_32 arch_64 float fpu nan tune tune_32 tune_64 divide llsc mips-plt synci"
-
-diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
-new file mode 100644
-index 0000000..b61051f
---- /dev/null
-+++ b/gcc/config/riscv/constraints.md
+diff -Nur original-gcc/gcc/config/riscv/constraints.md gcc/gcc/config/riscv/constraints.md
+--- original-gcc/gcc/config/riscv/constraints.md 1969-12-31 16:00:00.000000000 -0800
++++ gcc/gcc/config/riscv/constraints.md 2014-12-09 14:31:16.745857225 -0800
@@ -0,0 +1,95 @@
+;; Constraint definitions for RISC-V target.
+;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
@@ -245,11 +173,9 @@ index 0000000..b61051f
+ A vector zero."
+ (and (match_code "const_vector")
+ (match_test "op == CONST0_RTX (mode)")))
-diff --git a/gcc/config/riscv/elf.h b/gcc/config/riscv/elf.h
-new file mode 100644
-index 0000000..204288e
---- /dev/null
-+++ b/gcc/config/riscv/elf.h
+diff -Nur original-gcc/gcc/config/riscv/elf.h gcc/gcc/config/riscv/elf.h
+--- original-gcc/gcc/config/riscv/elf.h 1969-12-31 16:00:00.000000000 -0800
++++ gcc/gcc/config/riscv/elf.h 2014-12-09 14:31:16.745857225 -0800
@@ -0,0 +1,31 @@
+/* Target macros for mips*-elf targets.
+ Copyright (C) 1994, 1997, 1999, 2000, 2002, 2003, 2004, 2007, 2010
@@ -282,11 +208,9 @@ index 0000000..204288e
+#define ENDFILE_SPEC "crtend%O%s"
+
+#define NO_IMPLICIT_EXTERN_C 1
-diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv/generic.md
-new file mode 100644
-index 0000000..a6dc8fa7a
---- /dev/null
-+++ b/gcc/config/riscv/generic.md
+diff -Nur original-gcc/gcc/config/riscv/generic.md gcc/gcc/config/riscv/generic.md
+--- original-gcc/gcc/config/riscv/generic.md 1969-12-31 16:00:00.000000000 -0800
++++ gcc/gcc/config/riscv/generic.md 2014-12-09 14:31:16.745857225 -0800
@@ -0,0 +1,98 @@
+;; Generic DFA-based pipeline description for RISC-V targets.
+;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
@@ -386,11 +310,57 @@ index 0000000..a6dc8fa7a
+ (and (eq_attr "type" "fsqrt")
+ (eq_attr "mode" "DF"))
+ "alu")
-diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h
-new file mode 100644
-index 0000000..55f27ef
---- /dev/null
-+++ b/gcc/config/riscv/linux.h
+diff -Nur original-gcc/gcc/config/riscv/linux64.h gcc/gcc/config/riscv/linux64.h
+--- original-gcc/gcc/config/riscv/linux64.h 1969-12-31 16:00:00.000000000 -0800
++++ gcc/gcc/config/riscv/linux64.h 2014-12-09 14:31:16.745857225 -0800
+@@ -0,0 +1,44 @@
++/* Definitions for MIPS running Linux-based GNU systems with ELF format
++ using n32/64 abi.
++ Copyright 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010, 2011
++ Free Software Foundation, Inc.
++
++This file is part of GCC.
++
++GCC is free software; you can redistribute it and/or modify
++it under the terms of the GNU General Public License as published by
++the Free Software Foundation; either version 3, or (at your option)
++any later version.
++
++GCC is distributed in the hope that it will be useful,
++but WITHOUT ANY WARRANTY; without even the implied warranty of
++MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++GNU General Public License for more details.
++
++You should have received a copy of the GNU General Public License
++along with GCC; see the file COPYING3. If not see
++<http://www.gnu.org/licenses/>. */
++
++/* Force the default ABI flags onto the command line
++ in order to make the other specs easier to write. */
++#undef LIB_SPEC
++#define LIB_SPEC "\
++%{pthread:-lpthread} \
++%{shared:-lc} \
++%{!shared: \
++ %{profile:-lc_p} %{!profile:-lc}}"
++
++#define GLIBC_DYNAMIC_LINKER32 "/lib32/ld.so.1"
++#define GLIBC_DYNAMIC_LINKER64 "/lib/ld.so.1"
++
++#undef LINK_SPEC
++#define LINK_SPEC "\
++%{shared} \
++ %{!shared: \
++ %{!static: \
++ %{rdynamic:-export-dynamic} \
++ %{" OPT_ARCH64 ": -dynamic-linker " GNU_USER_DYNAMIC_LINKER64 "} \
++ %{" OPT_ARCH32 ": -dynamic-linker " GNU_USER_DYNAMIC_LINKER32 "}} \
++ %{static:-static}} \
++%{" OPT_ARCH64 ":-melf64lriscv} \
++%{" OPT_ARCH32 ":-melf32lriscv}"
+diff -Nur original-gcc/gcc/config/riscv/linux.h gcc/gcc/config/riscv/linux.h
+--- original-gcc/gcc/config/riscv/linux.h 1969-12-31 16:00:00.000000000 -0800
++++ gcc/gcc/config/riscv/linux.h 2014-12-09 14:31:16.745857225 -0800
@@ -0,0 +1,60 @@
+/* Definitions for MIPS running Linux-based GNU systems with ELF format.
+ Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
@@ -452,61 +422,9 @@ index 0000000..55f27ef
+#undef ENDFILE_SPEC
+#define ENDFILE_SPEC \
+ "%{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s"
-diff --git a/gcc/config/riscv/linux64.h b/gcc/config/riscv/linux64.h
-new file mode 100644
-index 0000000..36c124a
---- /dev/null
-+++ b/gcc/config/riscv/linux64.h
-@@ -0,0 +1,44 @@
-+/* Definitions for MIPS running Linux-based GNU systems with ELF format
-+ using n32/64 abi.
-+ Copyright 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010, 2011
-+ Free Software Foundation, Inc.
-+
-+This file is part of GCC.
-+
-+GCC is free software; you can redistribute it and/or modify
-+it under the terms of the GNU General Public License as published by
-+the Free Software Foundation; either version 3, or (at your option)
-+any later version.
-+
-+GCC is distributed in the hope that it will be useful,
-+but WITHOUT ANY WARRANTY; without even the implied warranty of
-+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+GNU General Public License for more details.
-+
-+You should have received a copy of the GNU General Public License
-+along with GCC; see the file COPYING3. If not see
-+<http://www.gnu.org/licenses/>. */
-+
-+/* Force the default ABI flags onto the command line
-+ in order to make the other specs easier to write. */
-+#undef LIB_SPEC
-+#define LIB_SPEC "\
-+%{pthread:-lpthread} \
-+%{shared:-lc} \
-+%{!shared: \
-+ %{profile:-lc_p} %{!profile:-lc}}"
-+
-+#define GLIBC_DYNAMIC_LINKER32 "/lib32/ld.so.1"
-+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld.so.1"
-+
-+#undef LINK_SPEC
-+#define LINK_SPEC "\
-+%{shared} \
-+ %{!shared: \
-+ %{!static: \
-+ %{rdynamic:-export-dynamic} \
-+ %{" OPT_ARCH64 ": -dynamic-linker " GNU_USER_DYNAMIC_LINKER64 "} \
-+ %{" OPT_ARCH32 ": -dynamic-linker " GNU_USER_DYNAMIC_LINKER32 "}} \
-+ %{static:-static}} \
-+%{" OPT_ARCH64 ":-melf64lriscv} \
-+%{" OPT_ARCH32 ":-melf32lriscv}"
-diff --git a/gcc/config/riscv/opcode-riscv.h b/gcc/config/riscv/opcode-riscv.h
-new file mode 100644
-index 0000000..a5435ac
---- /dev/null
-+++ b/gcc/config/riscv/opcode-riscv.h
+diff -Nur original-gcc/gcc/config/riscv/opcode-riscv.h gcc/gcc/config/riscv/opcode-riscv.h
+--- original-gcc/gcc/config/riscv/opcode-riscv.h 1969-12-31 16:00:00.000000000 -0800
++++ gcc/gcc/config/riscv/opcode-riscv.h 2014-12-09 14:31:16.745857225 -0800
@@ -0,0 +1,149 @@
+/* RISC-V ISA encoding.
+ Copyright (C) 2011-2014 Free Software Foundation, Inc.
@@ -657,11 +575,9 @@ index 0000000..a5435ac
+#include "riscv-opc.h"
+
+#endif /* _RISCV_H_ */
-diff --git a/gcc/config/riscv/peephole.md b/gcc/config/riscv/peephole.md
-new file mode 100644
-index 0000000..15e0861
---- /dev/null
-+++ b/gcc/config/riscv/peephole.md
+diff -Nur original-gcc/gcc/config/riscv/peephole.md gcc/gcc/config/riscv/peephole.md
+--- original-gcc/gcc/config/riscv/peephole.md 1969-12-31 16:00:00.000000000 -0800
++++ gcc/gcc/config/riscv/peephole.md 2014-12-09 14:32:35.932301937 -0800
@@ -0,0 +1,122 @@
+;;........................
+;; DI -> SI optimizations
@@ -785,11 +701,9 @@ index 0000000..15e0861
+ "!TARGET_64BIT && (flag_pic && SYMBOL_REF_LOCAL_P (operands[0]))"
+ "<store>\t%1,%0,%2"
+ [(set (attr "length") (const_int 8))])
-diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
-new file mode 100644
-index 0000000..f7a92c0
---- /dev/null
-+++ b/gcc/config/riscv/predicates.md
+diff -Nur original-gcc/gcc/config/riscv/predicates.md gcc/gcc/config/riscv/predicates.md
+--- original-gcc/gcc/config/riscv/predicates.md 1969-12-31 16:00:00.000000000 -0800
++++ gcc/gcc/config/riscv/predicates.md 2014-12-09 14:31:16.745857225 -0800
@@ -0,0 +1,182 @@
+;; Predicate description for RISC-V target.
+;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
@@ -973,1408 +887,10 @@ index 0000000..f7a92c0
+
+(define_predicate "fp_unorder_operator"
+ (match_code "ordered,unordered"))
-diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def
-new file mode 100644
-index 0000000..96a38f1
---- /dev/null
-+++ b/gcc/config/riscv/riscv-ftypes.def
-@@ -0,0 +1,39 @@
-+/* Definitions of prototypes for RISC-V built-in functions.
-+ Copyright (C) 2011-2014 Free Software Foundation, Inc.
-+ Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
-+ Based on MIPS target for GNU compiler.
-+
-+This file is part of GCC.
-+
-+GCC is free software; you can redistribute it and/or modify
-+it under the terms of the GNU General Public License as published by
-+the Free Software Foundation; either version 3, or (at your option)
-+any later version.
-+
-+GCC is distributed in the hope that it will be useful,
-+but WITHOUT ANY WARRANTY; without even the implied warranty of
-+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+GNU General Public License for more details.
-+
-+You should have received a copy of the GNU General Public License
-+along with GCC; see the file COPYING3. If not see
-+<http://www.gnu.org/licenses/>. */
-+
-+/* Invoke DEF_RISCV_FTYPE (NARGS, LIST) for each prototype used by
-+ MIPS built-in functions, where:
-+
-+ NARGS is the number of arguments.
-+ LIST contains the return-type code followed by the codes for each
-+ argument type.
-+
-+ Argument- and return-type codes are either modes or one of the following:
-+
-+ VOID for void_type_node
-+ INT for integer_type_node
-+ POINTER for ptr_type_node
-+
-+ (we don't use PTR because that's a ANSI-compatibillity macro).
-+
-+ Please keep this list lexicographically sorted by the LIST argument. */
-+
-+DEF_RISCV_FTYPE (1, (VOID, VOID))
-diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-modes.def
-new file mode 100644
-index 0000000..bb42344
---- /dev/null
-+++ b/gcc/config/riscv/riscv-modes.def
-@@ -0,0 +1,26 @@
-+/* Extra machine modes for RISC-V target.
-+ Copyright (C) 2011-2014 Free Software Foundation, Inc.
-+ Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
-+ Based on MIPS target for GNU compiler.
-+
-+This file is part of GCC.
-+
-+GCC is free software; you can redistribute it and/or modify
-+it under the terms of the GNU General Public License as published by
-+the Free Software Foundation; either version 3, or (at your option)
-+any later version.
-+
-+GCC is distributed in the hope that it will be useful,
-+but WITHOUT ANY WARRANTY; without even the implied warranty of
-+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+GNU General Public License for more details.
-+
-+You should have received a copy of the GNU General Public License
-+along with GCC; see the file COPYING3. If not see
-+<http://www.gnu.org/licenses/>. */
-+
-+FLOAT_MODE (TF, 16, ieee_quad_format);
-+
-+/* Vector modes. */
-+VECTOR_MODES (INT, 4); /* V8QI V4HI V2SI */
-+VECTOR_MODES (FLOAT, 4); /* V4HF V2SF */
-diff --git a/gcc/config/riscv/riscv-opc.h b/gcc/config/riscv/riscv-opc.h
-new file mode 100644
-index 0000000..eb29d3e
---- /dev/null
-+++ b/gcc/config/riscv/riscv-opc.h
-@@ -0,0 +1,1216 @@
-+/* Automatically generated by parse-opcodes */
-+#ifndef RISCV_ENCODING_H
-+#define RISCV_ENCODING_H
-+#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
-+#define MASK_CUSTOM3_RD_RS1_RS2 0x707f
-+#define MATCH_VLSEGSTWU 0xc00305b
-+#define MASK_VLSEGSTWU 0x1e00707f
-+#define MATCH_C_LW0 0x12
-+#define MASK_C_LW0 0x801f
-+#define MATCH_FMV_D_X 0xf2000053
-+#define MASK_FMV_D_X 0xfff0707f
-+#define MATCH_VLH 0x200205b
-+#define MASK_VLH 0xfff0707f
-+#define MATCH_C_LI 0x0
-+#define MASK_C_LI 0x1f
-+#define MATCH_FADD_D 0x2000053
-+#define MASK_FADD_D 0xfe00007f
-+#define MATCH_C_LD 0x9
-+#define MASK_C_LD 0x1f
-+#define MATCH_VLD 0x600205b
-+#define MASK_VLD 0xfff0707f
-+#define MATCH_FADD_S 0x53
-+#define MASK_FADD_S 0xfe00007f
-+#define MATCH_C_LW 0xa
-+#define MASK_C_LW 0x1f
-+#define MATCH_VLW 0x400205b
-+#define MASK_VLW 0xfff0707f
-+#define MATCH_VSSEGSTW 0x400307b
-+#define MASK_VSSEGSTW 0x1e00707f
-+#define MATCH_UTIDX 0x6077
-+#define MASK_UTIDX 0xfffff07f
-+#define MATCH_C_FLW 0x14
-+#define MASK_C_FLW 0x1f
-+#define MATCH_FSUB_D 0xa000053
-+#define MASK_FSUB_D 0xfe00007f
-+#define MATCH_VSSEGSTD 0x600307b
-+#define MASK_VSSEGSTD 0x1e00707f
-+#define MATCH_VSSEGSTB 0x307b
-+#define MASK_VSSEGSTB 0x1e00707f
-+#define MATCH_DIV 0x2004033
-+#define MASK_DIV 0xfe00707f
-+#define MATCH_FMV_H_X 0xf4000053
-+#define MASK_FMV_H_X 0xfff0707f
-+#define MATCH_C_FLD 0x15
-+#define MASK_C_FLD 0x1f
-+#define MATCH_FRRM 0x202073
-+#define MASK_FRRM 0xfffff07f
-+#define MATCH_VFMSV_S 0x1000202b
-+#define MASK_VFMSV_S 0xfff0707f
-+#define MATCH_C_LWSP 0x5
-+#define MASK_C_LWSP 0x1f
-+#define MATCH_FENCE 0xf
-+#define MASK_FENCE 0x707f
-+#define MATCH_FNMSUB_S 0x4b
-+#define MASK_FNMSUB_S 0x600007f
-+#define MATCH_FLE_S 0xa0000053
-+#define MASK_FLE_S 0xfe00707f
-+#define MATCH_FNMSUB_H 0x400004b
-+#define MASK_FNMSUB_H 0x600007f
-+#define MATCH_FLE_H 0xbc000053
-+#define MASK_FLE_H 0xfe00707f
-+#define MATCH_FLW 0x2007
-+#define MASK_FLW 0x707f
-+#define MATCH_VSETVL 0x600b
-+#define MASK_VSETVL 0xfff0707f
-+#define MATCH_VFMSV_D 0x1200202b
-+#define MASK_VFMSV_D 0xfff0707f
-+#define MATCH_FLE_D 0xa2000053
-+#define MASK_FLE_D 0xfe00707f
-+#define MATCH_FENCE_I 0x100f
-+#define MASK_FENCE_I 0x707f
-+#define MATCH_FNMSUB_D 0x200004b
-+#define MASK_FNMSUB_D 0x600007f
-+#define MATCH_ADDW 0x3b
-+#define MASK_ADDW 0xfe00707f
-+#define MATCH_XOR 0x4033
-+#define MASK_XOR 0xfe00707f
-+#define MATCH_SUB 0x40000033
-+#define MASK_SUB 0xfe00707f
-+#define MATCH_VSSTW 0x400307b
-+#define MASK_VSSTW 0xfe00707f
-+#define MATCH_VSSTH 0x200307b
-+#define MASK_VSSTH 0xfe00707f
-+#define MATCH_SC_W 0x1800202f
-+#define MASK_SC_W 0xf800707f
-+#define MATCH_VSSTB 0x307b
-+#define MASK_VSSTB 0xfe00707f
-+#define MATCH_VSSTD 0x600307b
-+#define MASK_VSSTD 0xfe00707f
-+#define MATCH_ADDI 0x13
-+#define MASK_ADDI 0x707f
-+#define MATCH_RDTIMEH 0xc8102073
-+#define MASK_RDTIMEH 0xfffff07f
-+#define MATCH_MULH 0x2001033
-+#define MASK_MULH 0xfe00707f
-+#define MATCH_CSRRSI 0x6073
-+#define MASK_CSRRSI 0x707f
-+#define MATCH_FCVT_D_WU 0xd2100053
-+#define MASK_FCVT_D_WU 0xfff0007f
-+#define MATCH_MULW 0x200003b
-+#define MASK_MULW 0xfe00707f
-+#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
-+#define MASK_CUSTOM1_RD_RS1_RS2 0x707f
-+#define MATCH_VENQIMM1 0xc00302b
-+#define MASK_VENQIMM1 0xfe007fff
-+#define MATCH_VENQIMM2 0xe00302b
-+#define MASK_VENQIMM2 0xfe007fff
-+#define MATCH_RDINSTRET 0xc0202073
-+#define MASK_RDINSTRET 0xfffff07f
-+#define MATCH_C_SWSP 0x8
-+#define MASK_C_SWSP 0x1f
-+#define MATCH_VLSTW 0x400305b
-+#define MASK_VLSTW 0xfe00707f
-+#define MATCH_VLSTH 0x200305b
-+#define MASK_VLSTH 0xfe00707f
-+#define MATCH_VLSTB 0x305b
-+#define MASK_VLSTB 0xfe00707f
-+#define MATCH_VLSTD 0x600305b
-+#define MASK_VLSTD 0xfe00707f
-+#define MATCH_ANDI 0x7013
-+#define MASK_ANDI 0x707f
-+#define MATCH_FMV_X_S 0xe0000053
-+#define MASK_FMV_X_S 0xfff0707f
-+#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
-+#define MASK_CUSTOM0_RD_RS1_RS2 0x707f
-+#define MATCH_FNMADD_S 0x4f
-+#define MASK_FNMADD_S 0x600007f
-+#define MATCH_LWU 0x6003
-+#define MASK_LWU 0x707f
-+#define MATCH_CUSTOM0_RS1 0x200b
-+#define MASK_CUSTOM0_RS1 0x707f
-+#define MATCH_VLSEGSTBU 0x800305b
-+#define MASK_VLSEGSTBU 0x1e00707f
-+#define MATCH_FNMADD_D 0x200004f
-+#define MASK_FNMADD_D 0x600007f
-+#define MATCH_FCVT_W_S 0xc0000053
-+#define MASK_FCVT_W_S 0xfff0007f
-+#define MATCH_C_SRAI 0x1019
-+#define MASK_C_SRAI 0x1c1f
-+#define MATCH_MULHSU 0x2002033
-+#define MASK_MULHSU 0xfe00707f
-+#define MATCH_FCVT_D_LU 0xd2300053
-+#define MASK_FCVT_D_LU 0xfff0007f
-+#define MATCH_FCVT_W_D 0xc2000053
-+#define MASK_FCVT_W_D 0xfff0007f
-+#define MATCH_FSUB_H 0xc000053
-+#define MASK_FSUB_H 0xfe00007f
-+#define MATCH_DIVUW 0x200503b
-+#define MASK_DIVUW 0xfe00707f
-+#define MATCH_SLTI 0x2013
-+#define MASK_SLTI 0x707f
-+#define MATCH_VLSTBU 0x800305b
-+#define MASK_VLSTBU 0xfe00707f
-+#define MATCH_SLTU 0x3033
-+#define MASK_SLTU 0xfe00707f
-+#define MATCH_FLH 0x1007
-+#define MASK_FLH 0x707f
-+#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
-+#define MASK_CUSTOM2_RD_RS1_RS2 0x707f
-+#define MATCH_FLD 0x3007
-+#define MASK_FLD 0x707f
-+#define MATCH_FSUB_S 0x8000053
-+#define MASK_FSUB_S 0xfe00007f
-+#define MATCH_FCVT_H_LU 0x6c000053
-+#define MASK_FCVT_H_LU 0xfff0007f
-+#define MATCH_CUSTOM0 0xb
-+#define MASK_CUSTOM0 0x707f
-+#define MATCH_CUSTOM1 0x2b
-+#define MASK_CUSTOM1 0x707f
-+#define MATCH_CUSTOM2 0x5b
-+#define MASK_CUSTOM2 0x707f
-+#define MATCH_CUSTOM3 0x7b
-+#define MASK_CUSTOM3 0x707f
-+#define MATCH_VXCPTSAVE 0x302b
-+#define MASK_VXCPTSAVE 0xfff07fff
-+#define MATCH_VMSV 0x200202b
-+#define MASK_VMSV 0xfff0707f
-+#define MATCH_FCVT_LU_S 0xc0300053
-+#define MASK_FCVT_LU_S 0xfff0007f
-+#define MATCH_AUIPC 0x17
-+#define MASK_AUIPC 0x7f
-+#define MATCH_FRFLAGS 0x102073
-+#define MASK_FRFLAGS 0xfffff07f
-+#define MATCH_FCVT_LU_D 0xc2300053
-+#define MASK_FCVT_LU_D 0xfff0007f
-+#define MATCH_CSRRWI 0x5073
-+#define MASK_CSRRWI 0x707f
-+#define MATCH_FADD_H 0x4000053
-+#define MASK_FADD_H 0xfe00007f
-+#define MATCH_FSQRT_S 0x58000053
-+#define MASK_FSQRT_S 0xfff0007f
-+#define MATCH_VXCPTKILL 0x400302b
-+#define MASK_VXCPTKILL 0xffffffff
-+#define MATCH_STOP 0x5077
-+#define MASK_STOP 0xffffffff
-+#define MATCH_FSGNJN_S 0x20001053
-+#define MASK_FSGNJN_S 0xfe00707f
-+#define MATCH_FSGNJN_H 0x34000053
-+#define MASK_FSGNJN_H 0xfe00707f
-+#define MATCH_FSQRT_D 0x5a000053
-+#define MASK_FSQRT_D 0xfff0007f
-+#define MATCH_XORI 0x4013
-+#define MASK_XORI 0x707f
-+#define MATCH_DIVU 0x2005033
-+#define MASK_DIVU 0xfe00707f
-+#define MATCH_FSGNJN_D 0x22001053
-+#define MASK_FSGNJN_D 0xfe00707f
-+#define MATCH_FSQRT_H 0x24000053
-+#define MASK_FSQRT_H 0xfff0007f
-+#define MATCH_VSSEGSTH 0x200307b
-+#define MASK_VSSEGSTH 0x1e00707f
-+#define MATCH_SW 0x2023
-+#define MASK_SW 0x707f
-+#define MATCH_VLSTWU 0xc00305b
-+#define MASK_VLSTWU 0xfe00707f
-+#define MATCH_VFSSEGW 0x1400207b
-+#define MASK_VFSSEGW 0x1ff0707f
-+#define MATCH_LHU 0x5003
-+#define MASK_LHU 0x707f
-+#define MATCH_SH 0x1023
-+#define MASK_SH 0x707f
-+#define MATCH_FMSUB_H 0x4000047
-+#define MASK_FMSUB_H 0x600007f
-+#define MATCH_VXCPTAUX 0x200402b
-+#define MASK_VXCPTAUX 0xfffff07f
-+#define MATCH_FMSUB_D 0x2000047
-+#define MASK_FMSUB_D 0x600007f
-+#define MATCH_VFSSEGD 0x1600207b
-+#define MASK_VFSSEGD 0x1ff0707f
-+#define MATCH_VLSEGHU 0xa00205b
-+#define MASK_VLSEGHU 0x1ff0707f
-+#define MATCH_MOVN 0x2007077
-+#define MASK_MOVN 0xfe00707f
-+#define MATCH_CUSTOM1_RS1 0x202b
-+#define MASK_CUSTOM1_RS1 0x707f
-+#define MATCH_VLSTHU 0xa00305b
-+#define MASK_VLSTHU 0xfe00707f
-+#define MATCH_MOVZ 0x7077
-+#define MASK_MOVZ 0xfe00707f
-+#define MATCH_CSRRW 0x1073
-+#define MASK_CSRRW 0x707f
-+#define MATCH_LD 0x3003
-+#define MASK_LD 0x707f
-+#define MATCH_LB 0x3
-+#define MASK_LB 0x707f
-+#define MATCH_VLWU 0xc00205b
-+#define MASK_VLWU 0xfff0707f
-+#define MATCH_LH 0x1003
-+#define MASK_LH 0x707f
-+#define MATCH_LW 0x2003
-+#define MASK_LW 0x707f
-+#define MATCH_CSRRC 0x3073
-+#define MASK_CSRRC 0x707f
-+#define MATCH_FCVT_LU_H 0x4c000053
-+#define MASK_FCVT_LU_H 0xfff0007f
-+#define MATCH_FCVT_S_D 0x40100053
-+#define MASK_FCVT_S_D 0xfff0007f
-+#define MATCH_BGEU 0x7063
-+#define MASK_BGEU 0x707f
-+#define MATCH_VFLSTD 0x1600305b
-+#define MASK_VFLSTD 0xfe00707f
-+#define MATCH_FCVT_S_L 0xd0200053
-+#define MASK_FCVT_S_L 0xfff0007f
-+#define MATCH_FCVT_S_H 0x84000053
-+#define MASK_FCVT_S_H 0xfff0007f
-+#define MATCH_FSCSR 0x301073
-+#define MASK_FSCSR 0xfff0707f
-+#define MATCH_FCVT_S_W 0xd0000053
-+#define MASK_FCVT_S_W 0xfff0007f
-+#define MATCH_VFLSTW 0x1400305b
-+#define MASK_VFLSTW 0xfe00707f
-+#define MATCH_VXCPTEVAC 0x600302b
-+#define MASK_VXCPTEVAC 0xfff07fff
-+#define MATCH_AMOMINU_D 0xc000302f
-+#define MASK_AMOMINU_D 0xf800707f
-+#define MATCH_FSFLAGS 0x101073
-+#define MASK_FSFLAGS 0xfff0707f
-+#define MATCH_SRLI 0x5013
-+#define MASK_SRLI 0xfc00707f
-+#define MATCH_C_SRLI 0x819
-+#define MASK_C_SRLI 0x1c1f
-+#define MATCH_AMOMINU_W 0xc000202f
-+#define MASK_AMOMINU_W 0xf800707f
-+#define MATCH_SRLW 0x503b
-+#define MASK_SRLW 0xfe00707f
-+#define MATCH_VFLSEGW 0x1400205b
-+#define MASK_VFLSEGW 0x1ff0707f
-+#define MATCH_C_LD0 0x8012
-+#define MASK_C_LD0 0x801f
-+#define MATCH_VLSEGBU 0x800205b
-+#define MASK_VLSEGBU 0x1ff0707f
-+#define MATCH_JALR 0x67
-+#define MASK_JALR 0x707f
-+#define MATCH_BLT 0x4063
-+#define MASK_BLT 0x707f
-+#define MATCH_CUSTOM2_RD_RS1 0x605b
-+#define MASK_CUSTOM2_RD_RS1 0x707f
-+#define MATCH_FCLASS_S 0xe0001053
-+#define MASK_FCLASS_S 0xfff0707f
-+#define MATCH_REM 0x2006033
-+#define MASK_REM 0xfe00707f
-+#define MATCH_FCLASS_D 0xe2001053
-+#define MASK_FCLASS_D 0xfff0707f
-+#define MATCH_FMUL_S 0x10000053
-+#define MASK_FMUL_S 0xfe00007f
-+#define MATCH_RDCYCLEH 0xc8002073
-+#define MASK_RDCYCLEH 0xfffff07f
-+#define MATCH_VLSEGSTHU 0xa00305b
-+#define MASK_VLSEGSTHU 0x1e00707f
-+#define MATCH_FMUL_D 0x12000053
-+#define MASK_FMUL_D 0xfe00007f
-+#define MATCH_ORI 0x6013
-+#define MASK_ORI 0x707f
-+#define MATCH_FMUL_H 0x14000053
-+#define MASK_FMUL_H 0xfe00007f
-+#define MATCH_VFLSEGD 0x1600205b
-+#define MASK_VFLSEGD 0x1ff0707f
-+#define MATCH_FEQ_S 0xa0002053
-+#define MASK_FEQ_S 0xfe00707f
-+#define MATCH_FSGNJX_D 0x22002053
-+#define MASK_FSGNJX_D 0xfe00707f
-+#define MATCH_SRAIW 0x4000501b
-+#define MASK_SRAIW 0xfe00707f
-+#define MATCH_FSGNJX_H 0x3c000053
-+#define MASK_FSGNJX_H 0xfe00707f
-+#define MATCH_FSGNJX_S 0x20002053
-+#define MASK_FSGNJX_S 0xfe00707f
-+#define MATCH_FEQ_D 0xa2002053
-+#define MASK_FEQ_D 0xfe00707f
-+#define MATCH_CUSTOM1_RD_RS1 0x602b
-+#define MASK_CUSTOM1_RD_RS1 0x707f
-+#define MATCH_FEQ_H 0xac000053
-+#define MASK_FEQ_H 0xfe00707f
-+#define MATCH_AMOMAXU_D 0xe000302f
-+#define MASK_AMOMAXU_D 0xf800707f
-+#define MATCH_DIVW 0x200403b
-+#define MASK_DIVW 0xfe00707f
-+#define MATCH_AMOMAXU_W 0xe000202f
-+#define MASK_AMOMAXU_W 0xf800707f
-+#define MATCH_SRAI_RV32 0x40005013
-+#define MASK_SRAI_RV32 0xfe00707f
-+#define MATCH_C_SRLI32 0xc19
-+#define MASK_C_SRLI32 0x1c1f
-+#define MATCH_VFSSTW 0x1400307b
-+#define MASK_VFSSTW 0xfe00707f
-+#define MATCH_CUSTOM0_RD 0x400b
-+#define MASK_CUSTOM0_RD 0x707f
-+#define MATCH_C_BEQ 0x10
-+#define MASK_C_BEQ 0x1f
-+#define MATCH_VFSSTD 0x1600307b
-+#define MASK_VFSSTD 0xfe00707f
-+#define MATCH_CUSTOM3_RD_RS1 0x607b
-+#define MASK_CUSTOM3_RD_RS1 0x707f
-+#define MATCH_LR_D 0x1000302f
-+#define MASK_LR_D 0xf9f0707f
-+#define MATCH_LR_W 0x1000202f
-+#define MASK_LR_W 0xf9f0707f
-+#define MATCH_FCVT_H_WU 0x7c000053
-+#define MASK_FCVT_H_WU 0xfff0007f
-+#define MATCH_VMVV 0x200002b
-+#define MASK_VMVV 0xfff0707f
-+#define MATCH_SLLW 0x103b
-+#define MASK_SLLW 0xfe00707f
-+#define MATCH_SLLI 0x1013
-+#define MASK_SLLI 0xfc00707f
-+#define MATCH_BEQ 0x63
-+#define MASK_BEQ 0x707f
-+#define MATCH_AND 0x7033
-+#define MASK_AND 0xfe00707f
-+#define MATCH_LBU 0x4003
-+#define MASK_LBU 0x707f
-+#define MATCH_FSGNJ_S 0x20000053
-+#define MASK_FSGNJ_S 0xfe00707f
-+#define MATCH_FMSUB_S 0x47
-+#define MASK_FMSUB_S 0x600007f
-+#define MATCH_C_SUB3 0x11c
-+#define MASK_C_SUB3 0x31f
-+#define MATCH_FSGNJ_H 0x2c000053
-+#define MASK_FSGNJ_H 0xfe00707f
-+#define MATCH_VLB 0x205b
-+#define MASK_VLB 0xfff0707f
-+#define MATCH_C_ADDIW 0x1d
-+#define MASK_C_ADDIW 0x1f
-+#define MATCH_CUSTOM3_RS1_RS2 0x307b
-+#define MASK_CUSTOM3_RS1_RS2 0x707f
-+#define MATCH_FSGNJ_D 0x22000053
-+#define MASK_FSGNJ_D 0xfe00707f
-+#define MATCH_VLSEGWU 0xc00205b
-+#define MASK_VLSEGWU 0x1ff0707f
-+#define MATCH_FCVT_S_WU 0xd0100053
-+#define MASK_FCVT_S_WU 0xfff0007f
-+#define MATCH_CUSTOM3_RS1 0x207b
-+#define MASK_CUSTOM3_RS1 0x707f
-+#define MATCH_SC_D 0x1800302f
-+#define MASK_SC_D 0xf800707f
-+#define MATCH_VFSW 0x1400207b
-+#define MASK_VFSW 0xfff0707f
-+#define MATCH_AMOSWAP_D 0x800302f
-+#define MASK_AMOSWAP_D 0xf800707f
-+#define MATCH_SB 0x23
-+#define MASK_SB 0x707f
-+#define MATCH_AMOSWAP_W 0x800202f
-+#define MASK_AMOSWAP_W 0xf800707f
-+#define MATCH_VFSD 0x1600207b
-+#define MASK_VFSD 0xfff0707f
-+#define MATCH_CUSTOM2_RS1 0x205b
-+#define MASK_CUSTOM2_RS1 0x707f
-+#define MATCH_SD 0x3023
-+#define MASK_SD 0x707f
-+#define MATCH_FMV_S_X 0xf0000053
-+#define MASK_FMV_S_X 0xfff0707f
-+#define MATCH_REMUW 0x200703b
-+#define MASK_REMUW 0xfe00707f
-+#define MATCH_JAL 0x6f
-+#define MASK_JAL 0x7f
-+#define MATCH_C_FSD 0x18
-+#define MASK_C_FSD 0x1f
-+#define MATCH_RDCYCLE 0xc0002073
-+#define MASK_RDCYCLE 0xfffff07f
-+#define MATCH_C_BNE 0x11
-+#define MASK_C_BNE 0x1f
-+#define MATCH_C_ADD 0x1a
-+#define MASK_C_ADD 0x801f
-+#define MATCH_VXCPTCAUSE 0x402b
-+#define MASK_VXCPTCAUSE 0xfffff07f
-+#define MATCH_VGETCFG 0x400b
-+#define MASK_VGETCFG 0xfffff07f
-+#define MATCH_LUI 0x37
-+#define MASK_LUI 0x7f
-+#define MATCH_VSETCFG 0x200b
-+#define MASK_VSETCFG 0x7fff
-+#define MATCH_C_SDSP 0x6
-+#define MASK_C_SDSP 0x1f
-+#define MATCH_C_LDSP 0x4
-+#define MASK_C_LDSP 0x1f
-+#define MATCH_FNMADD_H 0x400004f
-+#define MASK_FNMADD_H 0x600007f
-+#define MATCH_CUSTOM0_RS1_RS2 0x300b
-+#define MASK_CUSTOM0_RS1_RS2 0x707f
-+#define MATCH_SLLI_RV32 0x1013
-+#define MASK_SLLI_RV32 0xfe00707f
-+#define MATCH_MUL 0x2000033
-+#define MASK_MUL 0xfe00707f
-+#define MATCH_CSRRCI 0x7073
-+#define MASK_CSRRCI 0x707f
-+#define MATCH_C_SRAI32 0x1419
-+#define MASK_C_SRAI32 0x1c1f
-+#define MATCH_FLT_H 0xb4000053
-+#define MASK_FLT_H 0xfe00707f
-+#define MATCH_SRAI 0x40005013
-+#define MASK_SRAI 0xfc00707f
-+#define MATCH_AMOAND_D 0x6000302f
-+#define MASK_AMOAND_D 0xf800707f
-+#define MATCH_FLT_D 0xa2001053
-+#define MASK_FLT_D 0xfe00707f
-+#define MATCH_SRAW 0x4000503b
-+#define MASK_SRAW 0xfe00707f
-+#define MATCH_CSRRS 0x2073
-+#define MASK_CSRRS 0x707f
-+#define MATCH_FLT_S 0xa0001053
-+#define MASK_FLT_S 0xfe00707f
-+#define MATCH_ADDIW 0x1b
-+#define MASK_ADDIW 0x707f
-+#define MATCH_AMOAND_W 0x6000202f
-+#define MASK_AMOAND_W 0xf800707f
-+#define MATCH_CUSTOM2_RD 0x405b
-+#define MASK_CUSTOM2_RD 0x707f
-+#define MATCH_FCVT_WU_D 0xc2100053
-+#define MASK_FCVT_WU_D 0xfff0007f
-+#define MATCH_AMOXOR_W 0x2000202f
-+#define MASK_AMOXOR_W 0xf800707f
-+#define MATCH_FCVT_D_L 0xd2200053
-+#define MASK_FCVT_D_L 0xfff0007f
-+#define MATCH_FCVT_WU_H 0x5c000053
-+#define MASK_FCVT_WU_H 0xfff0007f
-+#define MATCH_C_SLLI 0x19
-+#define MASK_C_SLLI 0x1c1f
-+#define MATCH_AMOXOR_D 0x2000302f
-+#define MASK_AMOXOR_D 0xf800707f
-+#define MATCH_FCVT_WU_S 0xc0100053
-+#define MASK_FCVT_WU_S 0xfff0007f
-+#define MATCH_CUSTOM3_RD 0x407b
-+#define MASK_CUSTOM3_RD 0x707f
-+#define MATCH_FMAX_H 0xcc000053
-+#define MASK_FMAX_H 0xfe00707f
-+#define MATCH_VENQCNT 0x1000302b
-+#define MASK_VENQCNT 0xfe007fff
-+#define MATCH_VLBU 0x800205b
-+#define MASK_VLBU 0xfff0707f
-+#define MATCH_VLHU 0xa00205b
-+#define MASK_VLHU 0xfff0707f
-+#define MATCH_C_SW 0xd
-+#define MASK_C_SW 0x1f
-+#define MATCH_C_SD 0xc
-+#define MASK_C_SD 0x1f
-+#define MATCH_C_OR3 0x21c
-+#define MASK_C_OR3 0x31f
-+#define MATCH_C_AND3 0x31c
-+#define MASK_C_AND3 0x31f
-+#define MATCH_VFSSEGSTW 0x1400307b
-+#define MASK_VFSSEGSTW 0x1e00707f
-+#define MATCH_SLT 0x2033
-+#define MASK_SLT 0xfe00707f
-+#define MATCH_AMOOR_D 0x4000302f
-+#define MASK_AMOOR_D 0xf800707f
-+#define MATCH_REMU 0x2007033
-+#define MASK_REMU 0xfe00707f
-+#define MATCH_REMW 0x200603b
-+#define MASK_REMW 0xfe00707f
-+#define MATCH_SLL 0x1033
-+#define MASK_SLL 0xfe00707f
-+#define MATCH_VFSSEGSTD 0x1600307b
-+#define MASK_VFSSEGSTD 0x1e00707f
-+#define MATCH_AMOOR_W 0x4000202f
-+#define MASK_AMOOR_W 0xf800707f
-+#define MATCH_CUSTOM2_RS1_RS2 0x305b
-+#define MASK_CUSTOM2_RS1_RS2 0x707f
-+#define MATCH_VF 0x10202b
-+#define MASK_VF 0x1f0707f
-+#define MATCH_VFMVV 0x1000002b
-+#define MASK_VFMVV 0xfff0707f
-+#define MATCH_VFLSEGSTW 0x1400305b
-+#define MASK_VFLSEGSTW 0x1e00707f
-+#define MATCH_VXCPTRESTORE 0x200302b
-+#define MASK_VXCPTRESTORE 0xfff07fff
-+#define MATCH_VXCPTHOLD 0x800302b
-+#define MASK_VXCPTHOLD 0xffffffff
-+#define MATCH_SLTIU 0x3013
-+#define MASK_SLTIU 0x707f
-+#define MATCH_VFLSEGSTD 0x1600305b
-+#define MASK_VFLSEGSTD 0x1e00707f
-+#define MATCH_VFLD 0x1600205b
-+#define MASK_VFLD 0xfff0707f
-+#define MATCH_FMADD_S 0x43
-+#define MASK_FMADD_S 0x600007f
-+#define MATCH_VFLW 0x1400205b
-+#define MASK_VFLW 0xfff0707f
-+#define MATCH_FMADD_D 0x2000043
-+#define MASK_FMADD_D 0x600007f
-+#define MATCH_FMADD_H 0x4000043
-+#define MASK_FMADD_H 0x600007f
-+#define MATCH_SRET 0x80000073
-+#define MASK_SRET 0xffffffff
-+#define MATCH_VSSEGW 0x400207b
-+#define MASK_VSSEGW 0x1ff0707f
-+#define MATCH_CUSTOM0_RD_RS1 0x600b
-+#define MASK_CUSTOM0_RD_RS1 0x707f
-+#define MATCH_VSSEGH 0x200207b
-+#define MASK_VSSEGH 0x1ff0707f
-+#define MATCH_FRCSR 0x302073
-+#define MASK_FRCSR 0xfffff07f
-+#define MATCH_VSSEGD 0x600207b
-+#define MASK_VSSEGD 0x1ff0707f
-+#define MATCH_VSSEGB 0x207b
-+#define MASK_VSSEGB 0x1ff0707f
-+#define MATCH_FMIN_H 0xc4000053
-+#define MASK_FMIN_H 0xfe00707f
-+#define MATCH_FMIN_D 0x2a000053
-+#define MASK_FMIN_D 0xfe00707f
-+#define MATCH_BLTU 0x6063
-+#define MASK_BLTU 0x707f
-+#define MATCH_FMIN_S 0x28000053
-+#define MASK_FMIN_S 0xfe00707f
-+#define MATCH_SRLI_RV32 0x5013
-+#define MASK_SRLI_RV32 0xfe00707f
-+#define MATCH_SLLIW 0x101b
-+#define MASK_SLLIW 0xfe00707f
-+#define MATCH_FMAX_S 0x28001053
-+#define MASK_FMAX_S 0xfe00707f
-+#define MATCH_FCVT_D_H 0x8c000053
-+#define MASK_FCVT_D_H 0xfff0007f
-+#define MATCH_FCVT_D_W 0xd2000053
-+#define MASK_FCVT_D_W 0xfff0007f
-+#define MATCH_ADD 0x33
-+#define MASK_ADD 0xfe00707f
-+#define MATCH_FCVT_D_S 0x42000053
-+#define MASK_FCVT_D_S 0xfff0007f
-+#define MATCH_FMAX_D 0x2a001053
-+#define MASK_FMAX_D 0xfe00707f
-+#define MATCH_BNE 0x1063
-+#define MASK_BNE 0x707f
-+#define MATCH_CUSTOM1_RD 0x402b
-+#define MASK_CUSTOM1_RD 0x707f
-+#define MATCH_FSRM 0x201073
-+#define MASK_FSRM 0xfff0707f
-+#define MATCH_FDIV_D 0x1a000053
-+#define MASK_FDIV_D 0xfe00007f
-+#define MATCH_VSW 0x400207b
-+#define MASK_VSW 0xfff0707f
-+#define MATCH_FCVT_L_S 0xc0200053
-+#define MASK_FCVT_L_S 0xfff0007f
-+#define MATCH_FDIV_H 0x1c000053
-+#define MASK_FDIV_H 0xfe00007f
-+#define MATCH_VSB 0x207b
-+#define MASK_VSB 0xfff0707f
-+#define MATCH_FDIV_S 0x18000053
-+#define MASK_FDIV_S 0xfe00007f
-+#define MATCH_FSRMI 0x205073
-+#define MASK_FSRMI 0xfff0707f
-+#define MATCH_FCVT_L_H 0x44000053
-+#define MASK_FCVT_L_H 0xfff0007f
-+#define MATCH_VSH 0x200207b
-+#define MASK_VSH 0xfff0707f
-+#define MATCH_FCVT_L_D 0xc2200053
-+#define MASK_FCVT_L_D 0xfff0007f
-+#define MATCH_FCVT_H_S 0x90000053
-+#define MASK_FCVT_H_S 0xfff0007f
-+#define MATCH_SCALL 0x73
-+#define MASK_SCALL 0xffffffff
-+#define MATCH_FSFLAGSI 0x105073
-+#define MASK_FSFLAGSI 0xfff0707f
-+#define MATCH_FCVT_H_W 0x74000053
-+#define MASK_FCVT_H_W 0xfff0007f
-+#define MATCH_FCVT_H_L 0x64000053
-+#define MASK_FCVT_H_L 0xfff0007f
-+#define MATCH_SRLIW 0x501b
-+#define MASK_SRLIW 0xfe00707f
-+#define MATCH_FCVT_S_LU 0xd0300053
-+#define MASK_FCVT_S_LU 0xfff0007f
-+#define MATCH_FCVT_H_D 0x92000053
-+#define MASK_FCVT_H_D 0xfff0007f
-+#define MATCH_SBREAK 0x100073
-+#define MASK_SBREAK 0xffffffff
-+#define MATCH_RDINSTRETH 0xc8202073
-+#define MASK_RDINSTRETH 0xfffff07f
-+#define MATCH_SRA 0x40005033
-+#define MASK_SRA 0xfe00707f
-+#define MATCH_BGE 0x5063
-+#define MASK_BGE 0x707f
-+#define MATCH_SRL 0x5033
-+#define MASK_SRL 0xfe00707f
-+#define MATCH_VENQCMD 0xa00302b
-+#define MASK_VENQCMD 0xfe007fff
-+#define MATCH_OR 0x6033
-+#define MASK_OR 0xfe00707f
-+#define MATCH_SUBW 0x4000003b
-+#define MASK_SUBW 0xfe00707f
-+#define MATCH_FMV_X_D 0xe2000053
-+#define MASK_FMV_X_D 0xfff0707f
-+#define MATCH_RDTIME 0xc0102073
-+#define MASK_RDTIME 0xfffff07f
-+#define MATCH_AMOADD_D 0x302f
-+#define MASK_AMOADD_D 0xf800707f
-+#define MATCH_AMOMAX_W 0xa000202f
-+#define MASK_AMOMAX_W 0xf800707f
-+#define MATCH_C_MOVE 0x2
-+#define MASK_C_MOVE 0x801f
-+#define MATCH_FMOVN 0x6007077
-+#define MASK_FMOVN 0xfe00707f
-+#define MATCH_C_FSW 0x16
-+#define MASK_C_FSW 0x1f
-+#define MATCH_AMOADD_W 0x202f
-+#define MASK_AMOADD_W 0xf800707f
-+#define MATCH_AMOMAX_D 0xa000302f
-+#define MASK_AMOMAX_D 0xf800707f
-+#define MATCH_FMOVZ 0x4007077
-+#define MASK_FMOVZ 0xfe00707f
-+#define MATCH_CUSTOM1_RS1_RS2 0x302b
-+#define MASK_CUSTOM1_RS1_RS2 0x707f
-+#define MATCH_FMV_X_H 0xe4000053
-+#define MASK_FMV_X_H 0xfff0707f
-+#define MATCH_VSD 0x600207b
-+#define MASK_VSD 0xfff0707f
-+#define MATCH_VLSEGSTW 0x400305b
-+#define MASK_VLSEGSTW 0x1e00707f
-+#define MATCH_C_ADDI 0x1
-+#define MASK_C_ADDI 0x1f
-+#define MATCH_C_SLLIW 0x1819
-+#define MASK_C_SLLIW 0x1c1f
-+#define MATCH_VLSEGSTB 0x305b
-+#define MASK_VLSEGSTB 0x1e00707f
-+#define MATCH_VLSEGSTD 0x600305b
-+#define MASK_VLSEGSTD 0x1e00707f
-+#define MATCH_VLSEGSTH 0x200305b
-+#define MASK_VLSEGSTH 0x1e00707f
-+#define MATCH_MULHU 0x2003033
-+#define MASK_MULHU 0xfe00707f
-+#define MATCH_AMOMIN_W 0x8000202f
-+#define MASK_AMOMIN_W 0xf800707f
-+#define MATCH_C_SLLI32 0x419
-+#define MASK_C_SLLI32 0x1c1f
-+#define MATCH_C_ADD3 0x1c
-+#define MASK_C_ADD3 0x31f
-+#define MATCH_VGETVL 0x200400b
-+#define MASK_VGETVL 0xfffff07f
-+#define MATCH_AMOMIN_D 0x8000302f
-+#define MASK_AMOMIN_D 0xf800707f
-+#define MATCH_FCVT_W_H 0x54000053
-+#define MASK_FCVT_W_H 0xfff0007f
-+#define MATCH_VLSEGB 0x205b
-+#define MASK_VLSEGB 0x1ff0707f
-+#define MATCH_FSD 0x3027
-+#define MASK_FSD 0x707f
-+#define MATCH_VLSEGD 0x600205b
-+#define MASK_VLSEGD 0x1ff0707f
-+#define MATCH_FSH 0x1027
-+#define MASK_FSH 0x707f
-+#define MATCH_VLSEGH 0x200205b
-+#define MASK_VLSEGH 0x1ff0707f
-+#define MATCH_C_SUB 0x801a
-+#define MASK_C_SUB 0x801f
-+#define MATCH_VLSEGW 0x400205b
-+#define MASK_VLSEGW 0x1ff0707f
-+#define MATCH_FSW 0x2027
-+#define MASK_FSW 0x707f
-+#define MATCH_C_J 0x8002
-+#define MASK_C_J 0x801f
-+#define CSR_FFLAGS 0x1
-+#define CSR_FRM 0x2
-+#define CSR_FCSR 0x3
-+#define CSR_STATS 0xc0
-+#define CSR_SUP0 0x500
-+#define CSR_SUP1 0x501
-+#define CSR_EPC 0x502
-+#define CSR_BADVADDR 0x503
-+#define CSR_PTBR 0x504
-+#define CSR_ASID 0x505
-+#define CSR_COUNT 0x506
-+#define CSR_COMPARE 0x507
-+#define CSR_EVEC 0x508
-+#define CSR_CAUSE 0x509
-+#define CSR_STATUS 0x50a
-+#define CSR_HARTID 0x50b
-+#define CSR_IMPL 0x50c
-+#define CSR_FATC 0x50d
-+#define CSR_SEND_IPI 0x50e
-+#define CSR_CLEAR_IPI 0x50f
-+#define CSR_RESET 0x51d
-+#define CSR_TOHOST 0x51e
-+#define CSR_FROMHOST 0x51f
-+#define CSR_CYCLE 0xc00
-+#define CSR_TIME 0xc01
-+#define CSR_INSTRET 0xc02
-+#define CSR_UARCH0 0xcc0
-+#define CSR_UARCH1 0xcc1
-+#define CSR_UARCH2 0xcc2
-+#define CSR_UARCH3 0xcc3
-+#define CSR_UARCH4 0xcc4
-+#define CSR_UARCH5 0xcc5
-+#define CSR_UARCH6 0xcc6
-+#define CSR_UARCH7 0xcc7
-+#define CSR_UARCH8 0xcc8
-+#define CSR_UARCH9 0xcc9
-+#define CSR_UARCH10 0xcca
-+#define CSR_UARCH11 0xccb
-+#define CSR_UARCH12 0xccc
-+#define CSR_UARCH13 0xccd
-+#define CSR_UARCH14 0xcce
-+#define CSR_UARCH15 0xccf
-+#define CSR_COUNTH 0x586
-+#define CSR_CYCLEH 0xc80
-+#define CSR_TIMEH 0xc81
-+#define CSR_INSTRETH 0xc82
-+#define CAUSE_MISALIGNED_FETCH 0x0
-+#define CAUSE_FAULT_FETCH 0x1
-+#define CAUSE_ILLEGAL_INSTRUCTION 0x2
-+#define CAUSE_PRIVILEGED_INSTRUCTION 0x3
-+#define CAUSE_FP_DISABLED 0x4
-+#define CAUSE_SYSCALL 0x6
-+#define CAUSE_BREAKPOINT 0x7
-+#define CAUSE_MISALIGNED_LOAD 0x8
-+#define CAUSE_MISALIGNED_STORE 0x9
-+#define CAUSE_FAULT_LOAD 0xa
-+#define CAUSE_FAULT_STORE 0xb
-+#define CAUSE_ACCELERATOR_DISABLED 0xc
-+#endif
-+#ifdef DECLARE_INSN
-+DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
-+DECLARE_INSN(vlsegstwu, MATCH_VLSEGSTWU, MASK_VLSEGSTWU)
-+DECLARE_INSN(c_lw0, MATCH_C_LW0, MASK_C_LW0)
-+DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
-+DECLARE_INSN(vlh, MATCH_VLH, MASK_VLH)
-+DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
-+DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
-+DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
-+DECLARE_INSN(vld, MATCH_VLD, MASK_VLD)
-+DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
-+DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
-+DECLARE_INSN(vlw, MATCH_VLW, MASK_VLW)
-+DECLARE_INSN(vssegstw, MATCH_VSSEGSTW, MASK_VSSEGSTW)
-+DECLARE_INSN(utidx, MATCH_UTIDX, MASK_UTIDX)
-+DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
-+DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
-+DECLARE_INSN(vssegstd, MATCH_VSSEGSTD, MASK_VSSEGSTD)
-+DECLARE_INSN(vssegstb, MATCH_VSSEGSTB, MASK_VSSEGSTB)
-+DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
-+DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X)
-+DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
-+DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM)
-+DECLARE_INSN(vfmsv_s, MATCH_VFMSV_S, MASK_VFMSV_S)
-+DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
-+DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
-+DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
-+DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
-+DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H)
-+DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H)
-+DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
-+DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL)
-+DECLARE_INSN(vfmsv_d, MATCH_VFMSV_D, MASK_VFMSV_D)
-+DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
-+DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
-+DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
-+DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
-+DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
-+DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
-+DECLARE_INSN(vsstw, MATCH_VSSTW, MASK_VSSTW)
-+DECLARE_INSN(vssth, MATCH_VSSTH, MASK_VSSTH)
-+DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
-+DECLARE_INSN(vsstb, MATCH_VSSTB, MASK_VSSTB)
-+DECLARE_INSN(vsstd, MATCH_VSSTD, MASK_VSSTD)
-+DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
-+DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH)
-+DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
-+DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
-+DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
-+DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
-+DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
-+DECLARE_INSN(venqimm1, MATCH_VENQIMM1, MASK_VENQIMM1)
-+DECLARE_INSN(venqimm2, MATCH_VENQIMM2, MASK_VENQIMM2)
-+DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET)
-+DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
-+DECLARE_INSN(vlstw, MATCH_VLSTW, MASK_VLSTW)
-+DECLARE_INSN(vlsth, MATCH_VLSTH, MASK_VLSTH)
-+DECLARE_INSN(vlstb, MATCH_VLSTB, MASK_VLSTB)
-+DECLARE_INSN(vlstd, MATCH_VLSTD, MASK_VLSTD)
-+DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
-+DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
-+DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
-+DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
-+DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
-+DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
-+DECLARE_INSN(vlsegstbu, MATCH_VLSEGSTBU, MASK_VLSEGSTBU)
-+DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
-+DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
-+DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
-+DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
-+DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
-+DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
-+DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H)
-+DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
-+DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
-+DECLARE_INSN(vlstbu, MATCH_VLSTBU, MASK_VLSTBU)
-+DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
-+DECLARE_INSN(flh, MATCH_FLH, MASK_FLH)
-+DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
-+DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
-+DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
-+DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU)
-+DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
-+DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
-+DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
-+DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
-+DECLARE_INSN(vxcptsave, MATCH_VXCPTSAVE, MASK_VXCPTSAVE)
-+DECLARE_INSN(vmsv, MATCH_VMSV, MASK_VMSV)
-+DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
-+DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
-+DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS)
-+DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
-+DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
-+DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H)
-+DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
-+DECLARE_INSN(vxcptkill, MATCH_VXCPTKILL, MASK_VXCPTKILL)
-+DECLARE_INSN(stop, MATCH_STOP, MASK_STOP)
-+DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
-+DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_H, MASK_FSGNJN_H)
-+DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
-+DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
-+DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
-+DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
-+DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H)
-+DECLARE_INSN(vssegsth, MATCH_VSSEGSTH, MASK_VSSEGSTH)
-+DECLARE_INSN(sw, MATCH_SW, MASK_SW)
-+DECLARE_INSN(vlstwu, MATCH_VLSTWU, MASK_VLSTWU)
-+DECLARE_INSN(vfssegw, MATCH_VFSSEGW, MASK_VFSSEGW)
-+DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
-+DECLARE_INSN(sh, MATCH_SH, MASK_SH)
-+DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H)
-+DECLARE_INSN(vxcptaux, MATCH_VXCPTAUX, MASK_VXCPTAUX)
-+DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
-+DECLARE_INSN(vfssegd, MATCH_VFSSEGD, MASK_VFSSEGD)
-+DECLARE_INSN(vlseghu, MATCH_VLSEGHU, MASK_VLSEGHU)
-+DECLARE_INSN(movn, MATCH_MOVN, MASK_MOVN)
-+DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
-+DECLARE_INSN(vlsthu, MATCH_VLSTHU, MASK_VLSTHU)
-+DECLARE_INSN(movz, MATCH_MOVZ, MASK_MOVZ)
-+DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
-+DECLARE_INSN(ld, MATCH_LD, MASK_LD)
-+DECLARE_INSN(lb, MATCH_LB, MASK_LB)
-+DECLARE_INSN(vlwu, MATCH_VLWU, MASK_VLWU)
-+DECLARE_INSN(lh, MATCH_LH, MASK_LH)
-+DECLARE_INSN(lw, MATCH_LW, MASK_LW)
-+DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
-+DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H)
-+DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
-+DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
-+DECLARE_INSN(vflstd, MATCH_VFLSTD, MASK_VFLSTD)
-+DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
-+DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_H, MASK_FCVT_S_H)
-+DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR)
-+DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
-+DECLARE_INSN(vflstw, MATCH_VFLSTW, MASK_VFLSTW)
-+DECLARE_INSN(vxcptevac, MATCH_VXCPTEVAC, MASK_VXCPTEVAC)
-+DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
-+DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS)
-+DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
-+DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
-+DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
-+DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
-+DECLARE_INSN(vflsegw, MATCH_VFLSEGW, MASK_VFLSEGW)
-+DECLARE_INSN(c_ld0, MATCH_C_LD0, MASK_C_LD0)
-+DECLARE_INSN(vlsegbu, MATCH_VLSEGBU, MASK_VLSEGBU)
-+DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
-+DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
-+DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
-+DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
-+DECLARE_INSN(rem, MATCH_REM, MASK_REM)
-+DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
-+DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
-+DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH)
-+DECLARE_INSN(vlsegsthu, MATCH_VLSEGSTHU, MASK_VLSEGSTHU)
-+DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
-+DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
-+DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H)
-+DECLARE_INSN(vflsegd, MATCH_VFLSEGD, MASK_VFLSEGD)
-+DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
-+DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
-+DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
-+DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_H, MASK_FSGNJX_H)
-+DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
-+DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
-+DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
-+DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H)
-+DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
-+DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
-+DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
-+DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32)
-+DECLARE_INSN(c_srli32, MATCH_C_SRLI32, MASK_C_SRLI32)
-+DECLARE_INSN(vfsstw, MATCH_VFSSTW, MASK_VFSSTW)
-+DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
-+DECLARE_INSN(c_beq, MATCH_C_BEQ, MASK_C_BEQ)
-+DECLARE_INSN(vfsstd, MATCH_VFSSTD, MASK_VFSSTD)
-+DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
-+DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
-+DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
-+DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU)
-+DECLARE_INSN(vmvv, MATCH_VMVV, MASK_VMVV)
-+DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
-+DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
-+DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
-+DECLARE_INSN(and, MATCH_AND, MASK_AND)
-+DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
-+DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
-+DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
-+DECLARE_INSN(c_sub3, MATCH_C_SUB3, MASK_C_SUB3)
-+DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H)
-+DECLARE_INSN(vlb, MATCH_VLB, MASK_VLB)
-+DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
-+DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
-+DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
-+DECLARE_INSN(vlsegwu, MATCH_VLSEGWU, MASK_VLSEGWU)
-+DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
-+DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
-+DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
-+DECLARE_INSN(vfsw, MATCH_VFSW, MASK_VFSW)
-+DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
-+DECLARE_INSN(sb, MATCH_SB, MASK_SB)
-+DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
-+DECLARE_INSN(vfsd, MATCH_VFSD, MASK_VFSD)
-+DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
-+DECLARE_INSN(sd, MATCH_SD, MASK_SD)
-+DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
-+DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
-+DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
-+DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
-+DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE)
-+DECLARE_INSN(c_bne, MATCH_C_BNE, MASK_C_BNE)
-+DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
-+DECLARE_INSN(vxcptcause, MATCH_VXCPTCAUSE, MASK_VXCPTCAUSE)
-+DECLARE_INSN(vgetcfg, MATCH_VGETCFG, MASK_VGETCFG)
-+DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
-+DECLARE_INSN(vsetcfg, MATCH_VSETCFG, MASK_VSETCFG)
-+DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
-+DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
-+DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H)
-+DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
-+DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
-+DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
-+DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
-+DECLARE_INSN(c_srai32, MATCH_C_SRAI32, MASK_C_SRAI32)
-+DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H)
-+DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
-+DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
-+DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
-+DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
-+DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
-+DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
-+DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
-+DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
-+DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
-+DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
-+DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
-+DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
-+DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H)
-+DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
-+DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
-+DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
-+DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
-+DECLARE_INSN(fmax_h, MATCH_FMAX_H, MASK_FMAX_H)
-+DECLARE_INSN(venqcnt, MATCH_VENQCNT, MASK_VENQCNT)
-+DECLARE_INSN(vlbu, MATCH_VLBU, MASK_VLBU)
-+DECLARE_INSN(vlhu, MATCH_VLHU, MASK_VLHU)
-+DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
-+DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
-+DECLARE_INSN(c_or3, MATCH_C_OR3, MASK_C_OR3)
-+DECLARE_INSN(c_and3, MATCH_C_AND3, MASK_C_AND3)
-+DECLARE_INSN(vfssegstw, MATCH_VFSSEGSTW, MASK_VFSSEGSTW)
-+DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
-+DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
-+DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
-+DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
-+DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
-+DECLARE_INSN(vfssegstd, MATCH_VFSSEGSTD, MASK_VFSSEGSTD)
-+DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
-+DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
-+DECLARE_INSN(vf, MATCH_VF, MASK_VF)
-+DECLARE_INSN(vfmvv, MATCH_VFMVV, MASK_VFMVV)
-+DECLARE_INSN(vflsegstw, MATCH_VFLSEGSTW, MASK_VFLSEGSTW)
-+DECLARE_INSN(vxcptrestore, MATCH_VXCPTRESTORE, MASK_VXCPTRESTORE)
-+DECLARE_INSN(vxcpthold, MATCH_VXCPTHOLD, MASK_VXCPTHOLD)
-+DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
-+DECLARE_INSN(vflsegstd, MATCH_VFLSEGSTD, MASK_VFLSEGSTD)
-+DECLARE_INSN(vfld, MATCH_VFLD, MASK_VFLD)
-+DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
-+DECLARE_INSN(vflw, MATCH_VFLW, MASK_VFLW)
-+DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
-+DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H)
-+DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
-+DECLARE_INSN(vssegw, MATCH_VSSEGW, MASK_VSSEGW)
-+DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
-+DECLARE_INSN(vssegh, MATCH_VSSEGH, MASK_VSSEGH)
-+DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR)
-+DECLARE_INSN(vssegd, MATCH_VSSEGD, MASK_VSSEGD)
-+DECLARE_INSN(vssegb, MATCH_VSSEGB, MASK_VSSEGB)
-+DECLARE_INSN(fmin_h, MATCH_FMIN_H, MASK_FMIN_H)
-+DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
-+DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
-+DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
-+DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
-+DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
-+DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
-+DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H)
-+DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
-+DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
-+DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
-+DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
-+DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
-+DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
-+DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM)
-+DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
-+DECLARE_INSN(vsw, MATCH_VSW, MASK_VSW)
-+DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
-+DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H)
-+DECLARE_INSN(vsb, MATCH_VSB, MASK_VSB)
-+DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
-+DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI)
-+DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H)
-+DECLARE_INSN(vsh, MATCH_VSH, MASK_VSH)
-+DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
-+DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S)
-+DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL)
-+DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI)
-+DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W)
-+DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L)
-+DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
-+DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
-+DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D)
-+DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK)
-+DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH)
-+DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
-+DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
-+DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
-+DECLARE_INSN(venqcmd, MATCH_VENQCMD, MASK_VENQCMD)
-+DECLARE_INSN(or, MATCH_OR, MASK_OR)
-+DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
-+DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
-+DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME)
-+DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
-+DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
-+DECLARE_INSN(c_move, MATCH_C_MOVE, MASK_C_MOVE)
-+DECLARE_INSN(fmovn, MATCH_FMOVN, MASK_FMOVN)
-+DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
-+DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
-+DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
-+DECLARE_INSN(fmovz, MATCH_FMOVZ, MASK_FMOVZ)
-+DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
-+DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H)
-+DECLARE_INSN(vsd, MATCH_VSD, MASK_VSD)
-+DECLARE_INSN(vlsegstw, MATCH_VLSEGSTW, MASK_VLSEGSTW)
-+DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
-+DECLARE_INSN(c_slliw, MATCH_C_SLLIW, MASK_C_SLLIW)
-+DECLARE_INSN(vlsegstb, MATCH_VLSEGSTB, MASK_VLSEGSTB)
-+DECLARE_INSN(vlsegstd, MATCH_VLSEGSTD, MASK_VLSEGSTD)
-+DECLARE_INSN(vlsegsth, MATCH_VLSEGSTH, MASK_VLSEGSTH)
-+DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
-+DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
-+DECLARE_INSN(c_slli32, MATCH_C_SLLI32, MASK_C_SLLI32)
-+DECLARE_INSN(c_add3, MATCH_C_ADD3, MASK_C_ADD3)
-+DECLARE_INSN(vgetvl, MATCH_VGETVL, MASK_VGETVL)
-+DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
-+DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H)
-+DECLARE_INSN(vlsegb, MATCH_VLSEGB, MASK_VLSEGB)
-+DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
-+DECLARE_INSN(vlsegd, MATCH_VLSEGD, MASK_VLSEGD)
-+DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH)
-+DECLARE_INSN(vlsegh, MATCH_VLSEGH, MASK_VLSEGH)
-+DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
-+DECLARE_INSN(vlsegw, MATCH_VLSEGW, MASK_VLSEGW)
-+DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
-+DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
-+#endif
-+#ifdef DECLARE_CSR
-+DECLARE_CSR(fflags, CSR_FFLAGS)
-+DECLARE_CSR(frm, CSR_FRM)
-+DECLARE_CSR(fcsr, CSR_FCSR)
-+DECLARE_CSR(stats, CSR_STATS)
-+DECLARE_CSR(sup0, CSR_SUP0)
-+DECLARE_CSR(sup1, CSR_SUP1)
-+DECLARE_CSR(epc, CSR_EPC)
-+DECLARE_CSR(badvaddr, CSR_BADVADDR)
-+DECLARE_CSR(ptbr, CSR_PTBR)
-+DECLARE_CSR(asid, CSR_ASID)
-+DECLARE_CSR(count, CSR_COUNT)
-+DECLARE_CSR(compare, CSR_COMPARE)
-+DECLARE_CSR(evec, CSR_EVEC)
-+DECLARE_CSR(cause, CSR_CAUSE)
-+DECLARE_CSR(status, CSR_STATUS)
-+DECLARE_CSR(hartid, CSR_HARTID)
-+DECLARE_CSR(impl, CSR_IMPL)
-+DECLARE_CSR(fatc, CSR_FATC)
-+DECLARE_CSR(send_ipi, CSR_SEND_IPI)
-+DECLARE_CSR(clear_ipi, CSR_CLEAR_IPI)
-+DECLARE_CSR(reset, CSR_RESET)
-+DECLARE_CSR(tohost, CSR_TOHOST)
-+DECLARE_CSR(fromhost, CSR_FROMHOST)
-+DECLARE_CSR(cycle, CSR_CYCLE)
-+DECLARE_CSR(time, CSR_TIME)
-+DECLARE_CSR(instret, CSR_INSTRET)
-+DECLARE_CSR(uarch0, CSR_UARCH0)
-+DECLARE_CSR(uarch1, CSR_UARCH1)
-+DECLARE_CSR(uarch2, CSR_UARCH2)
-+DECLARE_CSR(uarch3, CSR_UARCH3)
-+DECLARE_CSR(uarch4, CSR_UARCH4)
-+DECLARE_CSR(uarch5, CSR_UARCH5)
-+DECLARE_CSR(uarch6, CSR_UARCH6)
-+DECLARE_CSR(uarch7, CSR_UARCH7)
-+DECLARE_CSR(uarch8, CSR_UARCH8)
-+DECLARE_CSR(uarch9, CSR_UARCH9)
-+DECLARE_CSR(uarch10, CSR_UARCH10)
-+DECLARE_CSR(uarch11, CSR_UARCH11)
-+DECLARE_CSR(uarch12, CSR_UARCH12)
-+DECLARE_CSR(uarch13, CSR_UARCH13)
-+DECLARE_CSR(uarch14, CSR_UARCH14)
-+DECLARE_CSR(uarch15, CSR_UARCH15)
-+DECLARE_CSR(counth, CSR_COUNTH)
-+DECLARE_CSR(cycleh, CSR_CYCLEH)
-+DECLARE_CSR(timeh, CSR_TIMEH)
-+DECLARE_CSR(instreth, CSR_INSTRETH)
-+#endif
-+#ifdef DECLARE_CAUSE
-+DECLARE_CAUSE("fflags", CAUSE_FFLAGS)
-+DECLARE_CAUSE("frm", CAUSE_FRM)
-+DECLARE_CAUSE("fcsr", CAUSE_FCSR)
-+DECLARE_CAUSE("stats", CAUSE_STATS)
-+DECLARE_CAUSE("sup0", CAUSE_SUP0)
-+DECLARE_CAUSE("sup1", CAUSE_SUP1)
-+DECLARE_CAUSE("epc", CAUSE_EPC)
-+DECLARE_CAUSE("badvaddr", CAUSE_BADVADDR)
-+DECLARE_CAUSE("ptbr", CAUSE_PTBR)
-+DECLARE_CAUSE("asid", CAUSE_ASID)
-+DECLARE_CAUSE("count", CAUSE_COUNT)
-+DECLARE_CAUSE("compare", CAUSE_COMPARE)
-+DECLARE_CAUSE("evec", CAUSE_EVEC)
-+DECLARE_CAUSE("cause", CAUSE_CAUSE)
-+DECLARE_CAUSE("status", CAUSE_STATUS)
-+DECLARE_CAUSE("hartid", CAUSE_HARTID)
-+DECLARE_CAUSE("impl", CAUSE_IMPL)
-+DECLARE_CAUSE("fatc", CAUSE_FATC)
-+DECLARE_CAUSE("send_ipi", CAUSE_SEND_IPI)
-+DECLARE_CAUSE("clear_ipi", CAUSE_CLEAR_IPI)
-+DECLARE_CAUSE("reset", CAUSE_RESET)
-+DECLARE_CAUSE("tohost", CAUSE_TOHOST)
-+DECLARE_CAUSE("fromhost", CAUSE_FROMHOST)
-+DECLARE_CAUSE("cycle", CAUSE_CYCLE)
-+DECLARE_CAUSE("time", CAUSE_TIME)
-+DECLARE_CAUSE("instret", CAUSE_INSTRET)
-+DECLARE_CAUSE("uarch0", CAUSE_UARCH0)
-+DECLARE_CAUSE("uarch1", CAUSE_UARCH1)
-+DECLARE_CAUSE("uarch2", CAUSE_UARCH2)
-+DECLARE_CAUSE("uarch3", CAUSE_UARCH3)
-+DECLARE_CAUSE("uarch4", CAUSE_UARCH4)
-+DECLARE_CAUSE("uarch5", CAUSE_UARCH5)
-+DECLARE_CAUSE("uarch6", CAUSE_UARCH6)
-+DECLARE_CAUSE("uarch7", CAUSE_UARCH7)
-+DECLARE_CAUSE("uarch8", CAUSE_UARCH8)
-+DECLARE_CAUSE("uarch9", CAUSE_UARCH9)
-+DECLARE_CAUSE("uarch10", CAUSE_UARCH10)
-+DECLARE_CAUSE("uarch11", CAUSE_UARCH11)
-+DECLARE_CAUSE("uarch12", CAUSE_UARCH12)
-+DECLARE_CAUSE("uarch13", CAUSE_UARCH13)
-+DECLARE_CAUSE("uarch14", CAUSE_UARCH14)
-+DECLARE_CAUSE("uarch15", CAUSE_UARCH15)
-+DECLARE_CAUSE("counth", CAUSE_COUNTH)
-+DECLARE_CAUSE("cycleh", CAUSE_CYCLEH)
-+DECLARE_CAUSE("timeh", CAUSE_TIMEH)
-+DECLARE_CAUSE("instreth", CAUSE_INSTRETH)
-+#endif
-diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
-new file mode 100644
-index 0000000..6b15dd5
---- /dev/null
-+++ b/gcc/config/riscv/riscv-protos.h
-@@ -0,0 +1,91 @@
-+/* Definition of RISC-V target for GNU compiler.
-+ Copyright (C) 2011-2014 Free Software Foundation, Inc.
-+ Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
-+ Based on MIPS target for GNU compiler.
-+
-+This file is part of GCC.
-+
-+GCC is free software; you can redistribute it and/or modify
-+it under the terms of the GNU General Public License as published by
-+the Free Software Foundation; either version 3, or (at your option)
-+any later version.
-+
-+GCC is distributed in the hope that it will be useful,
-+but WITHOUT ANY WARRANTY; without even the implied warranty of
-+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+GNU General Public License for more details.
-+
-+You should have received a copy of the GNU General Public License
-+along with GCC; see the file COPYING3. If not see
-+<http://www.gnu.org/licenses/>. */
-+
-+#ifndef GCC_RISCV_PROTOS_H
-+#define GCC_RISCV_PROTOS_H
-+
-+enum mips_symbol_type {
-+ SYMBOL_ABSOLUTE,
-+ SYMBOL_GOT_DISP,
-+ SYMBOL_TLS,
-+ SYMBOL_TLS_LE,
-+ SYMBOL_TLS_IE,
-+ SYMBOL_TLS_GD
-+};
-+#define NUM_SYMBOL_TYPES (SYMBOL_TLS_GD + 1)
-+
-+extern bool mips_symbolic_constant_p (rtx, enum mips_symbol_type *);
-+extern int riscv_regno_mode_ok_for_base_p (int, enum machine_mode, bool);
-+extern int riscv_address_insns (rtx, enum machine_mode, bool);
-+extern int riscv_const_insns (rtx);
-+extern int riscv_split_const_insns (rtx);
-+extern int mips_load_store_insns (rtx, rtx);
-+extern rtx mips_emit_move (rtx, rtx);
-+extern bool mips_split_symbol (rtx, rtx, enum machine_mode, rtx *);
-+extern rtx mips_unspec_address (rtx, enum mips_symbol_type);
-+extern void mips_move_integer (rtx, rtx, HOST_WIDE_INT);
-+extern bool mips_legitimize_move (enum machine_mode, rtx, rtx);
-+extern bool mips_legitimize_vector_move (enum machine_mode, rtx, rtx);
-+
-+extern rtx mips_subword (rtx, bool);
-+extern bool mips_split_64bit_move_p (rtx, rtx);
-+extern void mips_split_doubleword_move (rtx, rtx);
-+extern const char *mips_output_move (rtx, rtx);
-+extern const char *mips_riscv_output_vector_move (enum machine_mode, rtx, rtx);
-+#ifdef RTX_CODE
-+extern void riscv_expand_scc (rtx *);
-+extern void riscv_expand_conditional_branch (rtx *);
-+#endif
-+extern rtx riscv_expand_call (bool, rtx, rtx, rtx);
-+extern void riscv_expand_fcc_reload (rtx, rtx, rtx);
-+extern void riscv_set_return_address (rtx, rtx);
-+extern bool riscv_expand_block_move (rtx, rtx, rtx);
-+extern void riscv_expand_synci_loop (rtx, rtx);
-+
-+extern bool riscv_expand_ext_as_unaligned_load (rtx, rtx, HOST_WIDE_INT,
-+ HOST_WIDE_INT);
-+extern bool riscv_expand_ins_as_unaligned_store (rtx, rtx, HOST_WIDE_INT,
-+ HOST_WIDE_INT);
-+extern void mips_order_regs_for_local_alloc (void);
-+
-+extern rtx riscv_return_addr (int, rtx);
-+extern HOST_WIDE_INT riscv_initial_elimination_offset (int, int);
-+extern void riscv_expand_prologue (void);
-+extern void riscv_expand_epilogue (bool);
-+extern bool mips_can_use_return_insn (void);
-+extern rtx riscv_function_value (const_tree, const_tree, enum machine_mode);
-+
-+extern enum reg_class riscv_secondary_reload_class (enum reg_class,
-+ enum machine_mode,
-+ rtx, bool);
-+extern int riscv_class_max_nregs (enum reg_class, enum machine_mode);
-+
-+extern unsigned int riscv_hard_regno_nregs (int, enum machine_mode);
-+
-+extern void irix_asm_output_align (FILE *, unsigned);
-+extern const char *current_section_name (void);
-+extern unsigned int current_section_flags (void);
-+
-+extern void riscv_expand_vector_init (rtx, rtx);
-+
-+extern bool riscv_size_ok_for_small_data_p (int size);
-+
-+#endif /* ! GCC_RISCV_PROTOS_H */
-diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
-new file mode 100644
-index 0000000..75b47e3
---- /dev/null
-+++ b/gcc/config/riscv/riscv.c
-@@ -0,0 +1,4491 @@
+diff -Nur original-gcc/gcc/config/riscv/riscv.c gcc/gcc/config/riscv/riscv.c
+--- original-gcc/gcc/config/riscv/riscv.c 1969-12-31 16:00:00.000000000 -0800
++++ gcc/gcc/config/riscv/riscv.c 2014-12-09 14:38:38.665778707 -0800
+@@ -0,0 +1,4489 @@
+/* Subroutines used for code generation for RISC-V.
+ Copyright (C) 2011-2014 Free Software Foundation, Inc.
+ Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
@@ -2652,13 +1168,13 @@ index 0000000..75b47e3
+/* Index R is the smallest register class that contains register R. */
+const enum reg_class riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = {
+ GR_REGS, GR_REGS, GR_REGS, GR_REGS,
-+ GR_REGS, GR_REGS, GR_REGS, GR_REGS,
++ GR_REGS, T_REGS, T_REGS, T_REGS,
+ GR_REGS, GR_REGS, GR_REGS, GR_REGS,
+ GR_REGS, GR_REGS, GR_REGS, GR_REGS,
+ GR_REGS, GR_REGS, GR_REGS, GR_REGS,
+ GR_REGS, GR_REGS, GR_REGS, GR_REGS,
-+ GR_REGS, GR_REGS, T_REGS, T_REGS,
-+ T_REGS, T_REGS, T_REGS, GR_REGS,
++ GR_REGS, GR_REGS, GR_REGS, GR_REGS,
++ T_REGS, T_REGS, T_REGS, T_REGS,
+ FP_REGS, FP_REGS, FP_REGS, FP_REGS,
+ FP_REGS, FP_REGS, FP_REGS, FP_REGS,
+ FP_REGS, FP_REGS, FP_REGS, FP_REGS,
@@ -3515,23 +2031,21 @@ index 0000000..75b47e3
+
+/* Return an instruction sequence that calls __tls_get_addr. SYM is
+ the TLS symbol we are referencing and TYPE is the symbol type to use
-+ (either global dynamic or local dynamic). V0 is an RTX for the
++ (either global dynamic or local dynamic). RESULT is an RTX for the
+ return value location. */
+
+static rtx
-+mips_call_tls_get_addr (rtx sym, rtx v0)
++mips_call_tls_get_addr (rtx sym, rtx result)
+{
-+ rtx insn, a0;
-+
-+ a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
++ rtx insn, a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
+
+ if (!mips_tls_symbol)
+ mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
+
+ start_sequence ();
+
-+ emit_insn (riscv_got_load_tls_gd(a0, sym));
-+ insn = riscv_expand_call (false, v0, mips_tls_symbol, const0_rtx);
++ emit_insn (riscv_got_load_tls_gd (a0, sym));
++ insn = riscv_expand_call (false, result, mips_tls_symbol, const0_rtx);
+ RTL_CONST_CALL_P (insn) = 1;
+ use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
+ insn = get_insns ();
@@ -3548,7 +2062,7 @@ index 0000000..75b47e3
+static rtx
+mips_legitimize_tls_address (rtx loc)
+{
-+ rtx dest, insn, v0, tp, tmp1;
++ rtx dest, insn, tp, tmp1;
+ enum tls_model model = SYMBOL_REF_TLS_MODEL (loc);
+
+ /* Since we support TLS copy relocs, non-PIC TLS accesses may all use LE. */
@@ -3561,10 +2075,10 @@ index 0000000..75b47e3
+ /* Rely on section anchors for the optimization that LDM TLS
+ provides. The anchor's address is loaded with GD TLS. */
+ case TLS_MODEL_GLOBAL_DYNAMIC:
-+ v0 = gen_rtx_REG (Pmode, GP_RETURN);
-+ insn = mips_call_tls_get_addr (loc, v0);
++ tmp1 = gen_rtx_REG (Pmode, GP_RETURN);
++ insn = mips_call_tls_get_addr (loc, tmp1);
+ dest = gen_reg_rtx (Pmode);
-+ emit_libcall_block (insn, dest, v0, loc);
++ emit_libcall_block (insn, dest, tmp1, loc);
+ break;
+
+ case TLS_MODEL_INITIAL_EXEC:
@@ -4974,7 +3488,7 @@ index 0000000..75b47e3
+}
+
+/* Implement TARGET_RETURN_IN_MEMORY. Scalars and small structures
-+ that fit in two registers are returned in v0/v1. */
++ that fit in two registers are returned in a0/a1. */
+
+static bool
+mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
@@ -6511,8 +5025,8 @@ index 0000000..75b47e3
+ use_sibcall_p = absolute_symbolic_operand (fnaddr, Pmode);
+
+ /* We need two temporary registers in some cases. */
-+ temp1 = gen_rtx_REG (Pmode, GP_RETURN);
-+ temp2 = gen_rtx_REG (Pmode, GP_RETURN + 1);
++ temp1 = gen_rtx_REG (Pmode, GP_TEMP_FIRST);
++ temp2 = gen_rtx_REG (Pmode, GP_TEMP_FIRST + 1);
+
+ /* Find out which register contains the "this" pointer. */
+ if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
@@ -6697,10 +5211,10 @@ index 0000000..75b47e3
+#define OP(X) gen_int_mode (X, SImode)
+#define MATCH_LREG ((Pmode) == DImode ? MATCH_LD : MATCH_LW)
+
-+ /* auipc v0, 0
-+ l[wd] v1, target_function_offset(v0)
-+ l[wd] $static_chain, static_chain_offset(v0)
-+ jr v1
++ /* auipc t0, 0
++ l[wd] t1, target_function_offset(t0)
++ l[wd] $static_chain, static_chain_offset(t0)
++ jr t1
+ */
+
+ trampoline[0] = OP (RISCV_UTYPE (AUIPC, STATIC_CHAIN_REGNUM, 0));
@@ -6866,12 +5380,53 @@ index 0000000..75b47e3
+struct gcc_target targetm = TARGET_INITIALIZER;
+
+#include "gt-riscv.h"
-diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
-new file mode 100644
-index 0000000..9972f4a
---- /dev/null
-+++ b/gcc/config/riscv/riscv.h
-@@ -0,0 +1,1161 @@
+diff -Nur original-gcc/gcc/config/riscv/riscv-ftypes.def gcc/gcc/config/riscv/riscv-ftypes.def
+--- original-gcc/gcc/config/riscv/riscv-ftypes.def 1969-12-31 16:00:00.000000000 -0800
++++ gcc/gcc/config/riscv/riscv-ftypes.def 2014-12-09 14:31:16.745857225 -0800
+@@ -0,0 +1,39 @@
++/* Definitions of prototypes for RISC-V built-in functions.
++ Copyright (C) 2011-2014 Free Software Foundation, Inc.
++ Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
++ Based on MIPS target for GNU compiler.
++
++This file is part of GCC.
++
++GCC is free software; you can redistribute it and/or modify
++it under the terms of the GNU General Public License as published by
++the Free Software Foundation; either version 3, or (at your option)
++any later version.
++
++GCC is distributed in the hope that it will be useful,
++but WITHOUT ANY WARRANTY; without even the implied warranty of
++MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++GNU General Public License for more details.
++
++You should have received a copy of the GNU General Public License
++along with GCC; see the file COPYING3. If not see
++<http://www.gnu.org/licenses/>. */
++
++/* Invoke DEF_RISCV_FTYPE (NARGS, LIST) for each prototype used by
++ MIPS built-in functions, where:
++
++ NARGS is the number of arguments.
++ LIST contains the return-type code followed by the codes for each
++ argument type.
++
++ Argument- and return-type codes are either modes or one of the following:
++
++ VOID for void_type_node
++ INT for integer_type_node
++ POINTER for ptr_type_node
++
++ (we don't use PTR because that's a ANSI-compatibillity macro).
++
++ Please keep this list lexicographically sorted by the LIST argument. */
++
++DEF_RISCV_FTYPE (1, (VOID, VOID))
+diff -Nur original-gcc/gcc/config/riscv/riscv.h gcc/gcc/config/riscv/riscv.h
+--- original-gcc/gcc/config/riscv/riscv.h 1969-12-31 16:00:00.000000000 -0800
++++ gcc/gcc/config/riscv/riscv.h 2014-12-09 14:38:38.665778707 -0800
+@@ -0,0 +1,1154 @@
+/* Definition of RISC-V target for GNU compiler.
+ Copyright (C) 2011-2014 Free Software Foundation, Inc.
+ Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
@@ -7309,8 +5864,8 @@ index 0000000..9972f4a
+
+#define FIXED_REGISTERS \
+{ /* General registers. */ \
-+ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
-+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
++ 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* Floating-point registers. */ \
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -7319,27 +5874,27 @@ index 0000000..9972f4a
+}
+
+
-+/* Function calls clobber x16-30 (v0-1, a0-7, t0-4) and f16-31
-+ (fv0-1, fa0-7, ft0-5). The call RTLs themselves clobber x1 (ra). */
++/* a0-a7, t0-a6, fa0-fa7, and ft0-ft11 are volatile across calls.
++ The call RTLs themselves clobber ra. */
+
+#define CALL_USED_REGISTERS \
+{ /* General registers. */ \
-+ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
-+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
++ 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, \
++ 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \
+ /* Floating-point registers. */ \
-+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
++ 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, \
++ 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \
+ /* Others. */ \
+ 1, 1 \
+}
+
+#define CALL_REALLY_USED_REGISTERS \
+{ /* General registers. */ \
-+ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
-+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
++ 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, \
++ 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \
+ /* Floating-point registers. */ \
-+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
++ 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, \
++ 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \
+ /* Others. */ \
+ 1, 1 \
+}
@@ -7354,12 +5909,6 @@ index 0000000..9972f4a
+#define FP_REG_LAST 63
+#define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
+
-+#define CALLEE_SAVED_GP_REG_FIRST (GP_REG_FIRST + 2)
-+#define CALLEE_SAVED_GP_REG_LAST (CALLEE_SAVED_GP_REG_FIRST + 12 - 1)
-+
-+#define CALLEE_SAVED_FP_REG_FIRST (FP_REG_FIRST + 0)
-+#define CALLEE_SAVED_FP_REG_LAST (CALLEE_SAVED_FP_REG_FIRST + 16 - 1)
-+
+/* The DWARF 2 CFA column which tracks the return address from a
+ signal handler context. This means that to maintain backwards
+ compatibility, no hard register can be assigned this column if it
@@ -7390,9 +5939,9 @@ index 0000000..9972f4a
+ && GET_MODE_CLASS (MODE2) == MODE_INT))
+
+/* Use s0 as the frame pointer if it is so requested. */
-+#define HARD_FRAME_POINTER_REGNUM 2
-+#define STACK_POINTER_REGNUM 14
-+#define THREAD_POINTER_REGNUM 15
++#define HARD_FRAME_POINTER_REGNUM 8
++#define STACK_POINTER_REGNUM 2
++#define THREAD_POINTER_REGNUM 3
+
+/* These two registers don't really exist: they get eliminated to either
+ the stack or hard frame pointer. */
@@ -7403,7 +5952,7 @@ index 0000000..9972f4a
+#define HARD_FRAME_POINTER_IS_ARG_POINTER 0
+
+/* Register in which static-chain is passed to a function. */
-+#define STATIC_CHAIN_REGNUM GP_RETURN
++#define STATIC_CHAIN_REGNUM GP_TEMP_FIRST
+
+/* Registers used as temporaries in prologue/epilogue code.
+
@@ -7412,8 +5961,8 @@ index 0000000..9972f4a
+ The epilogue temporary mustn't conflict with the return registers,
+ the frame pointer, the EH stack adjustment, or the EH data registers. */
+
-+#define RISCV_PROLOGUE_TEMP_REGNUM GP_TEMP_FIRST
-+#define RISCV_EPILOGUE_TEMP_REGNUM GP_TEMP_FIRST
++#define RISCV_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST + 1)
++#define RISCV_EPILOGUE_TEMP_REGNUM RISCV_PROLOGUE_TEMP_REGNUM
+
+#define RISCV_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP_REGNUM)
+#define RISCV_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, RISCV_EPILOGUE_TEMP_REGNUM)
@@ -7490,7 +6039,7 @@ index 0000000..9972f4a
+#define REG_CLASS_CONTENTS \
+{ \
+ { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
-+ { 0x7c000000, 0x00000000, 0x00000000 }, /* T_REGS */ \
++ { 0xf00000e0, 0x00000000, 0x00000000 }, /* T_REGS */ \
+ { 0xffffffff, 0x00000000, 0x00000000 }, /* GR_REGS */ \
+ { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \
+ { 0x00000000, 0x00000000, 0x00000003 }, /* FRAME_REGS */ \
@@ -7524,15 +6073,16 @@ index 0000000..9972f4a
+#define REG_ALLOC_ORDER \
+{ \
+ /* Call-clobbered GPRs. */ \
-+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 1, \
++ 15, 14, 13, 12, 11, 10, 16, 17, 5, 6, 7, 28, 29, 30, 31, 1, \
+ /* Call-saved GPRs. */ \
-+ 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, \
++ 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \
+ /* GPRs that can never be exposed to the register allocator. */ \
-+ 0, 14, 15, \
++ 0, 2, 3, 4, \
+ /* Call-clobbered FPRs. */ \
-+ 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
++ 32, 33, 34, 35, 36, 37, 38, 39, 42, 43, 44, 45, 46, 47, 48, 49, \
++ 60, 61, 62, 63, \
+ /* Call-saved FPRs. */ \
-+ 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
++ 40, 41, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \
+ /* None of the remaining classes have defined call-saved \
+ registers. */ \
+ 64, 65 \
@@ -7615,17 +6165,17 @@ index 0000000..9972f4a
+/* Symbolic macros for the registers used to return integer and floating
+ point values. */
+
-+#define GP_RETURN (GP_REG_FIRST + 16)
-+#define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 16))
++#define GP_RETURN GP_ARG_FIRST
++#define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : FP_ARG_FIRST)
+
+#define MAX_ARGS_IN_REGISTERS 8
+
+/* Symbolic macros for the first/last argument registers. */
+
-+#define GP_ARG_FIRST (GP_REG_FIRST + 18)
++#define GP_ARG_FIRST (GP_REG_FIRST + 10)
+#define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
+#define GP_TEMP_FIRST (GP_ARG_LAST + 1)
-+#define FP_ARG_FIRST (FP_REG_FIRST + 18)
++#define FP_ARG_FIRST (FP_REG_FIRST + 10)
+#define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
+
+#define LIBCALL_VALUE(MODE) \
@@ -7634,8 +6184,6 @@ index 0000000..9972f4a
+#define FUNCTION_VALUE(VALTYPE, FUNC) \
+ riscv_function_value (VALTYPE, FUNC, VOIDmode)
+
-+/* Return scalar values in v0 or fv0. */
-+
+#define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
+
+/* 1 if N is a possible register number for function argument passing.
@@ -7799,14 +6347,14 @@ index 0000000..9972f4a
+#endif
+
+#define REGISTER_NAMES \
-+{ "zero","ra", "s0", "s1", "s2", "s3", "s4", "s5", \
-+ "s6", "s7", "s8", "s9", "s10", "s11", "sp", "tp", \
-+ "v0", "v1", "a0", "a1", "a2", "a3", "a4", "a5", \
-+ "a6", "a7", "t0", "t1", "t2", "t3", "t4", "gp", \
-+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
-+ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
-+ "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \
-+ "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", \
++{ "zero","ra", "sp", "tp", "gp", "t0", "t1", "t2", \
++ "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", \
++ "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", \
++ "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", \
++ "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", \
++ "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", \
++ "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", \
++ "fs8", "fs9", "fs10","fs11","ft8", "ft9", "ft10","ft11", \
+ "arg", "frame", }
+
+#define ADDITIONAL_REGISTER_NAMES \
@@ -7843,38 +6391,38 @@ index 0000000..9972f4a
+ { "x29", 29 + GP_REG_FIRST }, \
+ { "x30", 30 + GP_REG_FIRST }, \
+ { "x31", 31 + GP_REG_FIRST }, \
-+ { "fs0", 0 + FP_REG_FIRST }, \
-+ { "fs1", 1 + FP_REG_FIRST }, \
-+ { "fs2", 2 + FP_REG_FIRST }, \
-+ { "fs3", 3 + FP_REG_FIRST }, \
-+ { "fs4", 4 + FP_REG_FIRST }, \
-+ { "fs5", 5 + FP_REG_FIRST }, \
-+ { "fs6", 6 + FP_REG_FIRST }, \
-+ { "fs7", 7 + FP_REG_FIRST }, \
-+ { "fs8", 8 + FP_REG_FIRST }, \
-+ { "fs9", 9 + FP_REG_FIRST }, \
-+ { "fs10", 10 + FP_REG_FIRST }, \
-+ { "fs11", 11 + FP_REG_FIRST }, \
-+ { "fs12", 12 + FP_REG_FIRST }, \
-+ { "fs13", 13 + FP_REG_FIRST }, \
-+ { "fs14", 14 + FP_REG_FIRST }, \
-+ { "fs15", 15 + FP_REG_FIRST }, \
-+ { "fv0", 16 + FP_REG_FIRST }, \
-+ { "fv1", 17 + FP_REG_FIRST }, \
-+ { "fa0", 18 + FP_REG_FIRST }, \
-+ { "fa1", 19 + FP_REG_FIRST }, \
-+ { "fa2", 20 + FP_REG_FIRST }, \
-+ { "fa3", 21 + FP_REG_FIRST }, \
-+ { "fa4", 22 + FP_REG_FIRST }, \
-+ { "fa5", 23 + FP_REG_FIRST }, \
-+ { "fa6", 24 + FP_REG_FIRST }, \
-+ { "fa7", 25 + FP_REG_FIRST }, \
-+ { "ft0", 26 + FP_REG_FIRST }, \
-+ { "ft1", 27 + FP_REG_FIRST }, \
-+ { "ft2", 28 + FP_REG_FIRST }, \
-+ { "ft3", 29 + FP_REG_FIRST }, \
-+ { "ft4", 30 + FP_REG_FIRST }, \
-+ { "ft5", 31 + FP_REG_FIRST }, \
++ { "f0", 0 + FP_REG_FIRST }, \
++ { "f1", 1 + FP_REG_FIRST }, \
++ { "f2", 2 + FP_REG_FIRST }, \
++ { "f3", 3 + FP_REG_FIRST }, \
++ { "f4", 4 + FP_REG_FIRST }, \
++ { "f5", 5 + FP_REG_FIRST }, \
++ { "f6", 6 + FP_REG_FIRST }, \
++ { "f7", 7 + FP_REG_FIRST }, \
++ { "f8", 8 + FP_REG_FIRST }, \
++ { "f9", 9 + FP_REG_FIRST }, \
++ { "f10", 10 + FP_REG_FIRST }, \
++ { "f11", 11 + FP_REG_FIRST }, \
++ { "f12", 12 + FP_REG_FIRST }, \
++ { "f13", 13 + FP_REG_FIRST }, \
++ { "f14", 14 + FP_REG_FIRST }, \
++ { "f15", 15 + FP_REG_FIRST }, \
++ { "f16", 16 + FP_REG_FIRST }, \
++ { "f17", 17 + FP_REG_FIRST }, \
++ { "f18", 18 + FP_REG_FIRST }, \
++ { "f19", 19 + FP_REG_FIRST }, \
++ { "f20", 20 + FP_REG_FIRST }, \
++ { "f21", 21 + FP_REG_FIRST }, \
++ { "f22", 22 + FP_REG_FIRST }, \
++ { "f23", 23 + FP_REG_FIRST }, \
++ { "f24", 24 + FP_REG_FIRST }, \
++ { "f25", 25 + FP_REG_FIRST }, \
++ { "f26", 26 + FP_REG_FIRST }, \
++ { "f27", 27 + FP_REG_FIRST }, \
++ { "f28", 28 + FP_REG_FIRST }, \
++ { "f29", 29 + FP_REG_FIRST }, \
++ { "f30", 30 + FP_REG_FIRST }, \
++ { "f31", 31 + FP_REG_FIRST }, \
+}
+
+/* Globalizing directive for a label. */
@@ -8033,12 +6581,10 @@ index 0000000..9972f4a
+
+#define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
+ (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
-diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
-new file mode 100644
-index 0000000..92b9794
---- /dev/null
-+++ b/gcc/config/riscv/riscv.md
-@@ -0,0 +1,2390 @@
+diff -Nur original-gcc/gcc/config/riscv/riscv.md gcc/gcc/config/riscv/riscv.md
+--- original-gcc/gcc/config/riscv/riscv.md 1969-12-31 16:00:00.000000000 -0800
++++ gcc/gcc/config/riscv/riscv.md 2014-12-09 14:37:25.559138383 -0800
+@@ -0,0 +1,2411 @@
+;; Machine description for RISC-V for GNU compiler.
+;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
+;; Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
@@ -8386,9 +6932,6 @@ index 0000000..92b9794
+;; from the same template.
+(define_code_iterator any_mod [mod umod])
+
-+;; Equality operators.
-+(define_code_iterator equality_op [eq ne])
-+
+;; These code iterators allow the signed and unsigned scc operations to use
+;; the same template.
+(define_code_iterator any_gt [gt gtu])
@@ -8429,13 +6972,6 @@ index 0000000..92b9794
+ (plus "add")
+ (minus "sub")])
+
-+;; The value of the bit when the branch is taken for branch_bit patterns.
-+;; Comparison is always against zero so this depends on the operator.
-+(define_code_attr bbv [(eq "0") (ne "1")])
-+
-+;; This is the inverse value of bbv.
-+(define_code_attr bbinv [(eq "1") (ne "0")])
-+
+;; Pipeline descriptions.
+;;
+;; generic.md provides a fallback for processors without a specific
@@ -10011,6 +8547,37 @@ index 0000000..92b9794
+ DONE;
+})
+
++(define_insn_and_split "*bbs<GPR:mode>"
++ [(set (pc)
++ (if_then_else
++ (match_operator 0 "equality_operator"
++ [(zero_extract:GPR (match_operand:GPR 2 "register_operand" "r")
++ (const_int 1)
++ (match_operand 3 "const_int_operand"))
++ (const_int 0)])
++ (label_ref (match_operand 1))
++ (pc)))
++ (clobber (match_scratch:GPR 4 "=&r"))]
++ ""
++ "#"
++ "reload_completed"
++ [(set (match_dup 4)
++ (ashift:GPR (match_dup 2) (match_dup 3)))
++ (set (pc)
++ (if_then_else
++ (match_op_dup 0 [(match_dup 4) (const_int 0)])
++ (label_ref (match_operand 1))
++ (pc)))]
++{
++ int shift = GET_MODE_BITSIZE (<MODE>mode) - 1 - INTVAL (operands[3]);
++ operands[3] = GEN_INT (shift);
++
++ if (GET_CODE (operands[0]) == EQ)
++ operands[0] = gen_rtx_GE (<MODE>mode, operands[4], const0_rtx);
++ else
++ operands[0] = gen_rtx_LT (<MODE>mode, operands[4], const0_rtx);
++})
++
+;;
+;; ....................
+;;
@@ -10429,11 +8996,1259 @@ index 0000000..92b9794
+
+(include "sync.md")
+(include "peephole.md")
-diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
-new file mode 100644
-index 0000000..0fdcb73
---- /dev/null
-+++ b/gcc/config/riscv/riscv.opt
+diff -Nur original-gcc/gcc/config/riscv/riscv-modes.def gcc/gcc/config/riscv/riscv-modes.def
+--- original-gcc/gcc/config/riscv/riscv-modes.def 1969-12-31 16:00:00.000000000 -0800
++++ gcc/gcc/config/riscv/riscv-modes.def 2014-12-09 14:31:16.745857225 -0800
+@@ -0,0 +1,26 @@
++/* Extra machine modes for RISC-V target.
++ Copyright (C) 2011-2014 Free Software Foundation, Inc.
++ Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
++ Based on MIPS target for GNU compiler.
++
++This file is part of GCC.
++
++GCC is free software; you can redistribute it and/or modify
++it under the terms of the GNU General Public License as published by
++the Free Software Foundation; either version 3, or (at your option)
++any later version.
++
++GCC is distributed in the hope that it will be useful,
++but WITHOUT ANY WARRANTY; without even the implied warranty of
++MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++GNU General Public License for more details.
++
++You should have received a copy of the GNU General Public License
++along with GCC; see the file COPYING3. If not see
++<http://www.gnu.org/licenses/>. */
++
++FLOAT_MODE (TF, 16, ieee_quad_format);
++
++/* Vector modes. */
++VECTOR_MODES (INT, 4); /* V8QI V4HI V2SI */
++VECTOR_MODES (FLOAT, 4); /* V4HF V2SF */
+diff -Nur original-gcc/gcc/config/riscv/riscv-opc.h gcc/gcc/config/riscv/riscv-opc.h
+--- original-gcc/gcc/config/riscv/riscv-opc.h 1969-12-31 16:00:00.000000000 -0800
++++ gcc/gcc/config/riscv/riscv-opc.h 2014-12-09 14:31:16.745857225 -0800
+@@ -0,0 +1,1216 @@
++/* Automatically generated by parse-opcodes */
++#ifndef RISCV_ENCODING_H
++#define RISCV_ENCODING_H
++#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
++#define MASK_CUSTOM3_RD_RS1_RS2 0x707f
++#define MATCH_VLSEGSTWU 0xc00305b
++#define MASK_VLSEGSTWU 0x1e00707f
++#define MATCH_C_LW0 0x12
++#define MASK_C_LW0 0x801f
++#define MATCH_FMV_D_X 0xf2000053
++#define MASK_FMV_D_X 0xfff0707f
++#define MATCH_VLH 0x200205b
++#define MASK_VLH 0xfff0707f
++#define MATCH_C_LI 0x0
++#define MASK_C_LI 0x1f
++#define MATCH_FADD_D 0x2000053
++#define MASK_FADD_D 0xfe00007f
++#define MATCH_C_LD 0x9
++#define MASK_C_LD 0x1f
++#define MATCH_VLD 0x600205b
++#define MASK_VLD 0xfff0707f
++#define MATCH_FADD_S 0x53
++#define MASK_FADD_S 0xfe00007f
++#define MATCH_C_LW 0xa
++#define MASK_C_LW 0x1f
++#define MATCH_VLW 0x400205b
++#define MASK_VLW 0xfff0707f
++#define MATCH_VSSEGSTW 0x400307b
++#define MASK_VSSEGSTW 0x1e00707f
++#define MATCH_UTIDX 0x6077
++#define MASK_UTIDX 0xfffff07f
++#define MATCH_C_FLW 0x14
++#define MASK_C_FLW 0x1f
++#define MATCH_FSUB_D 0xa000053
++#define MASK_FSUB_D 0xfe00007f
++#define MATCH_VSSEGSTD 0x600307b
++#define MASK_VSSEGSTD 0x1e00707f
++#define MATCH_VSSEGSTB 0x307b
++#define MASK_VSSEGSTB 0x1e00707f
++#define MATCH_DIV 0x2004033
++#define MASK_DIV 0xfe00707f
++#define MATCH_FMV_H_X 0xf4000053
++#define MASK_FMV_H_X 0xfff0707f
++#define MATCH_C_FLD 0x15
++#define MASK_C_FLD 0x1f
++#define MATCH_FRRM 0x202073
++#define MASK_FRRM 0xfffff07f
++#define MATCH_VFMSV_S 0x1000202b
++#define MASK_VFMSV_S 0xfff0707f
++#define MATCH_C_LWSP 0x5
++#define MASK_C_LWSP 0x1f
++#define MATCH_FENCE 0xf
++#define MASK_FENCE 0x707f
++#define MATCH_FNMSUB_S 0x4b
++#define MASK_FNMSUB_S 0x600007f
++#define MATCH_FLE_S 0xa0000053
++#define MASK_FLE_S 0xfe00707f
++#define MATCH_FNMSUB_H 0x400004b
++#define MASK_FNMSUB_H 0x600007f
++#define MATCH_FLE_H 0xbc000053
++#define MASK_FLE_H 0xfe00707f
++#define MATCH_FLW 0x2007
++#define MASK_FLW 0x707f
++#define MATCH_VSETVL 0x600b
++#define MASK_VSETVL 0xfff0707f
++#define MATCH_VFMSV_D 0x1200202b
++#define MASK_VFMSV_D 0xfff0707f
++#define MATCH_FLE_D 0xa2000053
++#define MASK_FLE_D 0xfe00707f
++#define MATCH_FENCE_I 0x100f
++#define MASK_FENCE_I 0x707f
++#define MATCH_FNMSUB_D 0x200004b
++#define MASK_FNMSUB_D 0x600007f
++#define MATCH_ADDW 0x3b
++#define MASK_ADDW 0xfe00707f
++#define MATCH_XOR 0x4033
++#define MASK_XOR 0xfe00707f
++#define MATCH_SUB 0x40000033
++#define MASK_SUB 0xfe00707f
++#define MATCH_VSSTW 0x400307b
++#define MASK_VSSTW 0xfe00707f
++#define MATCH_VSSTH 0x200307b
++#define MASK_VSSTH 0xfe00707f
++#define MATCH_SC_W 0x1800202f
++#define MASK_SC_W 0xf800707f
++#define MATCH_VSSTB 0x307b
++#define MASK_VSSTB 0xfe00707f
++#define MATCH_VSSTD 0x600307b
++#define MASK_VSSTD 0xfe00707f
++#define MATCH_ADDI 0x13
++#define MASK_ADDI 0x707f
++#define MATCH_RDTIMEH 0xc8102073
++#define MASK_RDTIMEH 0xfffff07f
++#define MATCH_MULH 0x2001033
++#define MASK_MULH 0xfe00707f
++#define MATCH_CSRRSI 0x6073
++#define MASK_CSRRSI 0x707f
++#define MATCH_FCVT_D_WU 0xd2100053
++#define MASK_FCVT_D_WU 0xfff0007f
++#define MATCH_MULW 0x200003b
++#define MASK_MULW 0xfe00707f
++#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
++#define MASK_CUSTOM1_RD_RS1_RS2 0x707f
++#define MATCH_VENQIMM1 0xc00302b
++#define MASK_VENQIMM1 0xfe007fff
++#define MATCH_VENQIMM2 0xe00302b
++#define MASK_VENQIMM2 0xfe007fff
++#define MATCH_RDINSTRET 0xc0202073
++#define MASK_RDINSTRET 0xfffff07f
++#define MATCH_C_SWSP 0x8
++#define MASK_C_SWSP 0x1f
++#define MATCH_VLSTW 0x400305b
++#define MASK_VLSTW 0xfe00707f
++#define MATCH_VLSTH 0x200305b
++#define MASK_VLSTH 0xfe00707f
++#define MATCH_VLSTB 0x305b
++#define MASK_VLSTB 0xfe00707f
++#define MATCH_VLSTD 0x600305b
++#define MASK_VLSTD 0xfe00707f
++#define MATCH_ANDI 0x7013
++#define MASK_ANDI 0x707f
++#define MATCH_FMV_X_S 0xe0000053
++#define MASK_FMV_X_S 0xfff0707f
++#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
++#define MASK_CUSTOM0_RD_RS1_RS2 0x707f
++#define MATCH_FNMADD_S 0x4f
++#define MASK_FNMADD_S 0x600007f
++#define MATCH_LWU 0x6003
++#define MASK_LWU 0x707f
++#define MATCH_CUSTOM0_RS1 0x200b
++#define MASK_CUSTOM0_RS1 0x707f
++#define MATCH_VLSEGSTBU 0x800305b
++#define MASK_VLSEGSTBU 0x1e00707f
++#define MATCH_FNMADD_D 0x200004f
++#define MASK_FNMADD_D 0x600007f
++#define MATCH_FCVT_W_S 0xc0000053
++#define MASK_FCVT_W_S 0xfff0007f
++#define MATCH_C_SRAI 0x1019
++#define MASK_C_SRAI 0x1c1f
++#define MATCH_MULHSU 0x2002033
++#define MASK_MULHSU 0xfe00707f
++#define MATCH_FCVT_D_LU 0xd2300053
++#define MASK_FCVT_D_LU 0xfff0007f
++#define MATCH_FCVT_W_D 0xc2000053
++#define MASK_FCVT_W_D 0xfff0007f
++#define MATCH_FSUB_H 0xc000053
++#define MASK_FSUB_H 0xfe00007f
++#define MATCH_DIVUW 0x200503b
++#define MASK_DIVUW 0xfe00707f
++#define MATCH_SLTI 0x2013
++#define MASK_SLTI 0x707f
++#define MATCH_VLSTBU 0x800305b
++#define MASK_VLSTBU 0xfe00707f
++#define MATCH_SLTU 0x3033
++#define MASK_SLTU 0xfe00707f
++#define MATCH_FLH 0x1007
++#define MASK_FLH 0x707f
++#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
++#define MASK_CUSTOM2_RD_RS1_RS2 0x707f
++#define MATCH_FLD 0x3007
++#define MASK_FLD 0x707f
++#define MATCH_FSUB_S 0x8000053
++#define MASK_FSUB_S 0xfe00007f
++#define MATCH_FCVT_H_LU 0x6c000053
++#define MASK_FCVT_H_LU 0xfff0007f
++#define MATCH_CUSTOM0 0xb
++#define MASK_CUSTOM0 0x707f
++#define MATCH_CUSTOM1 0x2b
++#define MASK_CUSTOM1 0x707f
++#define MATCH_CUSTOM2 0x5b
++#define MASK_CUSTOM2 0x707f
++#define MATCH_CUSTOM3 0x7b
++#define MASK_CUSTOM3 0x707f
++#define MATCH_VXCPTSAVE 0x302b
++#define MASK_VXCPTSAVE 0xfff07fff
++#define MATCH_VMSV 0x200202b
++#define MASK_VMSV 0xfff0707f
++#define MATCH_FCVT_LU_S 0xc0300053
++#define MASK_FCVT_LU_S 0xfff0007f
++#define MATCH_AUIPC 0x17
++#define MASK_AUIPC 0x7f
++#define MATCH_FRFLAGS 0x102073
++#define MASK_FRFLAGS 0xfffff07f
++#define MATCH_FCVT_LU_D 0xc2300053
++#define MASK_FCVT_LU_D 0xfff0007f
++#define MATCH_CSRRWI 0x5073
++#define MASK_CSRRWI 0x707f
++#define MATCH_FADD_H 0x4000053
++#define MASK_FADD_H 0xfe00007f
++#define MATCH_FSQRT_S 0x58000053
++#define MASK_FSQRT_S 0xfff0007f
++#define MATCH_VXCPTKILL 0x400302b
++#define MASK_VXCPTKILL 0xffffffff
++#define MATCH_STOP 0x5077
++#define MASK_STOP 0xffffffff
++#define MATCH_FSGNJN_S 0x20001053
++#define MASK_FSGNJN_S 0xfe00707f
++#define MATCH_FSGNJN_H 0x34000053
++#define MASK_FSGNJN_H 0xfe00707f
++#define MATCH_FSQRT_D 0x5a000053
++#define MASK_FSQRT_D 0xfff0007f
++#define MATCH_XORI 0x4013
++#define MASK_XORI 0x707f
++#define MATCH_DIVU 0x2005033
++#define MASK_DIVU 0xfe00707f
++#define MATCH_FSGNJN_D 0x22001053
++#define MASK_FSGNJN_D 0xfe00707f
++#define MATCH_FSQRT_H 0x24000053
++#define MASK_FSQRT_H 0xfff0007f
++#define MATCH_VSSEGSTH 0x200307b
++#define MASK_VSSEGSTH 0x1e00707f
++#define MATCH_SW 0x2023
++#define MASK_SW 0x707f
++#define MATCH_VLSTWU 0xc00305b
++#define MASK_VLSTWU 0xfe00707f
++#define MATCH_VFSSEGW 0x1400207b
++#define MASK_VFSSEGW 0x1ff0707f
++#define MATCH_LHU 0x5003
++#define MASK_LHU 0x707f
++#define MATCH_SH 0x1023
++#define MASK_SH 0x707f
++#define MATCH_FMSUB_H 0x4000047
++#define MASK_FMSUB_H 0x600007f
++#define MATCH_VXCPTAUX 0x200402b
++#define MASK_VXCPTAUX 0xfffff07f
++#define MATCH_FMSUB_D 0x2000047
++#define MASK_FMSUB_D 0x600007f
++#define MATCH_VFSSEGD 0x1600207b
++#define MASK_VFSSEGD 0x1ff0707f
++#define MATCH_VLSEGHU 0xa00205b
++#define MASK_VLSEGHU 0x1ff0707f
++#define MATCH_MOVN 0x2007077
++#define MASK_MOVN 0xfe00707f
++#define MATCH_CUSTOM1_RS1 0x202b
++#define MASK_CUSTOM1_RS1 0x707f
++#define MATCH_VLSTHU 0xa00305b
++#define MASK_VLSTHU 0xfe00707f
++#define MATCH_MOVZ 0x7077
++#define MASK_MOVZ 0xfe00707f
++#define MATCH_CSRRW 0x1073
++#define MASK_CSRRW 0x707f
++#define MATCH_LD 0x3003
++#define MASK_LD 0x707f
++#define MATCH_LB 0x3
++#define MASK_LB 0x707f
++#define MATCH_VLWU 0xc00205b
++#define MASK_VLWU 0xfff0707f
++#define MATCH_LH 0x1003
++#define MASK_LH 0x707f
++#define MATCH_LW 0x2003
++#define MASK_LW 0x707f
++#define MATCH_CSRRC 0x3073
++#define MASK_CSRRC 0x707f
++#define MATCH_FCVT_LU_H 0x4c000053
++#define MASK_FCVT_LU_H 0xfff0007f
++#define MATCH_FCVT_S_D 0x40100053
++#define MASK_FCVT_S_D 0xfff0007f
++#define MATCH_BGEU 0x7063
++#define MASK_BGEU 0x707f
++#define MATCH_VFLSTD 0x1600305b
++#define MASK_VFLSTD 0xfe00707f
++#define MATCH_FCVT_S_L 0xd0200053
++#define MASK_FCVT_S_L 0xfff0007f
++#define MATCH_FCVT_S_H 0x84000053
++#define MASK_FCVT_S_H 0xfff0007f
++#define MATCH_FSCSR 0x301073
++#define MASK_FSCSR 0xfff0707f
++#define MATCH_FCVT_S_W 0xd0000053
++#define MASK_FCVT_S_W 0xfff0007f
++#define MATCH_VFLSTW 0x1400305b
++#define MASK_VFLSTW 0xfe00707f
++#define MATCH_VXCPTEVAC 0x600302b
++#define MASK_VXCPTEVAC 0xfff07fff
++#define MATCH_AMOMINU_D 0xc000302f
++#define MASK_AMOMINU_D 0xf800707f
++#define MATCH_FSFLAGS 0x101073
++#define MASK_FSFLAGS 0xfff0707f
++#define MATCH_SRLI 0x5013
++#define MASK_SRLI 0xfc00707f
++#define MATCH_C_SRLI 0x819
++#define MASK_C_SRLI 0x1c1f
++#define MATCH_AMOMINU_W 0xc000202f
++#define MASK_AMOMINU_W 0xf800707f
++#define MATCH_SRLW 0x503b
++#define MASK_SRLW 0xfe00707f
++#define MATCH_VFLSEGW 0x1400205b
++#define MASK_VFLSEGW 0x1ff0707f
++#define MATCH_C_LD0 0x8012
++#define MASK_C_LD0 0x801f
++#define MATCH_VLSEGBU 0x800205b
++#define MASK_VLSEGBU 0x1ff0707f
++#define MATCH_JALR 0x67
++#define MASK_JALR 0x707f
++#define MATCH_BLT 0x4063
++#define MASK_BLT 0x707f
++#define MATCH_CUSTOM2_RD_RS1 0x605b
++#define MASK_CUSTOM2_RD_RS1 0x707f
++#define MATCH_FCLASS_S 0xe0001053
++#define MASK_FCLASS_S 0xfff0707f
++#define MATCH_REM 0x2006033
++#define MASK_REM 0xfe00707f
++#define MATCH_FCLASS_D 0xe2001053
++#define MASK_FCLASS_D 0xfff0707f
++#define MATCH_FMUL_S 0x10000053
++#define MASK_FMUL_S 0xfe00007f
++#define MATCH_RDCYCLEH 0xc8002073
++#define MASK_RDCYCLEH 0xfffff07f
++#define MATCH_VLSEGSTHU 0xa00305b
++#define MASK_VLSEGSTHU 0x1e00707f
++#define MATCH_FMUL_D 0x12000053
++#define MASK_FMUL_D 0xfe00007f
++#define MATCH_ORI 0x6013
++#define MASK_ORI 0x707f
++#define MATCH_FMUL_H 0x14000053
++#define MASK_FMUL_H 0xfe00007f
++#define MATCH_VFLSEGD 0x1600205b
++#define MASK_VFLSEGD 0x1ff0707f
++#define MATCH_FEQ_S 0xa0002053
++#define MASK_FEQ_S 0xfe00707f
++#define MATCH_FSGNJX_D 0x22002053
++#define MASK_FSGNJX_D 0xfe00707f
++#define MATCH_SRAIW 0x4000501b
++#define MASK_SRAIW 0xfe00707f
++#define MATCH_FSGNJX_H 0x3c000053
++#define MASK_FSGNJX_H 0xfe00707f
++#define MATCH_FSGNJX_S 0x20002053
++#define MASK_FSGNJX_S 0xfe00707f
++#define MATCH_FEQ_D 0xa2002053
++#define MASK_FEQ_D 0xfe00707f
++#define MATCH_CUSTOM1_RD_RS1 0x602b
++#define MASK_CUSTOM1_RD_RS1 0x707f
++#define MATCH_FEQ_H 0xac000053
++#define MASK_FEQ_H 0xfe00707f
++#define MATCH_AMOMAXU_D 0xe000302f
++#define MASK_AMOMAXU_D 0xf800707f
++#define MATCH_DIVW 0x200403b
++#define MASK_DIVW 0xfe00707f
++#define MATCH_AMOMAXU_W 0xe000202f
++#define MASK_AMOMAXU_W 0xf800707f
++#define MATCH_SRAI_RV32 0x40005013
++#define MASK_SRAI_RV32 0xfe00707f
++#define MATCH_C_SRLI32 0xc19
++#define MASK_C_SRLI32 0x1c1f
++#define MATCH_VFSSTW 0x1400307b
++#define MASK_VFSSTW 0xfe00707f
++#define MATCH_CUSTOM0_RD 0x400b
++#define MASK_CUSTOM0_RD 0x707f
++#define MATCH_C_BEQ 0x10
++#define MASK_C_BEQ 0x1f
++#define MATCH_VFSSTD 0x1600307b
++#define MASK_VFSSTD 0xfe00707f
++#define MATCH_CUSTOM3_RD_RS1 0x607b
++#define MASK_CUSTOM3_RD_RS1 0x707f
++#define MATCH_LR_D 0x1000302f
++#define MASK_LR_D 0xf9f0707f
++#define MATCH_LR_W 0x1000202f
++#define MASK_LR_W 0xf9f0707f
++#define MATCH_FCVT_H_WU 0x7c000053
++#define MASK_FCVT_H_WU 0xfff0007f
++#define MATCH_VMVV 0x200002b
++#define MASK_VMVV 0xfff0707f
++#define MATCH_SLLW 0x103b
++#define MASK_SLLW 0xfe00707f
++#define MATCH_SLLI 0x1013
++#define MASK_SLLI 0xfc00707f
++#define MATCH_BEQ 0x63
++#define MASK_BEQ 0x707f
++#define MATCH_AND 0x7033
++#define MASK_AND 0xfe00707f
++#define MATCH_LBU 0x4003
++#define MASK_LBU 0x707f
++#define MATCH_FSGNJ_S 0x20000053
++#define MASK_FSGNJ_S 0xfe00707f
++#define MATCH_FMSUB_S 0x47
++#define MASK_FMSUB_S 0x600007f
++#define MATCH_C_SUB3 0x11c
++#define MASK_C_SUB3 0x31f
++#define MATCH_FSGNJ_H 0x2c000053
++#define MASK_FSGNJ_H 0xfe00707f
++#define MATCH_VLB 0x205b
++#define MASK_VLB 0xfff0707f
++#define MATCH_C_ADDIW 0x1d
++#define MASK_C_ADDIW 0x1f
++#define MATCH_CUSTOM3_RS1_RS2 0x307b
++#define MASK_CUSTOM3_RS1_RS2 0x707f
++#define MATCH_FSGNJ_D 0x22000053
++#define MASK_FSGNJ_D 0xfe00707f
++#define MATCH_VLSEGWU 0xc00205b
++#define MASK_VLSEGWU 0x1ff0707f
++#define MATCH_FCVT_S_WU 0xd0100053
++#define MASK_FCVT_S_WU 0xfff0007f
++#define MATCH_CUSTOM3_RS1 0x207b
++#define MASK_CUSTOM3_RS1 0x707f
++#define MATCH_SC_D 0x1800302f
++#define MASK_SC_D 0xf800707f
++#define MATCH_VFSW 0x1400207b
++#define MASK_VFSW 0xfff0707f
++#define MATCH_AMOSWAP_D 0x800302f
++#define MASK_AMOSWAP_D 0xf800707f
++#define MATCH_SB 0x23
++#define MASK_SB 0x707f
++#define MATCH_AMOSWAP_W 0x800202f
++#define MASK_AMOSWAP_W 0xf800707f
++#define MATCH_VFSD 0x1600207b
++#define MASK_VFSD 0xfff0707f
++#define MATCH_CUSTOM2_RS1 0x205b
++#define MASK_CUSTOM2_RS1 0x707f
++#define MATCH_SD 0x3023
++#define MASK_SD 0x707f
++#define MATCH_FMV_S_X 0xf0000053
++#define MASK_FMV_S_X 0xfff0707f
++#define MATCH_REMUW 0x200703b
++#define MASK_REMUW 0xfe00707f
++#define MATCH_JAL 0x6f
++#define MASK_JAL 0x7f
++#define MATCH_C_FSD 0x18
++#define MASK_C_FSD 0x1f
++#define MATCH_RDCYCLE 0xc0002073
++#define MASK_RDCYCLE 0xfffff07f
++#define MATCH_C_BNE 0x11
++#define MASK_C_BNE 0x1f
++#define MATCH_C_ADD 0x1a
++#define MASK_C_ADD 0x801f
++#define MATCH_VXCPTCAUSE 0x402b
++#define MASK_VXCPTCAUSE 0xfffff07f
++#define MATCH_VGETCFG 0x400b
++#define MASK_VGETCFG 0xfffff07f
++#define MATCH_LUI 0x37
++#define MASK_LUI 0x7f
++#define MATCH_VSETCFG 0x200b
++#define MASK_VSETCFG 0x7fff
++#define MATCH_C_SDSP 0x6
++#define MASK_C_SDSP 0x1f
++#define MATCH_C_LDSP 0x4
++#define MASK_C_LDSP 0x1f
++#define MATCH_FNMADD_H 0x400004f
++#define MASK_FNMADD_H 0x600007f
++#define MATCH_CUSTOM0_RS1_RS2 0x300b
++#define MASK_CUSTOM0_RS1_RS2 0x707f
++#define MATCH_SLLI_RV32 0x1013
++#define MASK_SLLI_RV32 0xfe00707f
++#define MATCH_MUL 0x2000033
++#define MASK_MUL 0xfe00707f
++#define MATCH_CSRRCI 0x7073
++#define MASK_CSRRCI 0x707f
++#define MATCH_C_SRAI32 0x1419
++#define MASK_C_SRAI32 0x1c1f
++#define MATCH_FLT_H 0xb4000053
++#define MASK_FLT_H 0xfe00707f
++#define MATCH_SRAI 0x40005013
++#define MASK_SRAI 0xfc00707f
++#define MATCH_AMOAND_D 0x6000302f
++#define MASK_AMOAND_D 0xf800707f
++#define MATCH_FLT_D 0xa2001053
++#define MASK_FLT_D 0xfe00707f
++#define MATCH_SRAW 0x4000503b
++#define MASK_SRAW 0xfe00707f
++#define MATCH_CSRRS 0x2073
++#define MASK_CSRRS 0x707f
++#define MATCH_FLT_S 0xa0001053
++#define MASK_FLT_S 0xfe00707f
++#define MATCH_ADDIW 0x1b
++#define MASK_ADDIW 0x707f
++#define MATCH_AMOAND_W 0x6000202f
++#define MASK_AMOAND_W 0xf800707f
++#define MATCH_CUSTOM2_RD 0x405b
++#define MASK_CUSTOM2_RD 0x707f
++#define MATCH_FCVT_WU_D 0xc2100053
++#define MASK_FCVT_WU_D 0xfff0007f
++#define MATCH_AMOXOR_W 0x2000202f
++#define MASK_AMOXOR_W 0xf800707f
++#define MATCH_FCVT_D_L 0xd2200053
++#define MASK_FCVT_D_L 0xfff0007f
++#define MATCH_FCVT_WU_H 0x5c000053
++#define MASK_FCVT_WU_H 0xfff0007f
++#define MATCH_C_SLLI 0x19
++#define MASK_C_SLLI 0x1c1f
++#define MATCH_AMOXOR_D 0x2000302f
++#define MASK_AMOXOR_D 0xf800707f
++#define MATCH_FCVT_WU_S 0xc0100053
++#define MASK_FCVT_WU_S 0xfff0007f
++#define MATCH_CUSTOM3_RD 0x407b
++#define MASK_CUSTOM3_RD 0x707f
++#define MATCH_FMAX_H 0xcc000053
++#define MASK_FMAX_H 0xfe00707f
++#define MATCH_VENQCNT 0x1000302b
++#define MASK_VENQCNT 0xfe007fff
++#define MATCH_VLBU 0x800205b
++#define MASK_VLBU 0xfff0707f
++#define MATCH_VLHU 0xa00205b
++#define MASK_VLHU 0xfff0707f
++#define MATCH_C_SW 0xd
++#define MASK_C_SW 0x1f
++#define MATCH_C_SD 0xc
++#define MASK_C_SD 0x1f
++#define MATCH_C_OR3 0x21c
++#define MASK_C_OR3 0x31f
++#define MATCH_C_AND3 0x31c
++#define MASK_C_AND3 0x31f
++#define MATCH_VFSSEGSTW 0x1400307b
++#define MASK_VFSSEGSTW 0x1e00707f
++#define MATCH_SLT 0x2033
++#define MASK_SLT 0xfe00707f
++#define MATCH_AMOOR_D 0x4000302f
++#define MASK_AMOOR_D 0xf800707f
++#define MATCH_REMU 0x2007033
++#define MASK_REMU 0xfe00707f
++#define MATCH_REMW 0x200603b
++#define MASK_REMW 0xfe00707f
++#define MATCH_SLL 0x1033
++#define MASK_SLL 0xfe00707f
++#define MATCH_VFSSEGSTD 0x1600307b
++#define MASK_VFSSEGSTD 0x1e00707f
++#define MATCH_AMOOR_W 0x4000202f
++#define MASK_AMOOR_W 0xf800707f
++#define MATCH_CUSTOM2_RS1_RS2 0x305b
++#define MASK_CUSTOM2_RS1_RS2 0x707f
++#define MATCH_VF 0x10202b
++#define MASK_VF 0x1f0707f
++#define MATCH_VFMVV 0x1000002b
++#define MASK_VFMVV 0xfff0707f
++#define MATCH_VFLSEGSTW 0x1400305b
++#define MASK_VFLSEGSTW 0x1e00707f
++#define MATCH_VXCPTRESTORE 0x200302b
++#define MASK_VXCPTRESTORE 0xfff07fff
++#define MATCH_VXCPTHOLD 0x800302b
++#define MASK_VXCPTHOLD 0xffffffff
++#define MATCH_SLTIU 0x3013
++#define MASK_SLTIU 0x707f
++#define MATCH_VFLSEGSTD 0x1600305b
++#define MASK_VFLSEGSTD 0x1e00707f
++#define MATCH_VFLD 0x1600205b
++#define MASK_VFLD 0xfff0707f
++#define MATCH_FMADD_S 0x43
++#define MASK_FMADD_S 0x600007f
++#define MATCH_VFLW 0x1400205b
++#define MASK_VFLW 0xfff0707f
++#define MATCH_FMADD_D 0x2000043
++#define MASK_FMADD_D 0x600007f
++#define MATCH_FMADD_H 0x4000043
++#define MASK_FMADD_H 0x600007f
++#define MATCH_SRET 0x80000073
++#define MASK_SRET 0xffffffff
++#define MATCH_VSSEGW 0x400207b
++#define MASK_VSSEGW 0x1ff0707f
++#define MATCH_CUSTOM0_RD_RS1 0x600b
++#define MASK_CUSTOM0_RD_RS1 0x707f
++#define MATCH_VSSEGH 0x200207b
++#define MASK_VSSEGH 0x1ff0707f
++#define MATCH_FRCSR 0x302073
++#define MASK_FRCSR 0xfffff07f
++#define MATCH_VSSEGD 0x600207b
++#define MASK_VSSEGD 0x1ff0707f
++#define MATCH_VSSEGB 0x207b
++#define MASK_VSSEGB 0x1ff0707f
++#define MATCH_FMIN_H 0xc4000053
++#define MASK_FMIN_H 0xfe00707f
++#define MATCH_FMIN_D 0x2a000053
++#define MASK_FMIN_D 0xfe00707f
++#define MATCH_BLTU 0x6063
++#define MASK_BLTU 0x707f
++#define MATCH_FMIN_S 0x28000053
++#define MASK_FMIN_S 0xfe00707f
++#define MATCH_SRLI_RV32 0x5013
++#define MASK_SRLI_RV32 0xfe00707f
++#define MATCH_SLLIW 0x101b
++#define MASK_SLLIW 0xfe00707f
++#define MATCH_FMAX_S 0x28001053
++#define MASK_FMAX_S 0xfe00707f
++#define MATCH_FCVT_D_H 0x8c000053
++#define MASK_FCVT_D_H 0xfff0007f
++#define MATCH_FCVT_D_W 0xd2000053
++#define MASK_FCVT_D_W 0xfff0007f
++#define MATCH_ADD 0x33
++#define MASK_ADD 0xfe00707f
++#define MATCH_FCVT_D_S 0x42000053
++#define MASK_FCVT_D_S 0xfff0007f
++#define MATCH_FMAX_D 0x2a001053
++#define MASK_FMAX_D 0xfe00707f
++#define MATCH_BNE 0x1063
++#define MASK_BNE 0x707f
++#define MATCH_CUSTOM1_RD 0x402b
++#define MASK_CUSTOM1_RD 0x707f
++#define MATCH_FSRM 0x201073
++#define MASK_FSRM 0xfff0707f
++#define MATCH_FDIV_D 0x1a000053
++#define MASK_FDIV_D 0xfe00007f
++#define MATCH_VSW 0x400207b
++#define MASK_VSW 0xfff0707f
++#define MATCH_FCVT_L_S 0xc0200053
++#define MASK_FCVT_L_S 0xfff0007f
++#define MATCH_FDIV_H 0x1c000053
++#define MASK_FDIV_H 0xfe00007f
++#define MATCH_VSB 0x207b
++#define MASK_VSB 0xfff0707f
++#define MATCH_FDIV_S 0x18000053
++#define MASK_FDIV_S 0xfe00007f
++#define MATCH_FSRMI 0x205073
++#define MASK_FSRMI 0xfff0707f
++#define MATCH_FCVT_L_H 0x44000053
++#define MASK_FCVT_L_H 0xfff0007f
++#define MATCH_VSH 0x200207b
++#define MASK_VSH 0xfff0707f
++#define MATCH_FCVT_L_D 0xc2200053
++#define MASK_FCVT_L_D 0xfff0007f
++#define MATCH_FCVT_H_S 0x90000053
++#define MASK_FCVT_H_S 0xfff0007f
++#define MATCH_SCALL 0x73
++#define MASK_SCALL 0xffffffff
++#define MATCH_FSFLAGSI 0x105073
++#define MASK_FSFLAGSI 0xfff0707f
++#define MATCH_FCVT_H_W 0x74000053
++#define MASK_FCVT_H_W 0xfff0007f
++#define MATCH_FCVT_H_L 0x64000053
++#define MASK_FCVT_H_L 0xfff0007f
++#define MATCH_SRLIW 0x501b
++#define MASK_SRLIW 0xfe00707f
++#define MATCH_FCVT_S_LU 0xd0300053
++#define MASK_FCVT_S_LU 0xfff0007f
++#define MATCH_FCVT_H_D 0x92000053
++#define MASK_FCVT_H_D 0xfff0007f
++#define MATCH_SBREAK 0x100073
++#define MASK_SBREAK 0xffffffff
++#define MATCH_RDINSTRETH 0xc8202073
++#define MASK_RDINSTRETH 0xfffff07f
++#define MATCH_SRA 0x40005033
++#define MASK_SRA 0xfe00707f
++#define MATCH_BGE 0x5063
++#define MASK_BGE 0x707f
++#define MATCH_SRL 0x5033
++#define MASK_SRL 0xfe00707f
++#define MATCH_VENQCMD 0xa00302b
++#define MASK_VENQCMD 0xfe007fff
++#define MATCH_OR 0x6033
++#define MASK_OR 0xfe00707f
++#define MATCH_SUBW 0x4000003b
++#define MASK_SUBW 0xfe00707f
++#define MATCH_FMV_X_D 0xe2000053
++#define MASK_FMV_X_D 0xfff0707f
++#define MATCH_RDTIME 0xc0102073
++#define MASK_RDTIME 0xfffff07f
++#define MATCH_AMOADD_D 0x302f
++#define MASK_AMOADD_D 0xf800707f
++#define MATCH_AMOMAX_W 0xa000202f
++#define MASK_AMOMAX_W 0xf800707f
++#define MATCH_C_MOVE 0x2
++#define MASK_C_MOVE 0x801f
++#define MATCH_FMOVN 0x6007077
++#define MASK_FMOVN 0xfe00707f
++#define MATCH_C_FSW 0x16
++#define MASK_C_FSW 0x1f
++#define MATCH_AMOADD_W 0x202f
++#define MASK_AMOADD_W 0xf800707f
++#define MATCH_AMOMAX_D 0xa000302f
++#define MASK_AMOMAX_D 0xf800707f
++#define MATCH_FMOVZ 0x4007077
++#define MASK_FMOVZ 0xfe00707f
++#define MATCH_CUSTOM1_RS1_RS2 0x302b
++#define MASK_CUSTOM1_RS1_RS2 0x707f
++#define MATCH_FMV_X_H 0xe4000053
++#define MASK_FMV_X_H 0xfff0707f
++#define MATCH_VSD 0x600207b
++#define MASK_VSD 0xfff0707f
++#define MATCH_VLSEGSTW 0x400305b
++#define MASK_VLSEGSTW 0x1e00707f
++#define MATCH_C_ADDI 0x1
++#define MASK_C_ADDI 0x1f
++#define MATCH_C_SLLIW 0x1819
++#define MASK_C_SLLIW 0x1c1f
++#define MATCH_VLSEGSTB 0x305b
++#define MASK_VLSEGSTB 0x1e00707f
++#define MATCH_VLSEGSTD 0x600305b
++#define MASK_VLSEGSTD 0x1e00707f
++#define MATCH_VLSEGSTH 0x200305b
++#define MASK_VLSEGSTH 0x1e00707f
++#define MATCH_MULHU 0x2003033
++#define MASK_MULHU 0xfe00707f
++#define MATCH_AMOMIN_W 0x8000202f
++#define MASK_AMOMIN_W 0xf800707f
++#define MATCH_C_SLLI32 0x419
++#define MASK_C_SLLI32 0x1c1f
++#define MATCH_C_ADD3 0x1c
++#define MASK_C_ADD3 0x31f
++#define MATCH_VGETVL 0x200400b
++#define MASK_VGETVL 0xfffff07f
++#define MATCH_AMOMIN_D 0x8000302f
++#define MASK_AMOMIN_D 0xf800707f
++#define MATCH_FCVT_W_H 0x54000053
++#define MASK_FCVT_W_H 0xfff0007f
++#define MATCH_VLSEGB 0x205b
++#define MASK_VLSEGB 0x1ff0707f
++#define MATCH_FSD 0x3027
++#define MASK_FSD 0x707f
++#define MATCH_VLSEGD 0x600205b
++#define MASK_VLSEGD 0x1ff0707f
++#define MATCH_FSH 0x1027
++#define MASK_FSH 0x707f
++#define MATCH_VLSEGH 0x200205b
++#define MASK_VLSEGH 0x1ff0707f
++#define MATCH_C_SUB 0x801a
++#define MASK_C_SUB 0x801f
++#define MATCH_VLSEGW 0x400205b
++#define MASK_VLSEGW 0x1ff0707f
++#define MATCH_FSW 0x2027
++#define MASK_FSW 0x707f
++#define MATCH_C_J 0x8002
++#define MASK_C_J 0x801f
++#define CSR_FFLAGS 0x1
++#define CSR_FRM 0x2
++#define CSR_FCSR 0x3
++#define CSR_STATS 0xc0
++#define CSR_SUP0 0x500
++#define CSR_SUP1 0x501
++#define CSR_EPC 0x502
++#define CSR_BADVADDR 0x503
++#define CSR_PTBR 0x504
++#define CSR_ASID 0x505
++#define CSR_COUNT 0x506
++#define CSR_COMPARE 0x507
++#define CSR_EVEC 0x508
++#define CSR_CAUSE 0x509
++#define CSR_STATUS 0x50a
++#define CSR_HARTID 0x50b
++#define CSR_IMPL 0x50c
++#define CSR_FATC 0x50d
++#define CSR_SEND_IPI 0x50e
++#define CSR_CLEAR_IPI 0x50f
++#define CSR_RESET 0x51d
++#define CSR_TOHOST 0x51e
++#define CSR_FROMHOST 0x51f
++#define CSR_CYCLE 0xc00
++#define CSR_TIME 0xc01
++#define CSR_INSTRET 0xc02
++#define CSR_UARCH0 0xcc0
++#define CSR_UARCH1 0xcc1
++#define CSR_UARCH2 0xcc2
++#define CSR_UARCH3 0xcc3
++#define CSR_UARCH4 0xcc4
++#define CSR_UARCH5 0xcc5
++#define CSR_UARCH6 0xcc6
++#define CSR_UARCH7 0xcc7
++#define CSR_UARCH8 0xcc8
++#define CSR_UARCH9 0xcc9
++#define CSR_UARCH10 0xcca
++#define CSR_UARCH11 0xccb
++#define CSR_UARCH12 0xccc
++#define CSR_UARCH13 0xccd
++#define CSR_UARCH14 0xcce
++#define CSR_UARCH15 0xccf
++#define CSR_COUNTH 0x586
++#define CSR_CYCLEH 0xc80
++#define CSR_TIMEH 0xc81
++#define CSR_INSTRETH 0xc82
++#define CAUSE_MISALIGNED_FETCH 0x0
++#define CAUSE_FAULT_FETCH 0x1
++#define CAUSE_ILLEGAL_INSTRUCTION 0x2
++#define CAUSE_PRIVILEGED_INSTRUCTION 0x3
++#define CAUSE_FP_DISABLED 0x4
++#define CAUSE_SYSCALL 0x6
++#define CAUSE_BREAKPOINT 0x7
++#define CAUSE_MISALIGNED_LOAD 0x8
++#define CAUSE_MISALIGNED_STORE 0x9
++#define CAUSE_FAULT_LOAD 0xa
++#define CAUSE_FAULT_STORE 0xb
++#define CAUSE_ACCELERATOR_DISABLED 0xc
++#endif
++#ifdef DECLARE_INSN
++DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
++DECLARE_INSN(vlsegstwu, MATCH_VLSEGSTWU, MASK_VLSEGSTWU)
++DECLARE_INSN(c_lw0, MATCH_C_LW0, MASK_C_LW0)
++DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
++DECLARE_INSN(vlh, MATCH_VLH, MASK_VLH)
++DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
++DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
++DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
++DECLARE_INSN(vld, MATCH_VLD, MASK_VLD)
++DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
++DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
++DECLARE_INSN(vlw, MATCH_VLW, MASK_VLW)
++DECLARE_INSN(vssegstw, MATCH_VSSEGSTW, MASK_VSSEGSTW)
++DECLARE_INSN(utidx, MATCH_UTIDX, MASK_UTIDX)
++DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
++DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
++DECLARE_INSN(vssegstd, MATCH_VSSEGSTD, MASK_VSSEGSTD)
++DECLARE_INSN(vssegstb, MATCH_VSSEGSTB, MASK_VSSEGSTB)
++DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
++DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X)
++DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
++DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM)
++DECLARE_INSN(vfmsv_s, MATCH_VFMSV_S, MASK_VFMSV_S)
++DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
++DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
++DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
++DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
++DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H)
++DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H)
++DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
++DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL)
++DECLARE_INSN(vfmsv_d, MATCH_VFMSV_D, MASK_VFMSV_D)
++DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
++DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
++DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
++DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
++DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
++DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
++DECLARE_INSN(vsstw, MATCH_VSSTW, MASK_VSSTW)
++DECLARE_INSN(vssth, MATCH_VSSTH, MASK_VSSTH)
++DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
++DECLARE_INSN(vsstb, MATCH_VSSTB, MASK_VSSTB)
++DECLARE_INSN(vsstd, MATCH_VSSTD, MASK_VSSTD)
++DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
++DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH)
++DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
++DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
++DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
++DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
++DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
++DECLARE_INSN(venqimm1, MATCH_VENQIMM1, MASK_VENQIMM1)
++DECLARE_INSN(venqimm2, MATCH_VENQIMM2, MASK_VENQIMM2)
++DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET)
++DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
++DECLARE_INSN(vlstw, MATCH_VLSTW, MASK_VLSTW)
++DECLARE_INSN(vlsth, MATCH_VLSTH, MASK_VLSTH)
++DECLARE_INSN(vlstb, MATCH_VLSTB, MASK_VLSTB)
++DECLARE_INSN(vlstd, MATCH_VLSTD, MASK_VLSTD)
++DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
++DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
++DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
++DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
++DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
++DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
++DECLARE_INSN(vlsegstbu, MATCH_VLSEGSTBU, MASK_VLSEGSTBU)
++DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
++DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
++DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
++DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
++DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
++DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
++DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H)
++DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
++DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
++DECLARE_INSN(vlstbu, MATCH_VLSTBU, MASK_VLSTBU)
++DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
++DECLARE_INSN(flh, MATCH_FLH, MASK_FLH)
++DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
++DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
++DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
++DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU)
++DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
++DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
++DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
++DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
++DECLARE_INSN(vxcptsave, MATCH_VXCPTSAVE, MASK_VXCPTSAVE)
++DECLARE_INSN(vmsv, MATCH_VMSV, MASK_VMSV)
++DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
++DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
++DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS)
++DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
++DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
++DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H)
++DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
++DECLARE_INSN(vxcptkill, MATCH_VXCPTKILL, MASK_VXCPTKILL)
++DECLARE_INSN(stop, MATCH_STOP, MASK_STOP)
++DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
++DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_H, MASK_FSGNJN_H)
++DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
++DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
++DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
++DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
++DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H)
++DECLARE_INSN(vssegsth, MATCH_VSSEGSTH, MASK_VSSEGSTH)
++DECLARE_INSN(sw, MATCH_SW, MASK_SW)
++DECLARE_INSN(vlstwu, MATCH_VLSTWU, MASK_VLSTWU)
++DECLARE_INSN(vfssegw, MATCH_VFSSEGW, MASK_VFSSEGW)
++DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
++DECLARE_INSN(sh, MATCH_SH, MASK_SH)
++DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H)
++DECLARE_INSN(vxcptaux, MATCH_VXCPTAUX, MASK_VXCPTAUX)
++DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
++DECLARE_INSN(vfssegd, MATCH_VFSSEGD, MASK_VFSSEGD)
++DECLARE_INSN(vlseghu, MATCH_VLSEGHU, MASK_VLSEGHU)
++DECLARE_INSN(movn, MATCH_MOVN, MASK_MOVN)
++DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
++DECLARE_INSN(vlsthu, MATCH_VLSTHU, MASK_VLSTHU)
++DECLARE_INSN(movz, MATCH_MOVZ, MASK_MOVZ)
++DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
++DECLARE_INSN(ld, MATCH_LD, MASK_LD)
++DECLARE_INSN(lb, MATCH_LB, MASK_LB)
++DECLARE_INSN(vlwu, MATCH_VLWU, MASK_VLWU)
++DECLARE_INSN(lh, MATCH_LH, MASK_LH)
++DECLARE_INSN(lw, MATCH_LW, MASK_LW)
++DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
++DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H)
++DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
++DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
++DECLARE_INSN(vflstd, MATCH_VFLSTD, MASK_VFLSTD)
++DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
++DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_H, MASK_FCVT_S_H)
++DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR)
++DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
++DECLARE_INSN(vflstw, MATCH_VFLSTW, MASK_VFLSTW)
++DECLARE_INSN(vxcptevac, MATCH_VXCPTEVAC, MASK_VXCPTEVAC)
++DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
++DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS)
++DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
++DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
++DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
++DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
++DECLARE_INSN(vflsegw, MATCH_VFLSEGW, MASK_VFLSEGW)
++DECLARE_INSN(c_ld0, MATCH_C_LD0, MASK_C_LD0)
++DECLARE_INSN(vlsegbu, MATCH_VLSEGBU, MASK_VLSEGBU)
++DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
++DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
++DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
++DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
++DECLARE_INSN(rem, MATCH_REM, MASK_REM)
++DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
++DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
++DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH)
++DECLARE_INSN(vlsegsthu, MATCH_VLSEGSTHU, MASK_VLSEGSTHU)
++DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
++DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
++DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H)
++DECLARE_INSN(vflsegd, MATCH_VFLSEGD, MASK_VFLSEGD)
++DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
++DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
++DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
++DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_H, MASK_FSGNJX_H)
++DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
++DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
++DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
++DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H)
++DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
++DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
++DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
++DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32)
++DECLARE_INSN(c_srli32, MATCH_C_SRLI32, MASK_C_SRLI32)
++DECLARE_INSN(vfsstw, MATCH_VFSSTW, MASK_VFSSTW)
++DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
++DECLARE_INSN(c_beq, MATCH_C_BEQ, MASK_C_BEQ)
++DECLARE_INSN(vfsstd, MATCH_VFSSTD, MASK_VFSSTD)
++DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
++DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
++DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
++DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU)
++DECLARE_INSN(vmvv, MATCH_VMVV, MASK_VMVV)
++DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
++DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
++DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
++DECLARE_INSN(and, MATCH_AND, MASK_AND)
++DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
++DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
++DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
++DECLARE_INSN(c_sub3, MATCH_C_SUB3, MASK_C_SUB3)
++DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H)
++DECLARE_INSN(vlb, MATCH_VLB, MASK_VLB)
++DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
++DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
++DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
++DECLARE_INSN(vlsegwu, MATCH_VLSEGWU, MASK_VLSEGWU)
++DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
++DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
++DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
++DECLARE_INSN(vfsw, MATCH_VFSW, MASK_VFSW)
++DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
++DECLARE_INSN(sb, MATCH_SB, MASK_SB)
++DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
++DECLARE_INSN(vfsd, MATCH_VFSD, MASK_VFSD)
++DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
++DECLARE_INSN(sd, MATCH_SD, MASK_SD)
++DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
++DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
++DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
++DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
++DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE)
++DECLARE_INSN(c_bne, MATCH_C_BNE, MASK_C_BNE)
++DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
++DECLARE_INSN(vxcptcause, MATCH_VXCPTCAUSE, MASK_VXCPTCAUSE)
++DECLARE_INSN(vgetcfg, MATCH_VGETCFG, MASK_VGETCFG)
++DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
++DECLARE_INSN(vsetcfg, MATCH_VSETCFG, MASK_VSETCFG)
++DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
++DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
++DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H)
++DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
++DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
++DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
++DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
++DECLARE_INSN(c_srai32, MATCH_C_SRAI32, MASK_C_SRAI32)
++DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H)
++DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
++DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
++DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
++DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
++DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
++DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
++DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
++DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
++DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
++DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
++DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
++DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
++DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H)
++DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
++DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
++DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
++DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
++DECLARE_INSN(fmax_h, MATCH_FMAX_H, MASK_FMAX_H)
++DECLARE_INSN(venqcnt, MATCH_VENQCNT, MASK_VENQCNT)
++DECLARE_INSN(vlbu, MATCH_VLBU, MASK_VLBU)
++DECLARE_INSN(vlhu, MATCH_VLHU, MASK_VLHU)
++DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
++DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
++DECLARE_INSN(c_or3, MATCH_C_OR3, MASK_C_OR3)
++DECLARE_INSN(c_and3, MATCH_C_AND3, MASK_C_AND3)
++DECLARE_INSN(vfssegstw, MATCH_VFSSEGSTW, MASK_VFSSEGSTW)
++DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
++DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
++DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
++DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
++DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
++DECLARE_INSN(vfssegstd, MATCH_VFSSEGSTD, MASK_VFSSEGSTD)
++DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
++DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
++DECLARE_INSN(vf, MATCH_VF, MASK_VF)
++DECLARE_INSN(vfmvv, MATCH_VFMVV, MASK_VFMVV)
++DECLARE_INSN(vflsegstw, MATCH_VFLSEGSTW, MASK_VFLSEGSTW)
++DECLARE_INSN(vxcptrestore, MATCH_VXCPTRESTORE, MASK_VXCPTRESTORE)
++DECLARE_INSN(vxcpthold, MATCH_VXCPTHOLD, MASK_VXCPTHOLD)
++DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
++DECLARE_INSN(vflsegstd, MATCH_VFLSEGSTD, MASK_VFLSEGSTD)
++DECLARE_INSN(vfld, MATCH_VFLD, MASK_VFLD)
++DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
++DECLARE_INSN(vflw, MATCH_VFLW, MASK_VFLW)
++DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
++DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H)
++DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
++DECLARE_INSN(vssegw, MATCH_VSSEGW, MASK_VSSEGW)
++DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
++DECLARE_INSN(vssegh, MATCH_VSSEGH, MASK_VSSEGH)
++DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR)
++DECLARE_INSN(vssegd, MATCH_VSSEGD, MASK_VSSEGD)
++DECLARE_INSN(vssegb, MATCH_VSSEGB, MASK_VSSEGB)
++DECLARE_INSN(fmin_h, MATCH_FMIN_H, MASK_FMIN_H)
++DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
++DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
++DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
++DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
++DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
++DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
++DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H)
++DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
++DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
++DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
++DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
++DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
++DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
++DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM)
++DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
++DECLARE_INSN(vsw, MATCH_VSW, MASK_VSW)
++DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
++DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H)
++DECLARE_INSN(vsb, MATCH_VSB, MASK_VSB)
++DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
++DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI)
++DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H)
++DECLARE_INSN(vsh, MATCH_VSH, MASK_VSH)
++DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
++DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S)
++DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL)
++DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI)
++DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W)
++DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L)
++DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
++DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
++DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D)
++DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK)
++DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH)
++DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
++DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
++DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
++DECLARE_INSN(venqcmd, MATCH_VENQCMD, MASK_VENQCMD)
++DECLARE_INSN(or, MATCH_OR, MASK_OR)
++DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
++DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
++DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME)
++DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
++DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
++DECLARE_INSN(c_move, MATCH_C_MOVE, MASK_C_MOVE)
++DECLARE_INSN(fmovn, MATCH_FMOVN, MASK_FMOVN)
++DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
++DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
++DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
++DECLARE_INSN(fmovz, MATCH_FMOVZ, MASK_FMOVZ)
++DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
++DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H)
++DECLARE_INSN(vsd, MATCH_VSD, MASK_VSD)
++DECLARE_INSN(vlsegstw, MATCH_VLSEGSTW, MASK_VLSEGSTW)
++DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
++DECLARE_INSN(c_slliw, MATCH_C_SLLIW, MASK_C_SLLIW)
++DECLARE_INSN(vlsegstb, MATCH_VLSEGSTB, MASK_VLSEGSTB)
++DECLARE_INSN(vlsegstd, MATCH_VLSEGSTD, MASK_VLSEGSTD)
++DECLARE_INSN(vlsegsth, MATCH_VLSEGSTH, MASK_VLSEGSTH)
++DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
++DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
++DECLARE_INSN(c_slli32, MATCH_C_SLLI32, MASK_C_SLLI32)
++DECLARE_INSN(c_add3, MATCH_C_ADD3, MASK_C_ADD3)
++DECLARE_INSN(vgetvl, MATCH_VGETVL, MASK_VGETVL)
++DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
++DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H)
++DECLARE_INSN(vlsegb, MATCH_VLSEGB, MASK_VLSEGB)
++DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
++DECLARE_INSN(vlsegd, MATCH_VLSEGD, MASK_VLSEGD)
++DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH)
++DECLARE_INSN(vlsegh, MATCH_VLSEGH, MASK_VLSEGH)
++DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
++DECLARE_INSN(vlsegw, MATCH_VLSEGW, MASK_VLSEGW)
++DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
++DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
++#endif
++#ifdef DECLARE_CSR
++DECLARE_CSR(fflags, CSR_FFLAGS)
++DECLARE_CSR(frm, CSR_FRM)
++DECLARE_CSR(fcsr, CSR_FCSR)
++DECLARE_CSR(stats, CSR_STATS)
++DECLARE_CSR(sup0, CSR_SUP0)
++DECLARE_CSR(sup1, CSR_SUP1)
++DECLARE_CSR(epc, CSR_EPC)
++DECLARE_CSR(badvaddr, CSR_BADVADDR)
++DECLARE_CSR(ptbr, CSR_PTBR)
++DECLARE_CSR(asid, CSR_ASID)
++DECLARE_CSR(count, CSR_COUNT)
++DECLARE_CSR(compare, CSR_COMPARE)
++DECLARE_CSR(evec, CSR_EVEC)
++DECLARE_CSR(cause, CSR_CAUSE)
++DECLARE_CSR(status, CSR_STATUS)
++DECLARE_CSR(hartid, CSR_HARTID)
++DECLARE_CSR(impl, CSR_IMPL)
++DECLARE_CSR(fatc, CSR_FATC)
++DECLARE_CSR(send_ipi, CSR_SEND_IPI)
++DECLARE_CSR(clear_ipi, CSR_CLEAR_IPI)
++DECLARE_CSR(reset, CSR_RESET)
++DECLARE_CSR(tohost, CSR_TOHOST)
++DECLARE_CSR(fromhost, CSR_FROMHOST)
++DECLARE_CSR(cycle, CSR_CYCLE)
++DECLARE_CSR(time, CSR_TIME)
++DECLARE_CSR(instret, CSR_INSTRET)
++DECLARE_CSR(uarch0, CSR_UARCH0)
++DECLARE_CSR(uarch1, CSR_UARCH1)
++DECLARE_CSR(uarch2, CSR_UARCH2)
++DECLARE_CSR(uarch3, CSR_UARCH3)
++DECLARE_CSR(uarch4, CSR_UARCH4)
++DECLARE_CSR(uarch5, CSR_UARCH5)
++DECLARE_CSR(uarch6, CSR_UARCH6)
++DECLARE_CSR(uarch7, CSR_UARCH7)
++DECLARE_CSR(uarch8, CSR_UARCH8)
++DECLARE_CSR(uarch9, CSR_UARCH9)
++DECLARE_CSR(uarch10, CSR_UARCH10)
++DECLARE_CSR(uarch11, CSR_UARCH11)
++DECLARE_CSR(uarch12, CSR_UARCH12)
++DECLARE_CSR(uarch13, CSR_UARCH13)
++DECLARE_CSR(uarch14, CSR_UARCH14)
++DECLARE_CSR(uarch15, CSR_UARCH15)
++DECLARE_CSR(counth, CSR_COUNTH)
++DECLARE_CSR(cycleh, CSR_CYCLEH)
++DECLARE_CSR(timeh, CSR_TIMEH)
++DECLARE_CSR(instreth, CSR_INSTRETH)
++#endif
++#ifdef DECLARE_CAUSE
++DECLARE_CAUSE("fflags", CAUSE_FFLAGS)
++DECLARE_CAUSE("frm", CAUSE_FRM)
++DECLARE_CAUSE("fcsr", CAUSE_FCSR)
++DECLARE_CAUSE("stats", CAUSE_STATS)
++DECLARE_CAUSE("sup0", CAUSE_SUP0)
++DECLARE_CAUSE("sup1", CAUSE_SUP1)
++DECLARE_CAUSE("epc", CAUSE_EPC)
++DECLARE_CAUSE("badvaddr", CAUSE_BADVADDR)
++DECLARE_CAUSE("ptbr", CAUSE_PTBR)
++DECLARE_CAUSE("asid", CAUSE_ASID)
++DECLARE_CAUSE("count", CAUSE_COUNT)
++DECLARE_CAUSE("compare", CAUSE_COMPARE)
++DECLARE_CAUSE("evec", CAUSE_EVEC)
++DECLARE_CAUSE("cause", CAUSE_CAUSE)
++DECLARE_CAUSE("status", CAUSE_STATUS)
++DECLARE_CAUSE("hartid", CAUSE_HARTID)
++DECLARE_CAUSE("impl", CAUSE_IMPL)
++DECLARE_CAUSE("fatc", CAUSE_FATC)
++DECLARE_CAUSE("send_ipi", CAUSE_SEND_IPI)
++DECLARE_CAUSE("clear_ipi", CAUSE_CLEAR_IPI)
++DECLARE_CAUSE("reset", CAUSE_RESET)
++DECLARE_CAUSE("tohost", CAUSE_TOHOST)
++DECLARE_CAUSE("fromhost", CAUSE_FROMHOST)
++DECLARE_CAUSE("cycle", CAUSE_CYCLE)
++DECLARE_CAUSE("time", CAUSE_TIME)
++DECLARE_CAUSE("instret", CAUSE_INSTRET)
++DECLARE_CAUSE("uarch0", CAUSE_UARCH0)
++DECLARE_CAUSE("uarch1", CAUSE_UARCH1)
++DECLARE_CAUSE("uarch2", CAUSE_UARCH2)
++DECLARE_CAUSE("uarch3", CAUSE_UARCH3)
++DECLARE_CAUSE("uarch4", CAUSE_UARCH4)
++DECLARE_CAUSE("uarch5", CAUSE_UARCH5)
++DECLARE_CAUSE("uarch6", CAUSE_UARCH6)
++DECLARE_CAUSE("uarch7", CAUSE_UARCH7)
++DECLARE_CAUSE("uarch8", CAUSE_UARCH8)
++DECLARE_CAUSE("uarch9", CAUSE_UARCH9)
++DECLARE_CAUSE("uarch10", CAUSE_UARCH10)
++DECLARE_CAUSE("uarch11", CAUSE_UARCH11)
++DECLARE_CAUSE("uarch12", CAUSE_UARCH12)
++DECLARE_CAUSE("uarch13", CAUSE_UARCH13)
++DECLARE_CAUSE("uarch14", CAUSE_UARCH14)
++DECLARE_CAUSE("uarch15", CAUSE_UARCH15)
++DECLARE_CAUSE("counth", CAUSE_COUNTH)
++DECLARE_CAUSE("cycleh", CAUSE_CYCLEH)
++DECLARE_CAUSE("timeh", CAUSE_TIMEH)
++DECLARE_CAUSE("instreth", CAUSE_INSTRETH)
++#endif
+diff -Nur original-gcc/gcc/config/riscv/riscv.opt gcc/gcc/config/riscv/riscv.opt
+--- original-gcc/gcc/config/riscv/riscv.opt 1969-12-31 16:00:00.000000000 -0800
++++ gcc/gcc/config/riscv/riscv.opt 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,63 @@
+; Options for the MIPS port of the compiler
+;
@@ -10498,11 +10313,104 @@ index 0000000..0fdcb73
+matomic
+Target Report Mask(ATOMIC)
+Use hardware atomic memory instructions. Enabled by default, use -mno-atomic to disable
-diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
-new file mode 100644
-index 0000000..cdf22c6
---- /dev/null
-+++ b/gcc/config/riscv/sync.md
+diff -Nur original-gcc/gcc/config/riscv/riscv-protos.h gcc/gcc/config/riscv/riscv-protos.h
+--- original-gcc/gcc/config/riscv/riscv-protos.h 1969-12-31 16:00:00.000000000 -0800
++++ gcc/gcc/config/riscv/riscv-protos.h 2014-12-09 14:32:35.932301937 -0800
+@@ -0,0 +1,91 @@
++/* Definition of RISC-V target for GNU compiler.
++ Copyright (C) 2011-2014 Free Software Foundation, Inc.
++ Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
++ Based on MIPS target for GNU compiler.
++
++This file is part of GCC.
++
++GCC is free software; you can redistribute it and/or modify
++it under the terms of the GNU General Public License as published by
++the Free Software Foundation; either version 3, or (at your option)
++any later version.
++
++GCC is distributed in the hope that it will be useful,
++but WITHOUT ANY WARRANTY; without even the implied warranty of
++MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++GNU General Public License for more details.
++
++You should have received a copy of the GNU General Public License
++along with GCC; see the file COPYING3. If not see
++<http://www.gnu.org/licenses/>. */
++
++#ifndef GCC_RISCV_PROTOS_H
++#define GCC_RISCV_PROTOS_H
++
++enum mips_symbol_type {
++ SYMBOL_ABSOLUTE,
++ SYMBOL_GOT_DISP,
++ SYMBOL_TLS,
++ SYMBOL_TLS_LE,
++ SYMBOL_TLS_IE,
++ SYMBOL_TLS_GD
++};
++#define NUM_SYMBOL_TYPES (SYMBOL_TLS_GD + 1)
++
++extern bool mips_symbolic_constant_p (rtx, enum mips_symbol_type *);
++extern int riscv_regno_mode_ok_for_base_p (int, enum machine_mode, bool);
++extern int riscv_address_insns (rtx, enum machine_mode, bool);
++extern int riscv_const_insns (rtx);
++extern int riscv_split_const_insns (rtx);
++extern int mips_load_store_insns (rtx, rtx);
++extern rtx mips_emit_move (rtx, rtx);
++extern bool mips_split_symbol (rtx, rtx, enum machine_mode, rtx *);
++extern rtx mips_unspec_address (rtx, enum mips_symbol_type);
++extern void mips_move_integer (rtx, rtx, HOST_WIDE_INT);
++extern bool mips_legitimize_move (enum machine_mode, rtx, rtx);
++extern bool mips_legitimize_vector_move (enum machine_mode, rtx, rtx);
++
++extern rtx mips_subword (rtx, bool);
++extern bool mips_split_64bit_move_p (rtx, rtx);
++extern void mips_split_doubleword_move (rtx, rtx);
++extern const char *mips_output_move (rtx, rtx);
++extern const char *mips_riscv_output_vector_move (enum machine_mode, rtx, rtx);
++#ifdef RTX_CODE
++extern void riscv_expand_scc (rtx *);
++extern void riscv_expand_conditional_branch (rtx *);
++#endif
++extern rtx riscv_expand_call (bool, rtx, rtx, rtx);
++extern void riscv_expand_fcc_reload (rtx, rtx, rtx);
++extern void riscv_set_return_address (rtx, rtx);
++extern bool riscv_expand_block_move (rtx, rtx, rtx);
++extern void riscv_expand_synci_loop (rtx, rtx);
++
++extern bool riscv_expand_ext_as_unaligned_load (rtx, rtx, HOST_WIDE_INT,
++ HOST_WIDE_INT);
++extern bool riscv_expand_ins_as_unaligned_store (rtx, rtx, HOST_WIDE_INT,
++ HOST_WIDE_INT);
++extern void mips_order_regs_for_local_alloc (void);
++
++extern rtx riscv_return_addr (int, rtx);
++extern HOST_WIDE_INT riscv_initial_elimination_offset (int, int);
++extern void riscv_expand_prologue (void);
++extern void riscv_expand_epilogue (bool);
++extern bool mips_can_use_return_insn (void);
++extern rtx riscv_function_value (const_tree, const_tree, enum machine_mode);
++
++extern enum reg_class riscv_secondary_reload_class (enum reg_class,
++ enum machine_mode,
++ rtx, bool);
++extern int riscv_class_max_nregs (enum reg_class, enum machine_mode);
++
++extern unsigned int riscv_hard_regno_nregs (int, enum machine_mode);
++
++extern void irix_asm_output_align (FILE *, unsigned);
++extern const char *current_section_name (void);
++extern unsigned int current_section_flags (void);
++
++extern void riscv_expand_vector_init (rtx, rtx);
++
++extern bool riscv_size_ok_for_small_data_p (int size);
++
++#endif /* ! GCC_RISCV_PROTOS_H */
+diff -Nur original-gcc/gcc/config/riscv/sync.md gcc/gcc/config/riscv/sync.md
+--- original-gcc/gcc/config/riscv/sync.md 1969-12-31 16:00:00.000000000 -0800
++++ gcc/gcc/config/riscv/sync.md 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,197 @@
+;; Machine description for RISC-V atomic operations.
+;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
@@ -10701,34 +10609,83 @@ index 0000000..cdf22c6
+ gen_lowpart (SImode, shmt)));
+ DONE;
+})
-diff --git a/gcc/config/riscv/t-elf b/gcc/config/riscv/t-elf
-new file mode 100644
-index 0000000..00e60cc
---- /dev/null
-+++ b/gcc/config/riscv/t-elf
-@@ -0,0 +1,5 @@
+diff -Nur original-gcc/gcc/config/riscv/t-elf gcc/gcc/config/riscv/t-elf
+--- original-gcc/gcc/config/riscv/t-elf 1969-12-31 16:00:00.000000000 -0800
++++ gcc/gcc/config/riscv/t-elf 2014-12-09 14:38:12.796969166 -0800
+@@ -0,0 +1,4 @@
+# Build the libraries for both hard and soft floating point
+
-+MULTILIB_OPTIONS = msoft-float m64/m32 mfdiv mno-atomic
-+MULTILIB_DIRNAMES = soft-float 64 32 fdiv no-atomic
-+MULTILIB_EXCEPTIONS = *msoft-float*/*mfdiv*
-diff --git a/gcc/config/riscv/t-linux64 b/gcc/config/riscv/t-linux64
-new file mode 100644
-index 0000000..51c2b17
---- /dev/null
-+++ b/gcc/config/riscv/t-linux64
-@@ -0,0 +1,6 @@
++MULTILIB_OPTIONS = msoft-float m64/m32 mno-atomic
++MULTILIB_DIRNAMES = soft-float 64 32 no-atomic
+diff -Nur original-gcc/gcc/config/riscv/t-linux64 gcc/gcc/config/riscv/t-linux64
+--- original-gcc/gcc/config/riscv/t-linux64 1969-12-31 16:00:00.000000000 -0800
++++ gcc/gcc/config/riscv/t-linux64 2014-12-09 14:38:12.796969166 -0800
+@@ -0,0 +1,5 @@
+# Build the libraries for both hard and soft floating point
+
-+MULTILIB_OPTIONS = m64/m32 msoft-float mfdiv mno-atomic
-+MULTILIB_DIRNAMES = 64 32 soft-float fdiv no-atomic
-+MULTILIB_EXCEPTIONS = *msoft-float*/*mfdiv*
++MULTILIB_OPTIONS = m64/m32 msoft-float mno-atomic
++MULTILIB_DIRNAMES = 64 32 soft-float no-atomic
+MULTILIB_OSDIRNAMES = ../lib ../lib32
-diff --git a/gcc/configure b/gcc/configure
-index eae8fc8..e89f5b3 100755
---- a/gcc/configure
-+++ b/gcc/configure
-@@ -23506,6 +23506,25 @@ x3: .space 4
+diff -Nur original-gcc/gcc/config.gcc gcc/gcc/config.gcc
+--- original-gcc/gcc/config.gcc 2014-06-16 01:15:35.000000000 -0700
++++ gcc/gcc/config.gcc 2014-12-09 14:38:51.655180307 -0800
+@@ -1944,6 +1944,20 @@
+ cxx_target_objs="${cxx_target_objs} microblaze-c.o"
+ tmake_file="${tmake_file} microblaze/t-microblaze"
+ ;;
++riscv*-*-linux*) # Linux RISC-V
++ tm_file="elfos.h gnu-user.h linux.h glibc-stdint.h ${tm_file} riscv/linux.h riscv/linux64.h"
++ tmake_file="${tmake_file} riscv/t-linux64"
++ gnu_ld=yes
++ gas=yes
++ gcc_cv_initfini_array=yes
++ ;;
++riscv*-*-elf*) # Linux RISC-V
++ tm_file="elfos.h newlib-stdint.h ${tm_file} riscv/elf.h"
++ tmake_file="${tmake_file} riscv/t-elf"
++ gnu_ld=yes
++ gas=yes
++ gcc_cv_initfini_array=yes
++ ;;
+ mips*-*-netbsd*) # NetBSD/mips, either endian.
+ target_cpu_default="MASK_ABICALLS"
+ tm_file="elfos.h ${tm_file} mips/elf.h netbsd.h netbsd-elf.h mips/netbsd.h"
+@@ -3750,6 +3764,31 @@
+ done
+ ;;
+
++ riscv*-*-*)
++ supported_defaults="abi arch arch_32 arch_64 float tune tune_32 tune_64"
++
++ case ${with_float} in
++ "" | soft | hard)
++ # OK
++ ;;
++ *)
++ echo "Unknown floating point type used in --with-float=$with_float" 1>&2
++ exit 1
++ ;;
++ esac
++
++ case ${with_abi} in
++ "" | 32 | 64)
++ # OK
++ ;;
++ *)
++ echo "Unknown ABI used in --with-abi=$with_abi" 1>&2
++ exit 1
++ ;;
++ esac
++
++ ;;
++
+ mips*-*-*)
+ supported_defaults="abi arch arch_32 arch_64 float fpu nan tune tune_32 tune_64 divide llsc mips-plt synci"
+
+diff -Nur original-gcc/gcc/configure gcc/gcc/configure
+--- original-gcc/gcc/configure 2014-05-28 04:37:50.000000000 -0700
++++ gcc/gcc/configure 2014-12-09 14:38:51.655180307 -0800
+@@ -23506,6 +23506,25 @@
tls_first_minor=14
tls_as_opt="-a32 --fatal-warnings"
;;
@@ -10740,13 +10697,13 @@ index eae8fc8..e89f5b3 100755
+ .text
+ la.tls.gd a0,x
+ la.tls.ie a1,x
-+ lui v0,%tls_ie_hi(x)
-+ lw v0,%tls_ie_lo(x)(v0)
-+ add v0,v0,tp,%tls_ie_add(x)
-+ lw v0,%tls_ie_off(x)(v0)
-+ lui v0,%tprel_hi(x)
-+ add v0,v0,tp,%tprel_add(x)
-+ lw v0,%tprel_lo(x)(v0)'
++ lui a0,%tls_ie_pcrel_hi(x)
++ lw a0,%pcrel_lo(x)(a0)
++ add a0,a0,tp
++ lw a0,0(a0)
++ lui a0,%tprel_hi(x)
++ add a0,a0,tp,%tprel_add(x)
++ lw a0,%tprel_lo(x)(a0)'
+ tls_first_major=2
+ tls_first_minor=21
+ tls_as_opt='-m32 --fatal-warnings'
@@ -10754,11 +10711,10 @@ index eae8fc8..e89f5b3 100755
s390-*-*)
conftest_s='
.section ".tdata","awT",@progbits
-diff --git a/gcc/configure.ac b/gcc/configure.ac
-index 87c7d6b..0f074bc 100644
---- a/gcc/configure.ac
-+++ b/gcc/configure.ac
-@@ -3178,6 +3178,25 @@ x3: .space 4
+diff -Nur original-gcc/gcc/configure.ac gcc/gcc/configure.ac
+--- original-gcc/gcc/configure.ac 2014-05-28 04:37:50.000000000 -0700
++++ gcc/gcc/configure.ac 2014-12-09 14:38:51.655180307 -0800
+@@ -3178,6 +3178,25 @@
tls_first_minor=14
tls_as_opt="-a32 --fatal-warnings"
;;
@@ -10770,13 +10726,13 @@ index 87c7d6b..0f074bc 100644
+ .text
+ la.tls.gd a0,x
+ la.tls.ie a1,x
-+ lui v0,%tls_ie_hi(x)
-+ lw v0,%tls_ie_lo(x)(v0)
-+ add v0,v0,tp,%tls_ie_add(x)
-+ lw v0,%tls_ie_off(x)(v0)
-+ lui v0,%tprel_hi(x)
-+ add v0,v0,tp,%tprel_add(x)
-+ lw v0,%tprel_lo(x)(v0)'
++ lui a0,%tls_ie_pcrel_hi(x)
++ lw a0,%pcrel_lo(x)(a0)
++ add a0,a0,tp
++ lw a0,0(a0)
++ lui a0,%tprel_hi(x)
++ add a0,a0,tp,%tprel_add(x)
++ lw a0,%tprel_lo(x)(a0)'
+ tls_first_major=2
+ tls_first_minor=21
+ tls_as_opt='-m32 --fatal-warnings'
@@ -10784,10 +10740,9 @@ index 87c7d6b..0f074bc 100644
s390-*-*)
conftest_s='
.section ".tdata","awT",@progbits
-diff --git a/gcc/testsuite/gcc.c-torture/execute/20101011-1.c b/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
-index 1952dbd..7015082 100644
---- a/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
-+++ b/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
+diff -Nur original-gcc/gcc/testsuite/gcc.c-torture/execute/20101011-1.c gcc/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
+--- original-gcc/gcc/testsuite/gcc.c-torture/execute/20101011-1.c 2013-12-30 23:05:35.000000000 -0800
++++ gcc/gcc/testsuite/gcc.c-torture/execute/20101011-1.c 2014-12-09 14:38:51.655180307 -0800
@@ -6,6 +6,9 @@
#elif defined (__powerpc__) || defined (__PPC__) || defined (__ppc__) || defined (__POWERPC__) || defined (__ppc)
/* On PPC division by zero does not trap. */
@@ -10798,10 +10753,21 @@ index 1952dbd..7015082 100644
#elif defined (__SPU__)
/* On SPU division by zero does not trap. */
# define DO_TEST 0
-diff --git a/libatomic/configure.tgt b/libatomic/configure.tgt
-index a3757ef..516348d 100644
---- a/libatomic/configure.tgt
-+++ b/libatomic/configure.tgt
+diff -Nur original-gcc/libatomic/cas_n.c gcc/libatomic/cas_n.c
+--- original-gcc/libatomic/cas_n.c 2014-02-20 09:43:53.000000000 -0800
++++ gcc/libatomic/cas_n.c 2014-12-09 14:38:51.655180307 -0800
+@@ -70,7 +70,7 @@
+ mask = -1;
+ }
+
+- weval = *eptr << shift;
++ weval = (UWORD)*eptr << shift;
+ wnewval = (UWORD)newval << shift;
+ woldval = __atomic_load_n (wptr, __ATOMIC_RELAXED);
+ do
+diff -Nur original-gcc/libatomic/configure.tgt gcc/libatomic/configure.tgt
+--- original-gcc/libatomic/configure.tgt 2014-01-02 14:24:30.000000000 -0800
++++ gcc/libatomic/configure.tgt 2014-12-09 14:38:51.655180307 -0800
@@ -29,6 +29,7 @@
case "${target_cpu}" in
alpha*) ARCH=alpha ;;
@@ -10810,54 +10776,19 @@ index a3757ef..516348d 100644
sh*) ARCH=sh ;;
arm*)
-diff --git a/libgcc/config.host b/libgcc/config.host
-index f4a7428..2e14897 100644
---- a/libgcc/config.host
-+++ b/libgcc/config.host
-@@ -167,6 +167,9 @@ powerpc*-*-*)
- ;;
- rs6000*-*-*)
- ;;
-+riscv*)
-+ cpu_type=riscv
-+ ;;
- score*-*-*)
- cpu_type=score
- ;;
-@@ -1002,6 +1005,14 @@ powerpcle-*-eabi*)
- tmake_file="${tmake_file} rs6000/t-ppccomm rs6000/t-crtstuff t-crtstuff-pic t-fdpbit"
- extra_parts="$extra_parts crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o ecrti.o ecrtn.o ncrti.o ncrtn.o"
- ;;
-+riscv*-*-linux*)
-+ tmake_file="${tmake_file} riscv/t-fpbit riscv/t-dpbit riscv/t-tpbit riscv/t-linux"
-+ extra_parts="$extra_parts crtbegin.o crtend.o crti.o crtn.o crtendS.o crtbeginT.o"
-+ ;;
-+riscv*-*-*)
-+ tmake_file="${tmake_file} riscv/t-fpbit riscv/t-dpbit riscv/t-elf"
-+ extra_parts="$extra_parts crtbegin.o crtend.o crti.o crtn.o"
-+ ;;
- rs6000-ibm-aix4.[3456789]* | powerpc-ibm-aix4.[3456789]*)
- md_unwind_header=rs6000/aix-unwind.h
- tmake_file="t-fdpbit rs6000/t-ppc64-fp rs6000/t-slibgcc-aix rs6000/t-ibm-ldouble"
-diff --git a/libgcc/config/riscv/crti.S b/libgcc/config/riscv/crti.S
-new file mode 100644
-index 0000000..89bac70
---- /dev/null
-+++ b/libgcc/config/riscv/crti.S
+diff -Nur original-gcc/libgcc/config/riscv/crti.S gcc/libgcc/config/riscv/crti.S
+--- original-gcc/libgcc/config/riscv/crti.S 1969-12-31 16:00:00.000000000 -0800
++++ gcc/libgcc/config/riscv/crti.S 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1 @@
+/* crti.S is empty because .init_array/.fini_array are used exclusively. */
-diff --git a/libgcc/config/riscv/crtn.S b/libgcc/config/riscv/crtn.S
-new file mode 100644
-index 0000000..ca6ee7b
---- /dev/null
-+++ b/libgcc/config/riscv/crtn.S
+diff -Nur original-gcc/libgcc/config/riscv/crtn.S gcc/libgcc/config/riscv/crtn.S
+--- original-gcc/libgcc/config/riscv/crtn.S 1969-12-31 16:00:00.000000000 -0800
++++ gcc/libgcc/config/riscv/crtn.S 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1 @@
+/* crtn.S is empty because .init_array/.fini_array are used exclusively. */
-diff --git a/libgcc/config/riscv/riscv-fp.c b/libgcc/config/riscv/riscv-fp.c
-new file mode 100644
-index 0000000..6d7a1f1
---- /dev/null
-+++ b/libgcc/config/riscv/riscv-fp.c
+diff -Nur original-gcc/libgcc/config/riscv/riscv-fp.c gcc/libgcc/config/riscv/riscv-fp.c
+--- original-gcc/libgcc/config/riscv/riscv-fp.c 1969-12-31 16:00:00.000000000 -0800
++++ gcc/libgcc/config/riscv/riscv-fp.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,178 @@
+/* Functions needed for soft-float on riscv-linux. Based on
+ rs6000/ppc64-fp.c with TF types removed.
@@ -11037,47 +10968,37 @@ index 0000000..6d7a1f1
+}
+
+#endif
-diff --git a/libgcc/config/riscv/t-dpbit b/libgcc/config/riscv/t-dpbit
-new file mode 100644
-index 0000000..b2f2c17
---- /dev/null
-+++ b/libgcc/config/riscv/t-dpbit
+diff -Nur original-gcc/libgcc/config/riscv/t-dpbit gcc/libgcc/config/riscv/t-dpbit
+--- original-gcc/libgcc/config/riscv/t-dpbit 1969-12-31 16:00:00.000000000 -0800
++++ gcc/libgcc/config/riscv/t-dpbit 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,4 @@
+LIB2ADD += dp-bit.c
+
+dp-bit.c: $(srcdir)/fp-bit.c
+ cat $(srcdir)/fp-bit.c > dp-bit.c
-diff --git a/libgcc/config/riscv/t-elf b/libgcc/config/riscv/t-elf
-new file mode 100644
-index 0000000..6e93f06
---- /dev/null
-+++ b/libgcc/config/riscv/t-elf
+diff -Nur original-gcc/libgcc/config/riscv/t-elf gcc/libgcc/config/riscv/t-elf
+--- original-gcc/libgcc/config/riscv/t-elf 1969-12-31 16:00:00.000000000 -0800
++++ gcc/libgcc/config/riscv/t-elf 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,2 @@
+# Assemble startup files.
+LIB2ADD += $(srcdir)/config/riscv/riscv-fp.c
-diff --git a/libgcc/config/riscv/t-fpbit b/libgcc/config/riscv/t-fpbit
-new file mode 100644
-index 0000000..772add5
---- /dev/null
-+++ b/libgcc/config/riscv/t-fpbit
+diff -Nur original-gcc/libgcc/config/riscv/t-fpbit gcc/libgcc/config/riscv/t-fpbit
+--- original-gcc/libgcc/config/riscv/t-fpbit 1969-12-31 16:00:00.000000000 -0800
++++ gcc/libgcc/config/riscv/t-fpbit 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,5 @@
+LIB2ADD += fp-bit.c
+
+fp-bit.c: $(srcdir)/fp-bit.c
+ echo '#define FLOAT' > fp-bit.c
+ cat $(srcdir)/fp-bit.c >> fp-bit.c
-diff --git a/libgcc/config/riscv/t-linux b/libgcc/config/riscv/t-linux
-new file mode 100644
-index 0000000..6f1b70d
---- /dev/null
-+++ b/libgcc/config/riscv/t-linux
+diff -Nur original-gcc/libgcc/config/riscv/t-linux gcc/libgcc/config/riscv/t-linux
+--- original-gcc/libgcc/config/riscv/t-linux 1969-12-31 16:00:00.000000000 -0800
++++ gcc/libgcc/config/riscv/t-linux 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1 @@
+LIB2ADD += $(srcdir)/config/riscv/riscv-fp.c
-diff --git a/libgcc/config/riscv/t-tpbit b/libgcc/config/riscv/t-tpbit
-new file mode 100644
-index 0000000..d5df179
---- /dev/null
-+++ b/libgcc/config/riscv/t-tpbit
+diff -Nur original-gcc/libgcc/config/riscv/t-tpbit gcc/libgcc/config/riscv/t-tpbit
+--- original-gcc/libgcc/config/riscv/t-tpbit 1969-12-31 16:00:00.000000000 -0800
++++ gcc/libgcc/config/riscv/t-tpbit 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,10 @@
+LIB2ADD += tp-bit.c
+
@@ -11089,3 +11010,21 @@ index 0000000..d5df179
+ echo '# define TFLOAT' >> tp-bit.c
+ cat $(srcdir)/fp-bit.c >> tp-bit.c
+ echo '#endif' >> tp-bit.c
+diff -Nur original-gcc/libgcc/config.host gcc/libgcc/config.host
+--- original-gcc/libgcc/config.host 2014-03-27 08:40:31.000000000 -0700
++++ gcc/libgcc/config.host 2014-12-09 14:38:51.655180307 -0800
+@@ -1002,6 +1002,14 @@
+ tmake_file="${tmake_file} rs6000/t-ppccomm rs6000/t-crtstuff t-crtstuff-pic t-fdpbit"
+ extra_parts="$extra_parts crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o ecrti.o ecrtn.o ncrti.o ncrtn.o"
+ ;;
++riscv*-*-linux*)
++ tmake_file="${tmake_file} riscv/t-fpbit riscv/t-dpbit riscv/t-tpbit riscv/t-linux"
++ extra_parts="$extra_parts crtbegin.o crtend.o crti.o crtn.o crtendS.o crtbeginT.o"
++ ;;
++riscv*-*-*)
++ tmake_file="${tmake_file} riscv/t-fpbit riscv/t-dpbit riscv/t-elf"
++ extra_parts="$extra_parts crtbegin.o crtend.o crti.o crtn.o"
++ ;;
+ rs6000-ibm-aix4.[3456789]* | powerpc-ibm-aix4.[3456789]*)
+ md_unwind_header=rs6000/aix-unwind.h
+ tmake_file="t-fdpbit rs6000/t-ppc64-fp rs6000/t-slibgcc-aix rs6000/t-ibm-ldouble"
diff --git a/sys-libs/glibc/Manifest b/sys-libs/glibc/Manifest
index edd9633..eb1860b 100644
--- a/sys-libs/glibc/Manifest
+++ b/sys-libs/glibc/Manifest
@@ -10,7 +10,7 @@ AUX eblits/src_install.eblit 7995 SHA256 b4ffcc37e9123c80013c2f8e3a9851fea8fdcdf
AUX eblits/src_prepare.eblit 2391 SHA256 460774d6b76214005ec4fb4fe9ce9dbf2f5a466bf3123e89d86ec29827a261d8 SHA512 ec147469aa6dc1e843291d68d3dda75946381ea17b7bc7daec09ac6dc5a6d4508ac1737ed53b0fb24d745afdda3356afac6cda1adac5a4971be385e390c037c6 WHIRLPOOL 9ecac39a3fafe07482fb6c8d9883cadbaff1117ba0c627b5e8f5a99ee26d0ffbeaaa27ac0cb5c9a440cce89f696bac489cd3831e43260e1c0eb1c70425db4213
AUX eblits/src_test.eblit 790 SHA256 48b0f5ef0e91258148355f4d2d6be01a5d6c6704cc0cfbe956aa58e1b9171edc SHA512 8435ab9bbf64457be596e58a7fed5775f7b9062eccf36d39c894aa45b96f0aff5d46c58fc53f7bdf9fe828238ade69d49a3fa7e7cc027b0fa0f1e126b33e6779 WHIRLPOOL 030dd714da4a1ea08b743b32c668d38531deff4bf1cb0e5751a8cf32b329e1df50299cb789f59f9d4f06805051800e761ea0ef5add72005e3e8d47452b3f1201
AUX eblits/src_unpack.eblit 3209 SHA256 82b23ecfe2fc3b7e93545af4b67e2525e1ee3c9f2d4eac3af435cf44e8254da4 SHA512 4f9cb34be2869864c0f814141bf1b6504b4138c3c672dd1fef9c5ad448c6fabab98445551cb364035978898c9e7829168ef702b068b4dadf325cf925c70ab42f WHIRLPOOL bdcf238477e6148dcdb8371eee40cb8ee920e039848e1088923922e615529fea70089fb5f1094630269d3a876c4752f41d0433b2948f5b5283a532938c9858df
-AUX glibc-2.20-riscv.patch 245891 SHA256 7efc6f165abbb4606809478df67fef8640c4d4b23ac401f2a95cd0ee9d27d827 SHA512 abf6c9aa3c0c812d4ce16e4517f896113e482b81f436b0f645f4ac304d4695be5f249daa9183c37c7b8a744164deba2b0937a9bc73be38be6df486bf8843020e WHIRLPOOL 714f7de7fc4fd3d57d91bd17d16f1a1a170dc11e412df33bb9bae6f1960eac9888d8f400e6dce889bc6e7cd751ab9728f48231cabcd76c51cd92c18a63815eed
+AUX glibc-2.20-riscv.patch 255379 SHA256 a8b0ad6da0e4d5e77a54836682fcb5a1ca06abd977005ea9f76f6a2ffb5eef9d SHA512 f93e56d6d3e13dd396a07a7f4fbe804e61e9ffb90236bd467b5f575f13c7d09030ee5bfbd1f68f4c37a87d66602d8002ddfdaa22abe178061468ff0863348229 WHIRLPOOL e8aae7f473b8749b0479f24ad4a43379ae9e71743b9c9401531c2a6d4aea491ea0e697ac12ddca50a41e149eb6eb095ccc5dd1e1f615d6873a120bdaac9de984
AUX nscd 1621 SHA256 6165db3a2fcb251d4f3655c0461e018ce9c92a37f7f22a8fd2b75178b5435bc8 SHA512 3e1255ab014b3806112120000c3d2189a7c1c69dcd6639d5ce55e96bec721683a22b141982f6a6c6d44b14481c33fbbaa470863bef04e9b9eab7ccad1ddd5d95 WHIRLPOOL b7152f8d888fca13a16ea403c44eadbf1da2249dae3add11f73999259061824460a5479aa7e58c012bd737b62ecc81814109832cee33638279d90d4c08bfdbdc
AUX nscd.service 337 SHA256 de7bc9946309d34f0ab44aa22a4d3cf259fe91c57e8000d741cb09ecd3a6caa0 SHA512 2001100f3b054843c69b6fd2d38852c7c824282aa8998c25a3c0352db993705429d25c70d8ce6cb3579f836b7089644c520acac423ebd69cb1b36e94a77c5bea WHIRLPOOL f01d191971b0dc45f541c9ebaaa1a40f3497e2cc838cff6a20a7b1828d726c248abbd94322a5a5ff30c33ddb7d9086cd4d2ba3bdc1811fed59ff292ef3983a72
AUX nscd.tmpfilesd 111 SHA256 f0f64c4612d2097173854d2ec2e94ecbf4b77c7a6e94d950874e37346aa90d72 SHA512 53b80b331e1a85d8ee16eb2ce547a7249e944926c3d1cdd4a47a5301a5c842ffc7ec1e3dc0a731542a8facf8261c1c57121802d01741aa89898a3476c09da340 WHIRLPOOL cf1fed1a7e2ac1623a84f1cfa2062645afe3f791da2f4ace3859d12aa05df0e282b4c2e367a460015956ac2a8d01fee4cda84917a3adf2c38561dff200335270
diff --git a/sys-libs/glibc/files/glibc-2.20-riscv.patch b/sys-libs/glibc/files/glibc-2.20-riscv.patch
index 19edc52..fbe2a17 100644
--- a/sys-libs/glibc/files/glibc-2.20-riscv.patch
+++ b/sys-libs/glibc/files/glibc-2.20-riscv.patch
@@ -1,8 +1,7 @@
-diff --git a/scripts/config.sub b/scripts/config.sub
-index d654d03..5d14ffc 100755
---- a/scripts/config.sub
-+++ b/scripts/config.sub
-@@ -302,6 +302,7 @@ case $basic_machine in
+diff -Nur original-glibc/scripts/config.sub glibc/scripts/config.sub
+--- original-glibc/scripts/config.sub 2014-09-07 01:09:09.000000000 -0700
++++ glibc/scripts/config.sub 2014-12-09 14:40:30.020634841 -0800
+@@ -302,6 +302,7 @@
| pdp10 | pdp11 | pj | pjl \
| powerpc | powerpc64 | powerpc64le | powerpcle \
| pyramid \
@@ -10,11 +9,10 @@ index d654d03..5d14ffc 100755
| rl78 | rx \
| score \
| sh | sh[1234] | sh[24]a | sh[24]aeb | sh[23]e | sh[34]eb | sheb | shbe | shle | sh[1234]le | sh3ele \
-diff --git a/shlib-versions b/shlib-versions
-index 40469bd..2077b26 100644
---- a/shlib-versions
-+++ b/shlib-versions
-@@ -25,6 +25,7 @@ s390x-.*-linux.* DEFAULT GLIBC_2.2
+diff -Nur original-glibc/shlib-versions glibc/shlib-versions
+--- original-glibc/shlib-versions 2014-09-07 01:09:09.000000000 -0700
++++ glibc/shlib-versions 2014-12-09 14:40:30.020634841 -0800
+@@ -25,6 +25,7 @@
powerpc64-.*-linux.* DEFAULT GLIBC_2.3
powerpc.*le-.*-linux.* DEFAULT GLIBC_2.17
.*-.*-gnu-gnu.* DEFAULT GLIBC_2.2.6
@@ -22,163 +20,9 @@ index 40469bd..2077b26 100644
# Configuration Library=version Earliest symbol set (optional)
# ------------- --------------- ------------------------------
-diff --git a/sysdeps/riscv/Implies b/sysdeps/riscv/Implies
-new file mode 100644
-index 0000000..b1da7b4
---- /dev/null
-+++ b/sysdeps/riscv/Implies
-@@ -0,0 +1,7 @@
-+init_array
-+
-+ieee754/flt-32
-+ieee754/dbl-64
-+
-+# This needs to change to support rv32
-+riscv/rv64
-diff --git a/sysdeps/riscv/Makefile b/sysdeps/riscv/Makefile
-new file mode 100644
-index 0000000..cd9598a
---- /dev/null
-+++ b/sysdeps/riscv/Makefile
-@@ -0,0 +1,49 @@
-+ifneq ($(all-rtld-routines),)
-+CFLAGS-rtld.c += -mno-plt
-+CFLAGS-dl-load.c += -mno-plt
-+CFLAGS-dl-cache.c += -mno-plt
-+CFLAGS-dl-lookup.c += -mno-plt
-+CFLAGS-dl-object.c += -mno-plt
-+CFLAGS-dl-reloc.c += -mno-plt
-+CFLAGS-dl-deps.c += -mno-plt
-+CFLAGS-dl-runtime.c += -mno-plt
-+CFLAGS-dl-error.c += -mno-plt
-+CFLAGS-dl-init.c += -mno-plt
-+CFLAGS-dl-fini.c += -mno-plt
-+CFLAGS-dl-debug.c += -mno-plt
-+CFLAGS-dl-misc.c += -mno-plt
-+CFLAGS-dl-version.c += -mno-plt
-+CFLAGS-dl-profile.c += -mno-plt
-+CFLAGS-dl-conflict.c += -mno-plt
-+CFLAGS-dl-tls.c += -mno-plt
-+CFLAGS-dl-origin.c += -mno-plt
-+CFLAGS-dl-scope.c += -mno-plt
-+CFLAGS-dl-execstack.c += -mno-plt
-+CFLAGS-dl-caller.c += -mno-plt
-+CFLAGS-dl-open.c += -mno-plt
-+CFLAGS-dl-close.c += -mno-plt
-+CFLAGS-dl-sysdep.c += -mno-plt
-+CFLAGS-dl-environ.c += -mno-plt
-+CFLAGS-dl-minimal.c += -mno-plt
-+CFLAGS-dl-static.c += -mno-plt
-+CFLAGS-dl-brk.c += -mno-plt
-+CFLAGS-dl-sbrk.c += -mno-plt
-+CFLAGS-dl-getcwd.c += -mno-plt
-+CFLAGS-dl-openat64.c += -mno-plt
-+CFLAGS-dl-opendir.c += -mno-plt
-+CFLAGS-dl-fxstatat64.c += -mno-plt
-+endif
-+
-+CFLAGS-closedir.c += -mno-plt
-+CFLAGS-exit.c += -mno-plt
-+CFLAGS-cxa_atexit.c += -mno-plt
-+
-+ifeq ($(subdir),misc)
-+sysdep_headers += sys/asm.h sgidefs.h
-+endif
-+
-+ifeq ($(subdir),rt)
-+librt-sysdep_routines += rt-sysdep
-+endif
-+
-+ASFLAGS-.os += $(pic-ccflag)
-diff --git a/sysdeps/riscv/Versions b/sysdeps/riscv/Versions
-new file mode 100644
-index 0000000..5a0c2d2
---- /dev/null
-+++ b/sysdeps/riscv/Versions
-@@ -0,0 +1,5 @@
-+libc {
-+ GLIBC_2.14 {
-+ __memcpy_g;
-+ }
-+}
-diff --git a/sysdeps/riscv/__longjmp.S b/sysdeps/riscv/__longjmp.S
-new file mode 100644
-index 0000000..88f720e
---- /dev/null
-+++ b/sysdeps/riscv/__longjmp.S
-@@ -0,0 +1,67 @@
-+/* Copyright (C) 1996, 1997, 2000, 2002, 2003, 2004
-+ Free Software Foundation, Inc.
-+ This file is part of the GNU C Library.
-+
-+ The GNU C Library is free software; you can redistribute it and/or
-+ modify it under the terms of the GNU Lesser General Public
-+ License as published by the Free Software Foundation; either
-+ version 2.1 of the License, or (at your option) any later version.
-+
-+ The GNU C Library is distributed in the hope that it will be useful,
-+ but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ Lesser General Public License for more details.
-+
-+ You should have received a copy of the GNU Lesser General Public
-+ License along with the GNU C Library; if not, write to the Free
-+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
-+ 02111-1307 USA. */
-+
-+#include <sysdep.h>
-+#include <sys/asm.h>
-+
-+ENTRY (__longjmp)
-+ REG_L ra, 0*SZREG(a0)
-+ REG_L s0, 1*SZREG(a0)
-+ REG_L s1, 2*SZREG(a0)
-+ REG_L s2, 3*SZREG(a0)
-+ REG_L s3, 4*SZREG(a0)
-+ REG_L s4, 5*SZREG(a0)
-+ REG_L s5, 6*SZREG(a0)
-+ REG_L s6, 7*SZREG(a0)
-+ REG_L s7, 8*SZREG(a0)
-+ REG_L s8, 9*SZREG(a0)
-+ REG_L s9, 10*SZREG(a0)
-+ REG_L s10,11*SZREG(a0)
-+ REG_L s11,12*SZREG(a0)
-+ REG_L sp, 13*SZREG(a0)
-+ REG_L tp, 14*SZREG(a0)
-+
-+#ifdef __riscv_hard_float
-+ REG_L a3, 15*SZREG(a0)
-+
-+ fld fs0, 16*SZREG+ 0*8(a0)
-+ fld fs1, 16*SZREG+ 1*8(a0)
-+ fld fs2, 16*SZREG+ 2*8(a0)
-+ fld fs3, 16*SZREG+ 3*8(a0)
-+ fld fs4, 16*SZREG+ 4*8(a0)
-+ fld fs5, 16*SZREG+ 5*8(a0)
-+ fld fs6, 16*SZREG+ 6*8(a0)
-+ fld fs7, 16*SZREG+ 7*8(a0)
-+ fld fs8, 16*SZREG+ 8*8(a0)
-+ fld fs9, 16*SZREG+ 9*8(a0)
-+ fld fs10,16*SZREG+10*8(a0)
-+ fld fs11,16*SZREG+11*8(a0)
-+ fld fs12,16*SZREG+12*8(a0)
-+ fld fs13,16*SZREG+13*8(a0)
-+ fld fs14,16*SZREG+14*8(a0)
-+ fld fs15,16*SZREG+15*8(a0)
-+
-+ fssr a3
-+#endif
-+
-+ sltu a3, a1, 1 # a3 = (a1 == 0)
-+ add v0, a3, a1 # v0 = (a1 == 0 ? 1 : a1)
-+ ret
-+
-+END(__longjmp)
-diff --git a/sysdeps/riscv/bits/atomic.h b/sysdeps/riscv/bits/atomic.h
-new file mode 100644
-index 0000000..aaa62d7
---- /dev/null
-+++ b/sysdeps/riscv/bits/atomic.h
+diff -Nur original-glibc/sysdeps/riscv/bits/atomic.h glibc/sysdeps/riscv/bits/atomic.h
+--- original-glibc/sysdeps/riscv/bits/atomic.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/bits/atomic.h 2014-12-09 14:32:35.932301937 -0800
@@ -0,0 +1,151 @@
+/* Low-level functions for atomic operations. Mips version.
+ Copyright (C) 2005 Free Software Foundation, Inc.
@@ -331,11 +175,9 @@ index 0000000..aaa62d7
+#endif /* __riscv_atomic */
+
+#endif /* bits/atomic.h */
-diff --git a/sysdeps/riscv/bits/dlfcn.h b/sysdeps/riscv/bits/dlfcn.h
-new file mode 100644
-index 0000000..a5b5bf5
---- /dev/null
-+++ b/sysdeps/riscv/bits/dlfcn.h
+diff -Nur original-glibc/sysdeps/riscv/bits/dlfcn.h glibc/sysdeps/riscv/bits/dlfcn.h
+--- original-glibc/sysdeps/riscv/bits/dlfcn.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/bits/dlfcn.h 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,66 @@
+/* System dependent definitions for run-time dynamic loading.
+ Copyright (C) 1996, 1997, 1999, 2000, 2001, 2004
@@ -403,22 +245,18 @@ index 0000000..a5b5bf5
+__END_DECLS
+
+#endif
-diff --git a/sysdeps/riscv/bits/endian.h b/sysdeps/riscv/bits/endian.h
-new file mode 100644
-index 0000000..4aaf559
---- /dev/null
-+++ b/sysdeps/riscv/bits/endian.h
+diff -Nur original-glibc/sysdeps/riscv/bits/endian.h glibc/sysdeps/riscv/bits/endian.h
+--- original-glibc/sysdeps/riscv/bits/endian.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/bits/endian.h 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,5 @@
+#ifndef _ENDIAN_H
+# error "Never use <bits/endian.h> directly; include <endian.h> instead."
+#endif
+
+#define __BYTE_ORDER __LITTLE_ENDIAN
-diff --git a/sysdeps/riscv/bits/fenv.h b/sysdeps/riscv/bits/fenv.h
-new file mode 100644
-index 0000000..0ccf5cb
---- /dev/null
-+++ b/sysdeps/riscv/bits/fenv.h
+diff -Nur original-glibc/sysdeps/riscv/bits/fenv.h glibc/sysdeps/riscv/bits/fenv.h
+--- original-glibc/sysdeps/riscv/bits/fenv.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/bits/fenv.h 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,57 @@
+/* Copyright (C) 1998, 1999, 2000 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
@@ -477,11 +315,9 @@ index 0000000..0ccf5cb
+
+/* If the default argument is used we use this value. */
+#define FE_DFL_ENV ((__const fenv_t *) -1)
-diff --git a/sysdeps/riscv/bits/ipctypes.h b/sysdeps/riscv/bits/ipctypes.h
-new file mode 100644
-index 0000000..0956e7d
---- /dev/null
-+++ b/sysdeps/riscv/bits/ipctypes.h
+diff -Nur original-glibc/sysdeps/riscv/bits/ipctypes.h glibc/sysdeps/riscv/bits/ipctypes.h
+--- original-glibc/sysdeps/riscv/bits/ipctypes.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/bits/ipctypes.h 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,32 @@
+/* bits/ipctypes.h -- Define some types used by SysV IPC/MSG/SHM. MIPS version
+ Copyright (C) 2002 Free Software Foundation, Inc.
@@ -515,11 +351,9 @@ index 0000000..0956e7d
+
+
+#endif /* bits/ipctypes.h */
-diff --git a/sysdeps/riscv/bits/link.h b/sysdeps/riscv/bits/link.h
-new file mode 100644
-index 0000000..f216ebd
---- /dev/null
-+++ b/sysdeps/riscv/bits/link.h
+diff -Nur original-glibc/sysdeps/riscv/bits/link.h glibc/sysdeps/riscv/bits/link.h
+--- original-glibc/sysdeps/riscv/bits/link.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/bits/link.h 2014-12-09 14:32:35.932301937 -0800
@@ -0,0 +1,76 @@
+/* Copyright (C) 2005, 2009 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
@@ -597,21 +431,17 @@ index 0000000..f216ebd
+#endif
+
+__END_DECLS
-diff --git a/sysdeps/riscv/bits/linkmap.h b/sysdeps/riscv/bits/linkmap.h
-new file mode 100644
-index 0000000..a6df782
---- /dev/null
-+++ b/sysdeps/riscv/bits/linkmap.h
+diff -Nur original-glibc/sysdeps/riscv/bits/linkmap.h glibc/sysdeps/riscv/bits/linkmap.h
+--- original-glibc/sysdeps/riscv/bits/linkmap.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/bits/linkmap.h 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,4 @@
+struct link_map_machine
+ {
+ ElfW(Addr) plt; /* Address of .plt */
+ };
-diff --git a/sysdeps/riscv/bits/mathdef.h b/sysdeps/riscv/bits/mathdef.h
-new file mode 100644
-index 0000000..1fef80f
---- /dev/null
-+++ b/sysdeps/riscv/bits/mathdef.h
+diff -Nur original-glibc/sysdeps/riscv/bits/mathdef.h glibc/sysdeps/riscv/bits/mathdef.h
+--- original-glibc/sysdeps/riscv/bits/mathdef.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/bits/mathdef.h 2014-12-09 14:32:35.932301937 -0800
@@ -0,0 +1,45 @@
+/* Copyright (C) 1997, 1998, 1999, 2000, 2002, 2003, 2004, 2007
+ Free Software Foundation, Inc.
@@ -658,11 +488,9 @@ index 0000000..1fef80f
+ declaration of all the `long double' function variants. */
+# define __NO_LONG_DOUBLE_MATH 1
+#endif
-diff --git a/sysdeps/riscv/bits/nan.h b/sysdeps/riscv/bits/nan.h
-new file mode 100644
-index 0000000..baaaa55
---- /dev/null
-+++ b/sysdeps/riscv/bits/nan.h
+diff -Nur original-glibc/sysdeps/riscv/bits/nan.h glibc/sysdeps/riscv/bits/nan.h
+--- original-glibc/sysdeps/riscv/bits/nan.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/bits/nan.h 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,56 @@
+/* `NAN' constant for IEEE 754 machines.
+ Copyright (C) 1992, 1996, 1997, 1999, 2002, 2004
@@ -720,11 +548,9 @@ index 0000000..baaaa55
+# define NAN (__nan_union.__d)
+
+#endif /* GCC. */
-diff --git a/sysdeps/riscv/bits/setjmp.h b/sysdeps/riscv/bits/setjmp.h
-new file mode 100644
-index 0000000..52e2d3d
---- /dev/null
-+++ b/sysdeps/riscv/bits/setjmp.h
+diff -Nur original-glibc/sysdeps/riscv/bits/setjmp.h glibc/sysdeps/riscv/bits/setjmp.h
+--- original-glibc/sysdeps/riscv/bits/setjmp.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/bits/setjmp.h 2014-12-09 14:38:38.665778707 -0800
@@ -0,0 +1,43 @@
+/* Define the machine-dependent type `jmp_buf'. RISC-V version.
+ Copyright (C) 1992,1993,1995,1997,2000,2002,2003,2004,2005,2006
@@ -765,15 +591,13 @@ index 0000000..52e2d3d
+ /* Callee-saved floating point registers.
+ Note that there are an even number of preceding words in this struct,
+ so no padding will be inserted before __fpregs, even for RV32. */
-+ double __fpregs[16];
++ double __fpregs[12];
+ } __jmp_buf[1];
+
+#endif /* _RISCV_BITS_SETJMP_H */
-diff --git a/sysdeps/riscv/bits/string.h b/sysdeps/riscv/bits/string.h
-new file mode 100644
-index 0000000..9d30fa6
---- /dev/null
-+++ b/sysdeps/riscv/bits/string.h
+diff -Nur original-glibc/sysdeps/riscv/bits/string.h glibc/sysdeps/riscv/bits/string.h
+--- original-glibc/sysdeps/riscv/bits/string.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/bits/string.h 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,25 @@
+/* This file should provide inline versions of string functions.
+
@@ -800,25 +624,45 @@ index 0000000..9d30fa6
+#endif /* __GNUC__ && !__cplusplus */
+
+#endif /* bits/string.h */
-diff --git a/sysdeps/riscv/bsd-_setjmp.c b/sysdeps/riscv/bsd-_setjmp.c
-new file mode 100644
-index 0000000..0d41310
---- /dev/null
-+++ b/sysdeps/riscv/bsd-_setjmp.c
+diff -Nur original-glibc/sysdeps/riscv/bits/wordsize.h glibc/sysdeps/riscv/bits/wordsize.h
+--- original-glibc/sysdeps/riscv/bits/wordsize.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/bits/wordsize.h 2014-12-09 14:32:35.932301937 -0800
+@@ -0,0 +1,22 @@
++/* Copyright (C) 2002, 2003 Free Software Foundation, Inc.
++ This file is part of the GNU C Library.
++
++ The GNU C Library is free software; you can redistribute it and/or
++ modify it under the terms of the GNU Lesser General Public
++ License as published by the Free Software Foundation; either
++ version 2.1 of the License, or (at your option) any later version.
++
++ The GNU C Library is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ Lesser General Public License for more details.
++
++ You should have received a copy of the GNU Lesser General Public
++ License along with the GNU C Library; if not, write to the Free
++ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
++ 02111-1307 USA. */
++
++#define __WORDSIZE _RISCV_SZPTR
++#if _RISCV_SIM == _ABI64
++# define __WORDSIZE_COMPAT32 1
++#endif
+diff -Nur original-glibc/sysdeps/riscv/bsd-_setjmp.c glibc/sysdeps/riscv/bsd-_setjmp.c
+--- original-glibc/sysdeps/riscv/bsd-_setjmp.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/bsd-_setjmp.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1 @@
+/* _setjmp is implemented in setjmp.S */
-diff --git a/sysdeps/riscv/bsd-setjmp.c b/sysdeps/riscv/bsd-setjmp.c
-new file mode 100644
-index 0000000..ee7c5e3
---- /dev/null
-+++ b/sysdeps/riscv/bsd-setjmp.c
+diff -Nur original-glibc/sysdeps/riscv/bsd-setjmp.c glibc/sysdeps/riscv/bsd-setjmp.c
+--- original-glibc/sysdeps/riscv/bsd-setjmp.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/bsd-setjmp.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1 @@
+/* setjmp is implemented in setjmp.S */
-diff --git a/sysdeps/riscv/configure b/sysdeps/riscv/configure
-new file mode 100644
-index 0000000..7280dbb
---- /dev/null
-+++ b/sysdeps/riscv/configure
+diff -Nur original-glibc/sysdeps/riscv/configure glibc/sysdeps/riscv/configure
+--- original-glibc/sysdeps/riscv/configure 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/configure 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,87 @@
+
+# as_fn_set_status STATUS
@@ -907,21 +751,17 @@ index 0000000..7280dbb
+
+$as_echo "#define PI_STATIC_AND_HIDDEN 1" >>confdefs.h
+
-diff --git a/sysdeps/riscv/configure.in b/sysdeps/riscv/configure.in
-new file mode 100644
-index 0000000..34f62d4
---- /dev/null
-+++ b/sysdeps/riscv/configure.in
+diff -Nur original-glibc/sysdeps/riscv/configure.in glibc/sysdeps/riscv/configure.in
+--- original-glibc/sysdeps/riscv/configure.in 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/configure.in 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,4 @@
+GLIBC_PROVIDES dnl See aclocal.m4 in the top level source directory.
+# Local configure fragment for sysdeps/riscv/elf.
+
+AC_DEFINE(PI_STATIC_AND_HIDDEN)
-diff --git a/sysdeps/riscv/dl-machine.h b/sysdeps/riscv/dl-machine.h
-new file mode 100644
-index 0000000..d92c3ac
---- /dev/null
-+++ b/sysdeps/riscv/dl-machine.h
+diff -Nur original-glibc/sysdeps/riscv/dl-machine.h glibc/sysdeps/riscv/dl-machine.h
+--- original-glibc/sysdeps/riscv/dl-machine.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/dl-machine.h 2014-12-09 14:38:38.665778707 -0800
@@ -0,0 +1,335 @@
+/* Machine-dependent ELF dynamic relocation inline functions. MIPS version.
+ Copyright (C) 1996-2001, 2002, 2003, 2004, 2005, 2006, 2007
@@ -1045,17 +885,17 @@ index 0000000..d92c3ac
+ move a0, sp\n\
+ jal _dl_start\n\
+ # Stash user entry point in s0.\n\
-+ move s0, v0\n\
++ move s0, a0\n\
+ # See if we were run as a command with the executable file\n\
+ # name as an extra leading argument.\n\
-+ lw v0, _dl_skip_args\n\
++ lw a0, _dl_skip_args\n\
+ # Load the original argument count.\n\
+ " STRINGXP(REG_L) " a1, 0(sp)\n\
+ # Subtract _dl_skip_args from it.\n\
-+ sub a1, a1, v0\n\
++ sub a1, a1, a0\n\
+ # Adjust the stack pointer to skip _dl_skip_args words.\n\
-+ sll v0, v0, " STRINGXP (PTRLOG) "\n\
-+ add sp, sp, v0\n\
++ sll a0, a0, " STRINGXP (PTRLOG) "\n\
++ add sp, sp, a0\n\
+ # Save back the modified argument count.\n\
+ " STRINGXP(REG_S) " a1, 0(sp)\n\
+ # Call _dl_init (struct link_map *main_map, int argc, char **argv, char **env) \n\
@@ -1066,8 +906,8 @@ index 0000000..d92c3ac
+ add a3, a3, " STRINGXP (SZREG) "\n\
+ # Call the function to run the initializers.\n\
+ jal _dl_init_internal\n\
-+ # Pass our finalizer function to the user in v0 as per ELF ABI.\n\
-+ lla v0, _dl_fini\n\
++ # Pass our finalizer function to _start.\n\
++ lla a0, _dl_fini\n\
+ # Jump to the user entry point.\n\
+ jr s0\n\
+ " _RTLD_EPILOGUE(ENTRY_POINT) "\
@@ -1258,11 +1098,9 @@ index 0000000..d92c3ac
+}
+
+#endif /* RESOLVE_MAP */
-diff --git a/sysdeps/riscv/dl-tls.h b/sysdeps/riscv/dl-tls.h
-new file mode 100644
-index 0000000..da2b444
---- /dev/null
-+++ b/sysdeps/riscv/dl-tls.h
+diff -Nur original-glibc/sysdeps/riscv/dl-tls.h glibc/sysdeps/riscv/dl-tls.h
+--- original-glibc/sysdeps/riscv/dl-tls.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/dl-tls.h 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,49 @@
+/* Thread-local storage handling in the ELF dynamic linker. MIPS version.
+ Copyright (C) 2005 Free Software Foundation, Inc.
@@ -1313,12 +1151,10 @@ index 0000000..da2b444
+
+/* Value used for dtv entries for which the allocation is delayed. */
+#define TLS_DTV_UNALLOCATED ((void *) -1l)
-diff --git a/sysdeps/riscv/dl-trampoline.S b/sysdeps/riscv/dl-trampoline.S
-new file mode 100644
-index 0000000..b3a4c09
---- /dev/null
-+++ b/sysdeps/riscv/dl-trampoline.S
-@@ -0,0 +1,40 @@
+diff -Nur original-glibc/sysdeps/riscv/dl-trampoline.S glibc/sysdeps/riscv/dl-trampoline.S
+--- original-glibc/sysdeps/riscv/dl-trampoline.S 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/dl-trampoline.S 2014-12-09 14:38:38.665778707 -0800
+@@ -0,0 +1,41 @@
+#include <sysdep.h>
+#include <sys/asm.h>
+
@@ -1343,6 +1179,7 @@ index 0000000..b3a4c09
+ mv a0, t0 # link map
+ add a1, a1, t1 # reloc offset (== thrice the .got.plt offset)
+ jal _dl_fixup
++ move t0, a0
+
+ # Restore arguments from stack.
+ REG_L ra, 9*SZREG(sp)
@@ -1357,13 +1194,11 @@ index 0000000..b3a4c09
+ addi sp, sp, 10*SZREG
+
+ # Invoke the callee.
-+ jr v0
++ jr t0
+END(_dl_runtime_resolve)
-diff --git a/sysdeps/riscv/fpu/bits/mathinline.h b/sysdeps/riscv/fpu/bits/mathinline.h
-new file mode 100644
-index 0000000..3c8a33d
---- /dev/null
-+++ b/sysdeps/riscv/fpu/bits/mathinline.h
+diff -Nur original-glibc/sysdeps/riscv/fpu/bits/mathinline.h glibc/sysdeps/riscv/fpu/bits/mathinline.h
+--- original-glibc/sysdeps/riscv/fpu/bits/mathinline.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/bits/mathinline.h 2014-12-09 14:32:35.932301937 -0800
@@ -0,0 +1,66 @@
+/* Inline math functions for RISC-V.
+ Copyright (C) 2011
@@ -1431,11 +1266,9 @@ index 0000000..3c8a33d
+
+#endif /* !__NO_MATH_INLINES && __OPTIMIZE__ */
+#endif /* __GNUC__ */
-diff --git a/sysdeps/riscv/fpu/fclrexcpt.c b/sysdeps/riscv/fpu/fclrexcpt.c
-new file mode 100644
-index 0000000..746dad9
---- /dev/null
-+++ b/sysdeps/riscv/fpu/fclrexcpt.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/fclrexcpt.c glibc/sysdeps/riscv/fpu/fclrexcpt.c
+--- original-glibc/sysdeps/riscv/fpu/fclrexcpt.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/fclrexcpt.c 2014-12-09 14:32:35.932301937 -0800
@@ -0,0 +1,29 @@
+/* Clear given exceptions in current floating-point environment.
+ Copyright (C) 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
@@ -1466,11 +1299,9 @@ index 0000000..746dad9
+ asm volatile ("csrc fflags, %0" : : "r"(excepts));
+ return 0;
+}
-diff --git a/sysdeps/riscv/fpu/fedisblxcpt.c b/sysdeps/riscv/fpu/fedisblxcpt.c
-new file mode 100644
-index 0000000..25eaee5
---- /dev/null
-+++ b/sysdeps/riscv/fpu/fedisblxcpt.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/fedisblxcpt.c glibc/sysdeps/riscv/fpu/fedisblxcpt.c
+--- original-glibc/sysdeps/riscv/fpu/fedisblxcpt.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/fedisblxcpt.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,29 @@
+/* Disable floating-point exceptions.
+ Copyright (C) 2000 Free Software Foundation, Inc.
@@ -1501,11 +1332,9 @@ index 0000000..25eaee5
+ /* FP exceptions never generate traps. */
+ return 0;
+}
-diff --git a/sysdeps/riscv/fpu/feenablxcpt.c b/sysdeps/riscv/fpu/feenablxcpt.c
-new file mode 100644
-index 0000000..761c58d
---- /dev/null
-+++ b/sysdeps/riscv/fpu/feenablxcpt.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/feenablxcpt.c glibc/sysdeps/riscv/fpu/feenablxcpt.c
+--- original-glibc/sysdeps/riscv/fpu/feenablxcpt.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/feenablxcpt.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,29 @@
+/* Enable floating-point exceptions.
+ Copyright (C) 2000 Free Software Foundation, Inc.
@@ -1536,11 +1365,9 @@ index 0000000..761c58d
+ /* FP exceptions never generate traps. */
+ return -1;
+}
-diff --git a/sysdeps/riscv/fpu/fegetenv.c b/sysdeps/riscv/fpu/fegetenv.c
-new file mode 100644
-index 0000000..da5d597
---- /dev/null
-+++ b/sysdeps/riscv/fpu/fegetenv.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/fegetenv.c glibc/sysdeps/riscv/fpu/fegetenv.c
+--- original-glibc/sysdeps/riscv/fpu/fegetenv.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/fegetenv.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,32 @@
+/* Store current floating-point environment.
+ Copyright (C) 1998, 1999, 2000, 2002, 2010 Free Software Foundation, Inc.
@@ -1574,11 +1401,9 @@ index 0000000..da5d597
+ return 0;
+}
+libm_hidden_def (fegetenv)
-diff --git a/sysdeps/riscv/fpu/fegetexcept.c b/sysdeps/riscv/fpu/fegetexcept.c
-new file mode 100644
-index 0000000..bdb4b7d
---- /dev/null
-+++ b/sysdeps/riscv/fpu/fegetexcept.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/fegetexcept.c glibc/sysdeps/riscv/fpu/fegetexcept.c
+--- original-glibc/sysdeps/riscv/fpu/fegetexcept.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/fegetexcept.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,29 @@
+/* Get enabled floating-point exceptions.
+ Copyright (C) 2000 Free Software Foundation, Inc.
@@ -1609,11 +1434,9 @@ index 0000000..bdb4b7d
+ /* FP exceptions never generate traps. */
+ return 0;
+}
-diff --git a/sysdeps/riscv/fpu/fegetround.c b/sysdeps/riscv/fpu/fegetround.c
-new file mode 100644
-index 0000000..47eb92f
---- /dev/null
-+++ b/sysdeps/riscv/fpu/fegetround.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/fegetround.c glibc/sysdeps/riscv/fpu/fegetround.c
+--- original-glibc/sysdeps/riscv/fpu/fegetround.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/fegetround.c 2014-12-09 14:32:35.932301937 -0800
@@ -0,0 +1,30 @@
+/* Return current rounding direction.
+ Copyright (C) 1998 Free Software Foundation, Inc.
@@ -1645,11 +1468,9 @@ index 0000000..47eb92f
+ _FPU_GETROUND (round);
+ return round;
+}
-diff --git a/sysdeps/riscv/fpu/feholdexcpt.c b/sysdeps/riscv/fpu/feholdexcpt.c
-new file mode 100644
-index 0000000..3d8fa22
---- /dev/null
-+++ b/sysdeps/riscv/fpu/feholdexcpt.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/feholdexcpt.c glibc/sysdeps/riscv/fpu/feholdexcpt.c
+--- original-glibc/sysdeps/riscv/fpu/feholdexcpt.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/feholdexcpt.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,32 @@
+/* Store current floating-point environment and clear exceptions.
+ Copyright (C) 2000 Free Software Foundation, Inc.
@@ -1683,11 +1504,9 @@ index 0000000..3d8fa22
+}
+
+libm_hidden_def (feholdexcept)
-diff --git a/sysdeps/riscv/fpu/fesetenv.c b/sysdeps/riscv/fpu/fesetenv.c
-new file mode 100644
-index 0000000..e34fdaf
---- /dev/null
-+++ b/sysdeps/riscv/fpu/fesetenv.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/fesetenv.c glibc/sysdeps/riscv/fpu/fesetenv.c
+--- original-glibc/sysdeps/riscv/fpu/fesetenv.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/fesetenv.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,31 @@
+/* Install given floating-point environment.
+ Copyright (C) 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
@@ -1720,11 +1539,9 @@ index 0000000..e34fdaf
+}
+
+libm_hidden_def (fesetenv)
-diff --git a/sysdeps/riscv/fpu/fesetround.c b/sysdeps/riscv/fpu/fesetround.c
-new file mode 100644
-index 0000000..ad80465
---- /dev/null
-+++ b/sysdeps/riscv/fpu/fesetround.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/fesetround.c glibc/sysdeps/riscv/fpu/fesetround.c
+--- original-glibc/sysdeps/riscv/fpu/fesetround.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/fesetround.c 2014-12-09 14:32:35.932301937 -0800
@@ -0,0 +1,34 @@
+/* Set current rounding direction.
+ Copyright (C) 1998 Free Software Foundation, Inc.
@@ -1760,11 +1577,9 @@ index 0000000..ad80465
+}
+
+libm_hidden_def (fesetround)
-diff --git a/sysdeps/riscv/fpu/feupdateenv.c b/sysdeps/riscv/fpu/feupdateenv.c
-new file mode 100644
-index 0000000..51611cd
---- /dev/null
-+++ b/sysdeps/riscv/fpu/feupdateenv.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/feupdateenv.c glibc/sysdeps/riscv/fpu/feupdateenv.c
+--- original-glibc/sysdeps/riscv/fpu/feupdateenv.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/feupdateenv.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,35 @@
+/* Install given floating-point environment and raise exceptions.
+ Copyright (C) 1998, 1999, 2000, 2002, 2010 Free Software Foundation, Inc.
@@ -1801,11 +1616,9 @@ index 0000000..51611cd
+ return 0;
+}
+libm_hidden_def (feupdateenv)
-diff --git a/sysdeps/riscv/fpu/fgetexcptflg.c b/sysdeps/riscv/fpu/fgetexcptflg.c
-new file mode 100644
-index 0000000..537f5b7
---- /dev/null
-+++ b/sysdeps/riscv/fpu/fgetexcptflg.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/fgetexcptflg.c glibc/sysdeps/riscv/fpu/fgetexcptflg.c
+--- original-glibc/sysdeps/riscv/fpu/fgetexcptflg.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/fgetexcptflg.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,35 @@
+/* Store current representation for exceptions.
+ Copyright (C) 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
@@ -1842,11 +1655,9 @@ index 0000000..537f5b7
+ /* Success. */
+ return 0;
+}
-diff --git a/sysdeps/riscv/fpu/fraiseexcpt.c b/sysdeps/riscv/fpu/fraiseexcpt.c
-new file mode 100644
-index 0000000..2a839d0
---- /dev/null
-+++ b/sysdeps/riscv/fpu/fraiseexcpt.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/fraiseexcpt.c glibc/sysdeps/riscv/fpu/fraiseexcpt.c
+--- original-glibc/sysdeps/riscv/fpu/fraiseexcpt.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/fraiseexcpt.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,31 @@
+/* Raise given exceptions.
+ Copyright (C) 2000, 2002 Free Software Foundation, Inc.
@@ -1879,11 +1690,9 @@ index 0000000..2a839d0
+}
+
+libm_hidden_def (feraiseexcept)
-diff --git a/sysdeps/riscv/fpu/fsetexcptflg.c b/sysdeps/riscv/fpu/fsetexcptflg.c
-new file mode 100644
-index 0000000..c28235a
---- /dev/null
-+++ b/sysdeps/riscv/fpu/fsetexcptflg.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/fsetexcptflg.c glibc/sysdeps/riscv/fpu/fsetexcptflg.c
+--- original-glibc/sysdeps/riscv/fpu/fsetexcptflg.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/fsetexcptflg.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,32 @@
+/* Set floating-point environment exception handling.
+ Copyright (C) 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
@@ -1917,11 +1726,9 @@ index 0000000..c28235a
+
+ return 0;
+}
-diff --git a/sysdeps/riscv/fpu/ftestexcept.c b/sysdeps/riscv/fpu/ftestexcept.c
-new file mode 100644
-index 0000000..8235fa1
---- /dev/null
-+++ b/sysdeps/riscv/fpu/ftestexcept.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/ftestexcept.c glibc/sysdeps/riscv/fpu/ftestexcept.c
+--- original-glibc/sysdeps/riscv/fpu/ftestexcept.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/ftestexcept.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,33 @@
+/* Test exception in current environment.
+ Copyright (C) 1998, 2010 Free Software Foundation, Inc.
@@ -1956,14 +1763,9 @@ index 0000000..8235fa1
+ return cw & excepts;
+}
+libm_hidden_def (fetestexcept)
-diff --git a/sysdeps/riscv/fpu/libm-test-ulps b/sysdeps/riscv/fpu/libm-test-ulps
-new file mode 100644
-index 0000000..e69de29
-diff --git a/sysdeps/riscv/fpu/s_copysign.c b/sysdeps/riscv/fpu/s_copysign.c
-new file mode 100644
-index 0000000..32dc5dc
---- /dev/null
-+++ b/sysdeps/riscv/fpu/s_copysign.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/s_copysign.c glibc/sysdeps/riscv/fpu/s_copysign.c
+--- original-glibc/sysdeps/riscv/fpu/s_copysign.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/s_copysign.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,9 @@
+#include "math.h"
+
@@ -1974,11 +1776,9 @@ index 0000000..32dc5dc
+ return res;
+}
+weak_alias (__copysign, copysign)
-diff --git a/sysdeps/riscv/fpu/s_copysignf.c b/sysdeps/riscv/fpu/s_copysignf.c
-new file mode 100644
-index 0000000..11d493b
---- /dev/null
-+++ b/sysdeps/riscv/fpu/s_copysignf.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/s_copysignf.c glibc/sysdeps/riscv/fpu/s_copysignf.c
+--- original-glibc/sysdeps/riscv/fpu/s_copysignf.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/s_copysignf.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,9 @@
+#include "math.h"
+
@@ -1989,11 +1789,9 @@ index 0000000..11d493b
+ return res;
+}
+weak_alias (__copysignf, copysignf)
-diff --git a/sysdeps/riscv/fpu/s_fabs.c b/sysdeps/riscv/fpu/s_fabs.c
-new file mode 100644
-index 0000000..95f5b28
---- /dev/null
-+++ b/sysdeps/riscv/fpu/s_fabs.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/s_fabs.c glibc/sysdeps/riscv/fpu/s_fabs.c
+--- original-glibc/sysdeps/riscv/fpu/s_fabs.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/s_fabs.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,9 @@
+#include "math.h"
+
@@ -2004,11 +1802,9 @@ index 0000000..95f5b28
+ return res;
+}
+weak_alias (__fabs, fabs)
-diff --git a/sysdeps/riscv/fpu/s_fabsf.c b/sysdeps/riscv/fpu/s_fabsf.c
-new file mode 100644
-index 0000000..9df4ae6
---- /dev/null
-+++ b/sysdeps/riscv/fpu/s_fabsf.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/s_fabsf.c glibc/sysdeps/riscv/fpu/s_fabsf.c
+--- original-glibc/sysdeps/riscv/fpu/s_fabsf.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/s_fabsf.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,9 @@
+#include "math.h"
+
@@ -2019,11 +1815,9 @@ index 0000000..9df4ae6
+ return res;
+}
+weak_alias (__fabsf, fabsf)
-diff --git a/sysdeps/riscv/fpu/s_fdim.c b/sysdeps/riscv/fpu/s_fdim.c
-new file mode 100644
-index 0000000..9835f59
---- /dev/null
-+++ b/sysdeps/riscv/fpu/s_fdim.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/s_fdim.c glibc/sysdeps/riscv/fpu/s_fdim.c
+--- original-glibc/sysdeps/riscv/fpu/s_fdim.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/s_fdim.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,17 @@
+#include <errno.h>
+#include <math.h>
@@ -2042,11 +1836,9 @@ index 0000000..9835f59
+ return diff;
+}
+weak_alias (__fdim, fdim)
-diff --git a/sysdeps/riscv/fpu/s_fdimf.c b/sysdeps/riscv/fpu/s_fdimf.c
-new file mode 100644
-index 0000000..480136c
---- /dev/null
-+++ b/sysdeps/riscv/fpu/s_fdimf.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/s_fdimf.c glibc/sysdeps/riscv/fpu/s_fdimf.c
+--- original-glibc/sysdeps/riscv/fpu/s_fdimf.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/s_fdimf.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,17 @@
+#include <errno.h>
+#include <math.h>
@@ -2065,11 +1857,9 @@ index 0000000..480136c
+ return diff;
+}
+weak_alias (__fdimf, fdimf)
-diff --git a/sysdeps/riscv/fpu/s_finite.c b/sysdeps/riscv/fpu/s_finite.c
-new file mode 100644
-index 0000000..bf2135b
---- /dev/null
-+++ b/sysdeps/riscv/fpu/s_finite.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/s_finite.c glibc/sysdeps/riscv/fpu/s_finite.c
+--- original-glibc/sysdeps/riscv/fpu/s_finite.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/s_finite.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,9 @@
+#include "math.h"
+#include "fpu_control.h"
@@ -2080,11 +1870,9 @@ index 0000000..bf2135b
+}
+hidden_def (__finite)
+weak_alias (__finite, finite)
-diff --git a/sysdeps/riscv/fpu/s_finitef.c b/sysdeps/riscv/fpu/s_finitef.c
-new file mode 100644
-index 0000000..6448d2d
---- /dev/null
-+++ b/sysdeps/riscv/fpu/s_finitef.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/s_finitef.c glibc/sysdeps/riscv/fpu/s_finitef.c
+--- original-glibc/sysdeps/riscv/fpu/s_finitef.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/s_finitef.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,9 @@
+#include "math.h"
+#include "fpu_control.h"
@@ -2095,11 +1883,9 @@ index 0000000..6448d2d
+}
+hidden_def (__finitef)
+weak_alias (__finitef, finitef)
-diff --git a/sysdeps/riscv/fpu/s_fma.c b/sysdeps/riscv/fpu/s_fma.c
-new file mode 100644
-index 0000000..797bc7d
---- /dev/null
-+++ b/sysdeps/riscv/fpu/s_fma.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/s_fma.c glibc/sysdeps/riscv/fpu/s_fma.c
+--- original-glibc/sysdeps/riscv/fpu/s_fma.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/s_fma.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,11 @@
+#include <math.h>
+#include <fenv.h>
@@ -2112,11 +1898,9 @@ index 0000000..797bc7d
+ return out;
+}
+weak_alias (__fma, fma)
-diff --git a/sysdeps/riscv/fpu/s_fmaf.c b/sysdeps/riscv/fpu/s_fmaf.c
-new file mode 100644
-index 0000000..11775f9
---- /dev/null
-+++ b/sysdeps/riscv/fpu/s_fmaf.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/s_fmaf.c glibc/sysdeps/riscv/fpu/s_fmaf.c
+--- original-glibc/sysdeps/riscv/fpu/s_fmaf.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/s_fmaf.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,11 @@
+#include <math.h>
+#include <fenv.h>
@@ -2129,11 +1913,9 @@ index 0000000..11775f9
+ return out;
+}
+weak_alias (__fmaf, fmaf)
-diff --git a/sysdeps/riscv/fpu/s_fmax.c b/sysdeps/riscv/fpu/s_fmax.c
-new file mode 100644
-index 0000000..8d2e662
---- /dev/null
-+++ b/sysdeps/riscv/fpu/s_fmax.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/s_fmax.c glibc/sysdeps/riscv/fpu/s_fmax.c
+--- original-glibc/sysdeps/riscv/fpu/s_fmax.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/s_fmax.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,9 @@
+#include <math.h>
+
@@ -2144,11 +1926,9 @@ index 0000000..8d2e662
+ return res;
+}
+weak_alias (__fmax, fmax)
-diff --git a/sysdeps/riscv/fpu/s_fmaxf.c b/sysdeps/riscv/fpu/s_fmaxf.c
-new file mode 100644
-index 0000000..aa62172
---- /dev/null
-+++ b/sysdeps/riscv/fpu/s_fmaxf.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/s_fmaxf.c glibc/sysdeps/riscv/fpu/s_fmaxf.c
+--- original-glibc/sysdeps/riscv/fpu/s_fmaxf.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/s_fmaxf.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,9 @@
+#include <math.h>
+
@@ -2159,11 +1939,9 @@ index 0000000..aa62172
+ return res;
+}
+weak_alias (__fmaxf, fmaxf)
-diff --git a/sysdeps/riscv/fpu/s_fmin.c b/sysdeps/riscv/fpu/s_fmin.c
-new file mode 100644
-index 0000000..e4e37df
---- /dev/null
-+++ b/sysdeps/riscv/fpu/s_fmin.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/s_fmin.c glibc/sysdeps/riscv/fpu/s_fmin.c
+--- original-glibc/sysdeps/riscv/fpu/s_fmin.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/s_fmin.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,9 @@
+#include <math.h>
+
@@ -2174,11 +1952,9 @@ index 0000000..e4e37df
+ return res;
+}
+weak_alias (__fmin, fmin)
-diff --git a/sysdeps/riscv/fpu/s_fminf.c b/sysdeps/riscv/fpu/s_fminf.c
-new file mode 100644
-index 0000000..5d25bc2
---- /dev/null
-+++ b/sysdeps/riscv/fpu/s_fminf.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/s_fminf.c glibc/sysdeps/riscv/fpu/s_fminf.c
+--- original-glibc/sysdeps/riscv/fpu/s_fminf.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/s_fminf.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,9 @@
+#include <math.h>
+
@@ -2189,11 +1965,9 @@ index 0000000..5d25bc2
+ return res;
+}
+weak_alias (__fminf, fminf)
-diff --git a/sysdeps/riscv/fpu/s_fpclassify.c b/sysdeps/riscv/fpu/s_fpclassify.c
-new file mode 100644
-index 0000000..2b58c3f
---- /dev/null
-+++ b/sysdeps/riscv/fpu/s_fpclassify.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/s_fpclassify.c glibc/sysdeps/riscv/fpu/s_fpclassify.c
+--- original-glibc/sysdeps/riscv/fpu/s_fpclassify.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/s_fpclassify.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,18 @@
+#include <math.h>
+#include "fpu_control.h"
@@ -2213,11 +1987,9 @@ index 0000000..2b58c3f
+ return FP_NAN;
+}
+libm_hidden_def (__fpclassify)
-diff --git a/sysdeps/riscv/fpu/s_fpclassifyf.c b/sysdeps/riscv/fpu/s_fpclassifyf.c
-new file mode 100644
-index 0000000..fae20fa
---- /dev/null
-+++ b/sysdeps/riscv/fpu/s_fpclassifyf.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/s_fpclassifyf.c glibc/sysdeps/riscv/fpu/s_fpclassifyf.c
+--- original-glibc/sysdeps/riscv/fpu/s_fpclassifyf.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/s_fpclassifyf.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,18 @@
+#include <math.h>
+#include "fpu_control.h"
@@ -2237,11 +2009,9 @@ index 0000000..fae20fa
+ return FP_NAN;
+}
+libm_hidden_def (__fpclassifyf)
-diff --git a/sysdeps/riscv/fpu/s_isinf.c b/sysdeps/riscv/fpu/s_isinf.c
-new file mode 100644
-index 0000000..339d97f
---- /dev/null
-+++ b/sysdeps/riscv/fpu/s_isinf.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/s_isinf.c glibc/sysdeps/riscv/fpu/s_isinf.c
+--- original-glibc/sysdeps/riscv/fpu/s_isinf.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/s_isinf.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,10 @@
+#include "math.h"
+#include "fpu_control.h"
@@ -2253,11 +2023,9 @@ index 0000000..339d97f
+}
+hidden_def (__isinf)
+weak_alias (__isinf, isinf)
-diff --git a/sysdeps/riscv/fpu/s_isinff.c b/sysdeps/riscv/fpu/s_isinff.c
-new file mode 100644
-index 0000000..501342e
---- /dev/null
-+++ b/sysdeps/riscv/fpu/s_isinff.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/s_isinff.c glibc/sysdeps/riscv/fpu/s_isinff.c
+--- original-glibc/sysdeps/riscv/fpu/s_isinff.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/s_isinff.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,10 @@
+#include "math.h"
+#include "fpu_control.h"
@@ -2269,11 +2037,9 @@ index 0000000..501342e
+}
+hidden_def (__isinff)
+weak_alias (__isinff, isinff)
-diff --git a/sysdeps/riscv/fpu/s_isnan.c b/sysdeps/riscv/fpu/s_isnan.c
-new file mode 100644
-index 0000000..dcbb629
---- /dev/null
-+++ b/sysdeps/riscv/fpu/s_isnan.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/s_isnan.c glibc/sysdeps/riscv/fpu/s_isnan.c
+--- original-glibc/sysdeps/riscv/fpu/s_isnan.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/s_isnan.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,9 @@
+#include "math.h"
+#include "fpu_control.h"
@@ -2284,11 +2050,9 @@ index 0000000..dcbb629
+}
+hidden_def (__isnan)
+weak_alias (__isnan, isnan)
-diff --git a/sysdeps/riscv/fpu/s_isnanf.c b/sysdeps/riscv/fpu/s_isnanf.c
-new file mode 100644
-index 0000000..78e9d0c
---- /dev/null
-+++ b/sysdeps/riscv/fpu/s_isnanf.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/s_isnanf.c glibc/sysdeps/riscv/fpu/s_isnanf.c
+--- original-glibc/sysdeps/riscv/fpu/s_isnanf.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/s_isnanf.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,9 @@
+#include "math.h"
+#include "fpu_control.h"
@@ -2299,11 +2063,9 @@ index 0000000..78e9d0c
+}
+hidden_def (__isnanf)
+weak_alias (__isnanf, isnanf)
-diff --git a/sysdeps/riscv/fpu/s_signbit.c b/sysdeps/riscv/fpu/s_signbit.c
-new file mode 100644
-index 0000000..5f99c3f
---- /dev/null
-+++ b/sysdeps/riscv/fpu/s_signbit.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/s_signbit.c glibc/sysdeps/riscv/fpu/s_signbit.c
+--- original-glibc/sysdeps/riscv/fpu/s_signbit.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/s_signbit.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,18 @@
+#include <features.h>
+#undef __USE_EXTERN_INLINES
@@ -2323,11 +2085,9 @@ index 0000000..5f99c3f
+ return hx < 0;
+#endif
+}
-diff --git a/sysdeps/riscv/fpu/s_signbitf.c b/sysdeps/riscv/fpu/s_signbitf.c
-new file mode 100644
-index 0000000..6e25688
---- /dev/null
-+++ b/sysdeps/riscv/fpu/s_signbitf.c
+diff -Nur original-glibc/sysdeps/riscv/fpu/s_signbitf.c glibc/sysdeps/riscv/fpu/s_signbitf.c
+--- original-glibc/sysdeps/riscv/fpu/s_signbitf.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu/s_signbitf.c 2014-12-09 14:31:16.755856778 -0800
@@ -0,0 +1,12 @@
+#include <features.h>
+#undef __USE_EXTERN_INLINES
@@ -2341,11 +2101,9 @@ index 0000000..6e25688
+ GET_FLOAT_WORD (hx, x);
+ return hx < 0;
+}
-diff --git a/sysdeps/riscv/fpu_control.h b/sysdeps/riscv/fpu_control.h
-new file mode 100644
-index 0000000..4c36db5
---- /dev/null
-+++ b/sysdeps/riscv/fpu_control.h
+diff -Nur original-glibc/sysdeps/riscv/fpu_control.h glibc/sysdeps/riscv/fpu_control.h
+--- original-glibc/sysdeps/riscv/fpu_control.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/fpu_control.h 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,92 @@
+/* FPU control word bits. Mips version.
+ Copyright (C) 1996, 1997, 1998, 1999, 2000, 2006, 2008
@@ -2439,11 +2197,9 @@ index 0000000..4c36db5
+#endif /* __mips_soft_float */
+
+#endif /* fpu_control.h */
-diff --git a/sysdeps/riscv/gccframe.h b/sysdeps/riscv/gccframe.h
-new file mode 100644
-index 0000000..ec9311c
---- /dev/null
-+++ b/sysdeps/riscv/gccframe.h
+diff -Nur original-glibc/sysdeps/riscv/gccframe.h glibc/sysdeps/riscv/gccframe.h
+--- original-glibc/sysdeps/riscv/gccframe.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/gccframe.h 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,22 @@
+/* Definition of object in frame unwind info. mips version.
+ Copyright (C) 2001 Free Software Foundation, Inc.
@@ -2467,11 +2223,9 @@ index 0000000..ec9311c
+#define FIRST_PSEUDO_REGISTER 76
+
+#include <sysdeps/generic/gccframe.h>
-diff --git a/sysdeps/riscv/ieee754.h b/sysdeps/riscv/ieee754.h
-new file mode 100644
-index 0000000..912e088
---- /dev/null
-+++ b/sysdeps/riscv/ieee754.h
+diff -Nur original-glibc/sysdeps/riscv/ieee754.h glibc/sysdeps/riscv/ieee754.h
+--- original-glibc/sysdeps/riscv/ieee754.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/ieee754.h 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,325 @@
+/* Copyright (C) 1992, 1995, 1996, 1999, 2002, 2003
+ Free Software Foundation, Inc.
@@ -2798,11 +2552,20 @@ index 0000000..912e088
+__END_DECLS
+
+#endif /* ieee754.h */
-diff --git a/sysdeps/riscv/jmpbuf-unwind.h b/sysdeps/riscv/jmpbuf-unwind.h
-new file mode 100644
-index 0000000..bfa1a64
---- /dev/null
-+++ b/sysdeps/riscv/jmpbuf-unwind.h
+diff -Nur original-glibc/sysdeps/riscv/Implies glibc/sysdeps/riscv/Implies
+--- original-glibc/sysdeps/riscv/Implies 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/Implies 2014-12-09 14:31:16.755856778 -0800
+@@ -0,0 +1,7 @@
++init_array
++
++ieee754/flt-32
++ieee754/dbl-64
++
++# This needs to change to support rv32
++riscv/rv64
+diff -Nur original-glibc/sysdeps/riscv/jmpbuf-unwind.h glibc/sysdeps/riscv/jmpbuf-unwind.h
+--- original-glibc/sysdeps/riscv/jmpbuf-unwind.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/jmpbuf-unwind.h 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,46 @@
+/* Copyright (C) 2003, 2005, 2006 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
@@ -2850,11 +2613,9 @@ index 0000000..bfa1a64
+
+/* We use the normal longjmp for unwinding. */
+#define __libc_unwind_longjmp(buf, val) __libc_longjmp (buf, val)
-diff --git a/sysdeps/riscv/ldsodefs.h b/sysdeps/riscv/ldsodefs.h
-new file mode 100644
-index 0000000..8820a08
---- /dev/null
-+++ b/sysdeps/riscv/ldsodefs.h
+diff -Nur original-glibc/sysdeps/riscv/ldsodefs.h glibc/sysdeps/riscv/ldsodefs.h
+--- original-glibc/sysdeps/riscv/ldsodefs.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/ldsodefs.h 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,70 @@
+/* Run-time dynamic linker data structures for loaded ELF shared objects.
+ Copyright (C) 2000, 2002, 2003, 2006, 2007 Free Software Foundation, Inc.
@@ -2926,11 +2687,9 @@ index 0000000..8820a08
+#include_next <ldsodefs.h>
+
+#endif
-diff --git a/sysdeps/riscv/libc-tls.c b/sysdeps/riscv/libc-tls.c
-new file mode 100644
-index 0000000..9984dce
---- /dev/null
-+++ b/sysdeps/riscv/libc-tls.c
+diff -Nur original-glibc/sysdeps/riscv/libc-tls.c glibc/sysdeps/riscv/libc-tls.c
+--- original-glibc/sysdeps/riscv/libc-tls.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/libc-tls.c 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,37 @@
+/* Thread-local storage handling in the ELF dynamic linker. MIPS version.
+ Copyright (C) 2005 Free Software Foundation, Inc.
@@ -2969,11 +2728,129 @@ index 0000000..9984dce
+}
+
+#endif
-diff --git a/sysdeps/riscv/memcpy.c b/sysdeps/riscv/memcpy.c
-new file mode 100644
-index 0000000..c4db923
---- /dev/null
-+++ b/sysdeps/riscv/memcpy.c
+diff -Nur original-glibc/sysdeps/riscv/__longjmp.S glibc/sysdeps/riscv/__longjmp.S
+--- original-glibc/sysdeps/riscv/__longjmp.S 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/__longjmp.S 2014-12-09 14:38:38.665778707 -0800
+@@ -0,0 +1,63 @@
++/* Copyright (C) 1996, 1997, 2000, 2002, 2003, 2004
++ Free Software Foundation, Inc.
++ This file is part of the GNU C Library.
++
++ The GNU C Library is free software; you can redistribute it and/or
++ modify it under the terms of the GNU Lesser General Public
++ License as published by the Free Software Foundation; either
++ version 2.1 of the License, or (at your option) any later version.
++
++ The GNU C Library is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ Lesser General Public License for more details.
++
++ You should have received a copy of the GNU Lesser General Public
++ License along with the GNU C Library; if not, write to the Free
++ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
++ 02111-1307 USA. */
++
++#include <sysdep.h>
++#include <sys/asm.h>
++
++ENTRY (__longjmp)
++ REG_L ra, 0*SZREG(a0)
++ REG_L s0, 1*SZREG(a0)
++ REG_L s1, 2*SZREG(a0)
++ REG_L s2, 3*SZREG(a0)
++ REG_L s3, 4*SZREG(a0)
++ REG_L s4, 5*SZREG(a0)
++ REG_L s5, 6*SZREG(a0)
++ REG_L s6, 7*SZREG(a0)
++ REG_L s7, 8*SZREG(a0)
++ REG_L s8, 9*SZREG(a0)
++ REG_L s9, 10*SZREG(a0)
++ REG_L s10,11*SZREG(a0)
++ REG_L s11,12*SZREG(a0)
++ REG_L sp, 13*SZREG(a0)
++ REG_L tp, 14*SZREG(a0)
++
++#ifdef __riscv_hard_float
++ REG_L a3, 15*SZREG(a0)
++
++ fld fs0, 16*SZREG+ 0*8(a0)
++ fld fs1, 16*SZREG+ 1*8(a0)
++ fld fs2, 16*SZREG+ 2*8(a0)
++ fld fs3, 16*SZREG+ 3*8(a0)
++ fld fs4, 16*SZREG+ 4*8(a0)
++ fld fs5, 16*SZREG+ 5*8(a0)
++ fld fs6, 16*SZREG+ 6*8(a0)
++ fld fs7, 16*SZREG+ 7*8(a0)
++ fld fs8, 16*SZREG+ 8*8(a0)
++ fld fs9, 16*SZREG+ 9*8(a0)
++ fld fs10,16*SZREG+10*8(a0)
++ fld fs11,16*SZREG+11*8(a0)
++
++ fssr a3
++#endif
++
++ seqz a0, a1
++ add a0, a0, a1 # a0 = (a1 == 0) ? 1 : a1
++ ret
++
++END(__longjmp)
+diff -Nur original-glibc/sysdeps/riscv/Makefile glibc/sysdeps/riscv/Makefile
+--- original-glibc/sysdeps/riscv/Makefile 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/Makefile 2014-12-09 14:32:35.932301937 -0800
+@@ -0,0 +1,49 @@
++ifneq ($(all-rtld-routines),)
++CFLAGS-rtld.c += -mno-plt
++CFLAGS-dl-load.c += -mno-plt
++CFLAGS-dl-cache.c += -mno-plt
++CFLAGS-dl-lookup.c += -mno-plt
++CFLAGS-dl-object.c += -mno-plt
++CFLAGS-dl-reloc.c += -mno-plt
++CFLAGS-dl-deps.c += -mno-plt
++CFLAGS-dl-runtime.c += -mno-plt
++CFLAGS-dl-error.c += -mno-plt
++CFLAGS-dl-init.c += -mno-plt
++CFLAGS-dl-fini.c += -mno-plt
++CFLAGS-dl-debug.c += -mno-plt
++CFLAGS-dl-misc.c += -mno-plt
++CFLAGS-dl-version.c += -mno-plt
++CFLAGS-dl-profile.c += -mno-plt
++CFLAGS-dl-conflict.c += -mno-plt
++CFLAGS-dl-tls.c += -mno-plt
++CFLAGS-dl-origin.c += -mno-plt
++CFLAGS-dl-scope.c += -mno-plt
++CFLAGS-dl-execstack.c += -mno-plt
++CFLAGS-dl-caller.c += -mno-plt
++CFLAGS-dl-open.c += -mno-plt
++CFLAGS-dl-close.c += -mno-plt
++CFLAGS-dl-sysdep.c += -mno-plt
++CFLAGS-dl-environ.c += -mno-plt
++CFLAGS-dl-minimal.c += -mno-plt
++CFLAGS-dl-static.c += -mno-plt
++CFLAGS-dl-brk.c += -mno-plt
++CFLAGS-dl-sbrk.c += -mno-plt
++CFLAGS-dl-getcwd.c += -mno-plt
++CFLAGS-dl-openat64.c += -mno-plt
++CFLAGS-dl-opendir.c += -mno-plt
++CFLAGS-dl-fxstatat64.c += -mno-plt
++endif
++
++CFLAGS-closedir.c += -mno-plt
++CFLAGS-exit.c += -mno-plt
++CFLAGS-cxa_atexit.c += -mno-plt
++
++ifeq ($(subdir),misc)
++sysdep_headers += sys/asm.h sgidefs.h
++endif
++
++ifeq ($(subdir),rt)
++librt-sysdep_routines += rt-sysdep
++endif
++
++ASFLAGS-.os += $(pic-ccflag)
+diff -Nur original-glibc/sysdeps/riscv/memcpy.c glibc/sysdeps/riscv/memcpy.c
+--- original-glibc/sysdeps/riscv/memcpy.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/memcpy.c 2014-12-09 14:32:35.932301937 -0800
@@ -0,0 +1,70 @@
+#include <string.h>
+#include <stdint.h>
@@ -3045,11 +2922,9 @@ index 0000000..c4db923
+}
+weak_alias (__memcpy, memcpy)
+libc_hidden_builtin_def (memcpy)
-diff --git a/sysdeps/riscv/memset.S b/sysdeps/riscv/memset.S
-new file mode 100644
-index 0000000..fcfba96
---- /dev/null
-+++ b/sysdeps/riscv/memset.S
+diff -Nur original-glibc/sysdeps/riscv/memset.S glibc/sysdeps/riscv/memset.S
+--- original-glibc/sysdeps/riscv/memset.S 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/memset.S 2014-12-09 14:38:38.665778707 -0800
@@ -0,0 +1,107 @@
+/* Copyright (C) 2014 Free Software Foundation, Inc.
+ Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
@@ -3074,9 +2949,9 @@ index 0000000..fcfba96
+
+ENTRY(memset)
+ li a6, 15
-+ move v0, a0
++ move a4, a0
+ bleu a2, a6, .Ltiny
-+ and a5, a0, 15
++ and a5, a4, 15
+ bnez a5, .Lmisaligned
+
+.Laligned:
@@ -3085,19 +2960,19 @@ index 0000000..fcfba96
+.Lwordified:
+ and a3, a2, ~15
+ and a2, a2, 15
-+ add a3, a3, a0
++ add a3, a3, a4
+
+#ifdef __riscv64
-+1:sd a1, 0(a0)
-+ sd a1, 8(a0)
++1:sd a1, 0(a4)
++ sd a1, 8(a4)
+#else
-+1:sw a1, 0(a0)
-+ sw a1, 4(a0)
-+ sw a1, 8(a0)
-+ sw a1, 12(a0)
++1:sw a1, 0(a4)
++ sw a1, 4(a4)
++ sw a1, 8(a4)
++ sw a1, 12(a4)
+#endif
-+ add a0, a0, 16
-+ bltu a0, a3, 1b
++ add a4, a4, 16
++ bltu a4, a3, 1b
+
+ bnez a2, .Ltiny
+ ret
@@ -3105,28 +2980,28 @@ index 0000000..fcfba96
+.Ltiny:
+ sub a3, a6, a2
+ sll a3, a3, 2
-+1:auipc a4, %pcrel_hi(.Ltable)
-+ add a3, a3, a4
++1:auipc t0, %pcrel_hi(.Ltable)
++ add a3, a3, t0
+.option push
+.option norvc
+.Ltable_misaligned:
+ jr a3, %pcrel_lo(1b)
+.Ltable:
-+ sb a1,14(a0)
-+ sb a1,13(a0)
-+ sb a1,12(a0)
-+ sb a1,11(a0)
-+ sb a1,10(a0)
-+ sb a1, 9(a0)
-+ sb a1, 8(a0)
-+ sb a1, 7(a0)
-+ sb a1, 6(a0)
-+ sb a1, 5(a0)
-+ sb a1, 4(a0)
-+ sb a1, 3(a0)
-+ sb a1, 2(a0)
-+ sb a1, 1(a0)
-+ sb a1, 0(a0)
++ sb a1,14(a4)
++ sb a1,13(a4)
++ sb a1,12(a4)
++ sb a1,11(a4)
++ sb a1,10(a4)
++ sb a1, 9(a4)
++ sb a1, 8(a4)
++ sb a1, 7(a4)
++ sb a1, 6(a4)
++ sb a1, 5(a4)
++ sb a1, 4(a4)
++ sb a1, 3(a4)
++ sb a1, 2(a4)
++ sb a1, 1(a4)
++ sb a1, 0(a4)
+.option pop
+ ret
+
@@ -3144,25 +3019,23 @@ index 0000000..fcfba96
+
+.Lmisaligned:
+ sll a3, a5, 2
-+1:auipc a4, %pcrel_hi(.Ltable_misaligned)
-+ add a3, a3, a4
++1:auipc t0, %pcrel_hi(.Ltable_misaligned)
++ add a3, a3, t0
+ mv t0, ra
+ jalr a3, %pcrel_lo(1b)
+ mv ra, t0
+
+ add a5, a5, -16
-+ sub a0, a0, a5
++ sub a4, a4, a5
+ add a2, a2, a5
+ bleu a2, a6, .Ltiny
+ j .Laligned
+END(memset)
+
+weak_alias(memset, __GI_memset)
-diff --git a/sysdeps/riscv/memusage.h b/sysdeps/riscv/memusage.h
-new file mode 100644
-index 0000000..c558a06
---- /dev/null
-+++ b/sysdeps/riscv/memusage.h
+diff -Nur original-glibc/sysdeps/riscv/memusage.h glibc/sysdeps/riscv/memusage.h
+--- original-glibc/sysdeps/riscv/memusage.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/memusage.h 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,21 @@
+/* Copyright (C) 2000 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
@@ -3185,42 +3058,9 @@ index 0000000..c558a06
+#define GETSP() ({ register uintptr_t stack_ptr asm ("sp"); stack_ptr; })
+
+#include <sysdeps/generic/memusage.h>
-diff --git a/sysdeps/riscv/nptl/Makefile b/sysdeps/riscv/nptl/Makefile
-new file mode 100644
-index 0000000..d0c59a5
---- /dev/null
-+++ b/sysdeps/riscv/nptl/Makefile
-@@ -0,0 +1,25 @@
-+# Copyright (C) 2005 Free Software Foundation, Inc.
-+# This file is part of the GNU C Library.
-+#
-+# The GNU C Library is free software; you can redistribute it and/or
-+# modify it under the terms of the GNU Lesser General Public
-+# License as published by the Free Software Foundation; either
-+# version 2.1 of the License, or (at your option) any later version.
-+#
-+# The GNU C Library is distributed in the hope that it will be useful,
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+# Lesser General Public License for more details.
-+#
-+# You should have received a copy of the GNU Lesser General Public
-+# License along with the GNU C Library; if not, write to the Free
-+# Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
-+# 02111-1307 USA.
-+
-+ifeq ($(subdir),csu)
-+gen-as-const-headers += tcb-offsets.sym
-+endif
-+
-+ifeq ($(subdir),nptl)
-+libpthread-sysdep_routines += nptl-sysdep
-+endif
-diff --git a/sysdeps/riscv/nptl/bits/pthreadtypes.h b/sysdeps/riscv/nptl/bits/pthreadtypes.h
-new file mode 100644
-index 0000000..ed8d1aa
---- /dev/null
-+++ b/sysdeps/riscv/nptl/bits/pthreadtypes.h
+diff -Nur original-glibc/sysdeps/riscv/nptl/bits/pthreadtypes.h glibc/sysdeps/riscv/nptl/bits/pthreadtypes.h
+--- original-glibc/sysdeps/riscv/nptl/bits/pthreadtypes.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/nptl/bits/pthreadtypes.h 2014-12-09 14:32:35.932301937 -0800
@@ -0,0 +1,241 @@
+/* Machine-specific pthread type layouts. RISC-V version.
+ Copyright (C) 2011-2014 Free Software Foundation, Inc.
@@ -3463,11 +3303,9 @@ index 0000000..ed8d1aa
+
+
+#endif /* bits/pthreadtypes.h */
-diff --git a/sysdeps/riscv/nptl/bits/semaphore.h b/sysdeps/riscv/nptl/bits/semaphore.h
-new file mode 100644
-index 0000000..28f8595
---- /dev/null
-+++ b/sysdeps/riscv/nptl/bits/semaphore.h
+diff -Nur original-glibc/sysdeps/riscv/nptl/bits/semaphore.h glibc/sysdeps/riscv/nptl/bits/semaphore.h
+--- original-glibc/sysdeps/riscv/nptl/bits/semaphore.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/nptl/bits/semaphore.h 2014-12-09 14:32:35.932301937 -0800
@@ -0,0 +1,37 @@
+/* Copyright (C) 2002, 2005, 2007 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
@@ -3506,19 +3344,15 @@ index 0000000..28f8595
+ char __size[__SIZEOF_SEM_T];
+ long int __align;
+} sem_t;
-diff --git a/sysdeps/riscv/nptl/clone.S b/sysdeps/riscv/nptl/clone.S
-new file mode 100644
-index 0000000..4106a34
---- /dev/null
-+++ b/sysdeps/riscv/nptl/clone.S
+diff -Nur original-glibc/sysdeps/riscv/nptl/clone.S glibc/sysdeps/riscv/nptl/clone.S
+--- original-glibc/sysdeps/riscv/nptl/clone.S 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/nptl/clone.S 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,2 @@
+#define RESET_PID
+#include <sysdeps/unix/sysv/linux/riscv/clone.S>
-diff --git a/sysdeps/riscv/nptl/lowlevellock.h b/sysdeps/riscv/nptl/lowlevellock.h
-new file mode 100644
-index 0000000..834bc2a
---- /dev/null
-+++ b/sysdeps/riscv/nptl/lowlevellock.h
+diff -Nur original-glibc/sysdeps/riscv/nptl/lowlevellock.h glibc/sysdeps/riscv/nptl/lowlevellock.h
+--- original-glibc/sysdeps/riscv/nptl/lowlevellock.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/nptl/lowlevellock.h 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,262 @@
+/* Copyright (C) 2011-2014 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
@@ -3782,21 +3616,46 @@ index 0000000..834bc2a
+ })
+
+#endif /* lowlevellock.h */
-diff --git a/sysdeps/riscv/nptl/nptl-sysdep.c b/sysdeps/riscv/nptl/nptl-sysdep.c
-new file mode 100644
-index 0000000..16c1736
---- /dev/null
-+++ b/sysdeps/riscv/nptl/nptl-sysdep.c
+diff -Nur original-glibc/sysdeps/riscv/nptl/Makefile glibc/sysdeps/riscv/nptl/Makefile
+--- original-glibc/sysdeps/riscv/nptl/Makefile 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/nptl/Makefile 2014-12-09 14:31:16.765856331 -0800
+@@ -0,0 +1,25 @@
++# Copyright (C) 2005 Free Software Foundation, Inc.
++# This file is part of the GNU C Library.
++#
++# The GNU C Library is free software; you can redistribute it and/or
++# modify it under the terms of the GNU Lesser General Public
++# License as published by the Free Software Foundation; either
++# version 2.1 of the License, or (at your option) any later version.
++#
++# The GNU C Library is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++# Lesser General Public License for more details.
++#
++# You should have received a copy of the GNU Lesser General Public
++# License along with the GNU C Library; if not, write to the Free
++# Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
++# 02111-1307 USA.
++
++ifeq ($(subdir),csu)
++gen-as-const-headers += tcb-offsets.sym
++endif
++
++ifeq ($(subdir),nptl)
++libpthread-sysdep_routines += nptl-sysdep
++endif
+diff -Nur original-glibc/sysdeps/riscv/nptl/nptl-sysdep.c glibc/sysdeps/riscv/nptl/nptl-sysdep.c
+--- original-glibc/sysdeps/riscv/nptl/nptl-sysdep.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/nptl/nptl-sysdep.c 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,2 @@
+/* Pull in __syscall_error. */
+#include <sysdep.c>
-diff --git a/sysdeps/riscv/nptl/pt-vfork.S b/sysdeps/riscv/nptl/pt-vfork.S
-new file mode 100644
-index 0000000..1fdbb26
---- /dev/null
-+++ b/sysdeps/riscv/nptl/pt-vfork.S
-@@ -0,0 +1,36 @@
-+/* Copyright (C) 2005, 2006 Free Software Foundation, Inc.
+diff -Nur original-glibc/sysdeps/riscv/nptl/pthreaddef.h glibc/sysdeps/riscv/nptl/pthreaddef.h
+--- original-glibc/sysdeps/riscv/nptl/pthreaddef.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/nptl/pthreaddef.h 2014-12-09 14:31:16.765856331 -0800
+@@ -0,0 +1,32 @@
++/* Copyright (C) 2011-2014 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
@@ -3814,29 +3673,23 @@ index 0000000..1fdbb26
+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307 USA. */
+
-+#include <tls.h>
-+#include "tcb-offsets.h"
++/* Default stack size. */
++#define ARCH_STACK_DEFAULT_SIZE (2 * 1024 * 1024)
+
-+/* Save the PID value. */
-+#define SAVE_PID \
-+ lw t0, PID_OFFSET(tp); /* Load the saved PID. */ \
-+ neg t0, t0; /* Negate it. */ \
-+ sw t0, PID_OFFSET(tp); /* Store the temporary PID. */
++/* Required stack pointer alignment at beginning. */
++#define STACK_ALIGN 16
+
-+/* Restore the old PID value in the parent. */
-+#define RESTORE_PID \
-+ beqz v0, 1f; /* If we are the parent... */ \
-+ lw t0, PID_OFFSET(tp); /* Load the saved PID. */ \
-+ neg t0, t0; /* Re-negate it. */ \
-+ sw t0, PID_OFFSET(tp); /* Restore the PID. */ \
-+1:
++/* Minimal stack size after allocating thread descriptor and guard size. */
++#define MINIMAL_REST_STACK 2048
+
-+#include <sysdeps/unix/sysv/linux/riscv/vfork.S>
-diff --git a/sysdeps/riscv/nptl/pthread_spin_destroy.c b/sysdeps/riscv/nptl/pthread_spin_destroy.c
-new file mode 100644
-index 0000000..e1eed80
---- /dev/null
-+++ b/sysdeps/riscv/nptl/pthread_spin_destroy.c
++/* Alignment requirement for TCB. */
++#define TCB_ALIGNMENT 16
++
++/* Location of current stack frame. */
++#define CURRENT_STACK_FRAME __builtin_frame_address (0)
+diff -Nur original-glibc/sysdeps/riscv/nptl/pthread_spin_destroy.c glibc/sysdeps/riscv/nptl/pthread_spin_destroy.c
+--- original-glibc/sysdeps/riscv/nptl/pthread_spin_destroy.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/nptl/pthread_spin_destroy.c 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,30 @@
+/* Copyright (C) 2002 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
@@ -3868,11 +3721,9 @@ index 0000000..e1eed80
+ return pthread_mutex_destroy(lock);
+}
+#endif
-diff --git a/sysdeps/riscv/nptl/pthread_spin_init.c b/sysdeps/riscv/nptl/pthread_spin_init.c
-new file mode 100644
-index 0000000..b85181a
---- /dev/null
-+++ b/sysdeps/riscv/nptl/pthread_spin_init.c
+diff -Nur original-glibc/sysdeps/riscv/nptl/pthread_spin_init.c glibc/sysdeps/riscv/nptl/pthread_spin_init.c
+--- original-glibc/sysdeps/riscv/nptl/pthread_spin_init.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/nptl/pthread_spin_init.c 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,30 @@
+/* pthread_spin_init -- initialize a spin lock. Generic version.
+ Copyright (C) 2003 Free Software Foundation, Inc.
@@ -3904,11 +3755,9 @@ index 0000000..b85181a
+ return pthread_mutex_init(lock, NULL);
+}
+#endif
-diff --git a/sysdeps/riscv/nptl/pthread_spin_lock.c b/sysdeps/riscv/nptl/pthread_spin_lock.c
-new file mode 100644
-index 0000000..0e8840b
---- /dev/null
-+++ b/sysdeps/riscv/nptl/pthread_spin_lock.c
+diff -Nur original-glibc/sysdeps/riscv/nptl/pthread_spin_lock.c glibc/sysdeps/riscv/nptl/pthread_spin_lock.c
+--- original-glibc/sysdeps/riscv/nptl/pthread_spin_lock.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/nptl/pthread_spin_lock.c 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,39 @@
+/* Copyright (C) 2005 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
@@ -3949,11 +3798,9 @@ index 0000000..0e8840b
+ return pthread_mutex_lock(lock);
+#endif
+}
-diff --git a/sysdeps/riscv/nptl/pthread_spin_trylock.c b/sysdeps/riscv/nptl/pthread_spin_trylock.c
-new file mode 100644
-index 0000000..b19ec5e
---- /dev/null
-+++ b/sysdeps/riscv/nptl/pthread_spin_trylock.c
+diff -Nur original-glibc/sysdeps/riscv/nptl/pthread_spin_trylock.c glibc/sysdeps/riscv/nptl/pthread_spin_trylock.c
+--- original-glibc/sysdeps/riscv/nptl/pthread_spin_trylock.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/nptl/pthread_spin_trylock.c 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,39 @@
+/* Copyright (C) 2005 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
@@ -3994,11 +3841,9 @@ index 0000000..b19ec5e
+ return pthread_mutex_trylock(lock);
+#endif
+}
-diff --git a/sysdeps/riscv/nptl/pthread_spin_unlock.c b/sysdeps/riscv/nptl/pthread_spin_unlock.c
-new file mode 100644
-index 0000000..133311c
---- /dev/null
-+++ b/sysdeps/riscv/nptl/pthread_spin_unlock.c
+diff -Nur original-glibc/sysdeps/riscv/nptl/pthread_spin_unlock.c glibc/sysdeps/riscv/nptl/pthread_spin_unlock.c
+--- original-glibc/sysdeps/riscv/nptl/pthread_spin_unlock.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/nptl/pthread_spin_unlock.c 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,33 @@
+/* pthread_spin_unlock -- unlock a spin lock. Generic version.
+ Copyright (C) 2003 Free Software Foundation, Inc.
@@ -4033,13 +3878,11 @@ index 0000000..133311c
+ return pthread_mutex_unlock(lock);
+#endif
+}
-diff --git a/sysdeps/riscv/nptl/pthreaddef.h b/sysdeps/riscv/nptl/pthreaddef.h
-new file mode 100644
-index 0000000..59927ed
---- /dev/null
-+++ b/sysdeps/riscv/nptl/pthreaddef.h
-@@ -0,0 +1,32 @@
-+/* Copyright (C) 2011-2014 Free Software Foundation, Inc.
+diff -Nur original-glibc/sysdeps/riscv/nptl/pt-vfork.S glibc/sysdeps/riscv/nptl/pt-vfork.S
+--- original-glibc/sysdeps/riscv/nptl/pt-vfork.S 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/nptl/pt-vfork.S 2014-12-09 14:38:38.665778707 -0800
+@@ -0,0 +1,36 @@
++/* Copyright (C) 2005, 2006 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
@@ -4057,26 +3900,28 @@ index 0000000..59927ed
+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307 USA. */
+
-+/* Default stack size. */
-+#define ARCH_STACK_DEFAULT_SIZE (2 * 1024 * 1024)
-+
-+/* Required stack pointer alignment at beginning. */
-+#define STACK_ALIGN 16
++#include <tls.h>
++#include "tcb-offsets.h"
+
-+/* Minimal stack size after allocating thread descriptor and guard size. */
-+#define MINIMAL_REST_STACK 2048
++/* Save the PID value. */
++#define SAVE_PID \
++ lw t0, PID_OFFSET(tp); /* Load the saved PID. */ \
++ neg t0, t0; /* Negate it. */ \
++ sw t0, PID_OFFSET(tp); /* Store the temporary PID. */
+
-+/* Alignment requirement for TCB. */
-+#define TCB_ALIGNMENT 16
++/* Restore the old PID value in the parent. */
++#define RESTORE_PID \
++ beqz a0, 1f; /* If we are the parent... */ \
++ lw t0, PID_OFFSET(tp); /* Load the saved PID. */ \
++ neg t0, t0; /* Re-negate it. */ \
++ sw t0, PID_OFFSET(tp); /* Restore the PID. */ \
++1:
+
-+/* Location of current stack frame. */
-+#define CURRENT_STACK_FRAME __builtin_frame_address (0)
-diff --git a/sysdeps/riscv/nptl/sysdep-cancel.h b/sysdeps/riscv/nptl/sysdep-cancel.h
-new file mode 100644
-index 0000000..3c1a396
---- /dev/null
-+++ b/sysdeps/riscv/nptl/sysdep-cancel.h
-@@ -0,0 +1,143 @@
++#include <sysdeps/unix/sysv/linux/riscv/vfork.S>
+diff -Nur original-glibc/sysdeps/riscv/nptl/sysdep-cancel.h glibc/sysdeps/riscv/nptl/sysdep-cancel.h
+--- original-glibc/sysdeps/riscv/nptl/sysdep-cancel.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/nptl/sysdep-cancel.h 2014-12-09 14:38:38.665778707 -0800
+@@ -0,0 +1,142 @@
+/* Copyright (C) 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
@@ -4116,14 +3961,14 @@ index 0000000..3c1a396
+ cfi_startproc; \
+ 99: j __syscall_error; \
+ ENTRY (name) \
-+ SINGLE_THREAD_P(v1); \
-+ bnez v1, L(pseudo_cancel); \
++ SINGLE_THREAD_P(t0); \
++ bnez t0, L(pseudo_cancel); \
+ .type __##syscall_name##_nocancel, @function; \
+ .globl __##syscall_name##_nocancel; \
+ __##syscall_name##_nocancel: \
-+ li v0, SYS_ify(syscall_name); \
++ li a7, SYS_ify(syscall_name); \
+ scall; \
-+ bltz v0, 99b; \
++ bltz a0, 99b; \
+ ret; \
+ .size __##syscall_name##_nocancel,.-__##syscall_name##_nocancel; \
+ L(pseudo_cancel): \
@@ -4133,16 +3978,16 @@ index 0000000..3c1a396
+ PUSHARGS_##args; /* save syscall args */ \
+ CENABLE; \
+ POPARGS_##args; /* restore syscall args */ \
-+ REG_S v0, STKOFF_SVMSK(sp); /* save mask */ \
-+ li v0, SYS_ify (syscall_name); \
++ REG_S a0, STKOFF_SVMSK(sp); /* save mask */ \
++ li a7, SYS_ify (syscall_name); \
+ scall; \
-+ REG_S v0, STKOFF_SC_V0(sp); /* save syscall result */ \
++ REG_S a0, STKOFF_A0(sp); /* save syscall result */ \
+ REG_L a0, STKOFF_SVMSK(sp); /* pass mask as arg1 */ \
+ CDISABLE; \
-+ REG_L v0, STKOFF_SC_V0(sp); /* restore syscall result */ \
++ REG_L a0, STKOFF_A0(sp); /* restore syscall result */ \
+ REG_L ra, STKOFF_RA(sp); /* restore return address */ \
+ RESTORESTK; \
-+ bltz v0, 99b; \
++ bltz a0, 99b; \
+ L(pseudo_end):
+
+
@@ -4179,7 +4024,6 @@ index 0000000..3c1a396
+# define STKOFF_A1 (STKOFF_A2 + SZREG) /* MT and 2 args. */
+# define STKOFF_SVMSK STKOFF_A1 /* Used if MT. */
+# define STKOFF_A0 (STKOFF_A1 + SZREG) /* MT and 1 arg. */
-+# define STKOFF_SC_V0 STKOFF_A0 /* Used if MT. */
+# define STKOFF_RA (STKOFF_A0 + SZREG) /* Used if MT. */
+
+# define STKSPACE (STKOFF_RA + SZREG)
@@ -4220,11 +4064,9 @@ index 0000000..3c1a396
+ __builtin_expect (THREAD_GETMEM (THREAD_SELF, \
+ header.multiple_threads) == 0, 1)
+#endif
-diff --git a/sysdeps/riscv/nptl/tcb-offsets.sym b/sysdeps/riscv/nptl/tcb-offsets.sym
-new file mode 100644
-index 0000000..e0e71dc
---- /dev/null
-+++ b/sysdeps/riscv/nptl/tcb-offsets.sym
+diff -Nur original-glibc/sysdeps/riscv/nptl/tcb-offsets.sym glibc/sysdeps/riscv/nptl/tcb-offsets.sym
+--- original-glibc/sysdeps/riscv/nptl/tcb-offsets.sym 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/nptl/tcb-offsets.sym 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,11 @@
+#include <sysdep.h>
+#include <tls.h>
@@ -4237,11 +4079,9 @@ index 0000000..e0e71dc
+MULTIPLE_THREADS_OFFSET thread_offsetof (header.multiple_threads)
+PID_OFFSET thread_offsetof (pid)
+TID_OFFSET thread_offsetof (tid)
-diff --git a/sysdeps/riscv/nptl/tls.h b/sysdeps/riscv/nptl/tls.h
-new file mode 100644
-index 0000000..2982f97
---- /dev/null
-+++ b/sysdeps/riscv/nptl/tls.h
+diff -Nur original-glibc/sysdeps/riscv/nptl/tls.h glibc/sysdeps/riscv/nptl/tls.h
+--- original-glibc/sysdeps/riscv/nptl/tls.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/nptl/tls.h 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,159 @@
+/* Definition for thread-local data handling. NPTL/RISC-V version.
+ Copyright (C) 2011-2014 Free Software Foundation, Inc.
@@ -4402,11 +4242,9 @@ index 0000000..2982f97
+#endif /* __ASSEMBLER__ */
+
+#endif /* tls.h */
-diff --git a/sysdeps/riscv/nptl/vfork.S b/sysdeps/riscv/nptl/vfork.S
-new file mode 100644
-index 0000000..7fabe8a
---- /dev/null
-+++ b/sysdeps/riscv/nptl/vfork.S
+diff -Nur original-glibc/sysdeps/riscv/nptl/vfork.S glibc/sysdeps/riscv/nptl/vfork.S
+--- original-glibc/sysdeps/riscv/nptl/vfork.S 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/nptl/vfork.S 2014-12-09 14:38:38.665778707 -0800
@@ -0,0 +1,41 @@
+/* Copyright (C) 2005, 2006 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
@@ -4439,7 +4277,7 @@ index 0000000..7fabe8a
+
+/* Restore the old PID value in the parent. */
+#define RESTORE_PID \
-+ beqz v0, 1f; /* If we are the parent... */ \
++ beqz a0, 1f; /* If we are the parent... */ \
+ lw t0, PID_OFFSET(tp); /* Load the saved PID. */ \
+ neg t0, t0; /* Re-negate it. */ \
+ li t1, 0x80000000; /* Load 0x80000000... */ \
@@ -4449,12 +4287,10 @@ index 0000000..7fabe8a
+1:
+
+#include <sysdeps/unix/sysv/linux/riscv/vfork.S>
-diff --git a/sysdeps/riscv/preconfigure b/sysdeps/riscv/preconfigure
-new file mode 100644
-index 0000000..2a5a109
---- /dev/null
-+++ b/sysdeps/riscv/preconfigure
-@@ -0,0 +1,21 @@
+diff -Nur original-glibc/sysdeps/riscv/preconfigure glibc/sysdeps/riscv/preconfigure
+--- original-glibc/sysdeps/riscv/preconfigure 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/preconfigure 2014-12-09 14:32:35.932301937 -0800
+@@ -0,0 +1,20 @@
+case "$CC $CFLAGS $CPPFLAGS " in
+*" -m32 "*) riscv_cc_abi=32 ;;
+*" -m64 "*) riscv_cc_abi=64 ;;
@@ -4466,9 +4302,8 @@ index 0000000..2a5a109
+*) riscv_config_abi=$riscv_cc_abi ;;
+esac
+case $riscv_config_abi in
-+default) base_machine=riscv machine=riscv/rv64 ;;
-+32) base_machine=riscv machine=riscv/rv32 ;;
-+64) base_machine=riscv machine=riscv/rv64 ;;
++default) machine=riscv/rv64 ;;
++32) machine=riscv/rv32 ;;
+esac
+machine=$machine/$config_machine
+if test $riscv_config_abi != $riscv_cc_abi; then
@@ -4476,127 +4311,22 @@ index 0000000..2a5a109
+ # set this in case configure tests depend on it.
+ CPPFLAGS="$CPPFLAGS -m$riscv_config_abi"
+fi
-diff --git a/sysdeps/riscv/rv32/Implies b/sysdeps/riscv/rv32/Implies
-new file mode 100644
-index 0000000..b2313e9
---- /dev/null
-+++ b/sysdeps/riscv/rv32/Implies
+diff -Nur original-glibc/sysdeps/riscv/rv32/Implies glibc/sysdeps/riscv/rv32/Implies
+--- original-glibc/sysdeps/riscv/rv32/Implies 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/rv32/Implies 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,2 @@
+riscv
+wordsize-32
-diff --git a/sysdeps/riscv/rv32/Makefile b/sysdeps/riscv/rv32/Makefile
-new file mode 100644
-index 0000000..f9c69e3
---- /dev/null
-+++ b/sysdeps/riscv/rv32/Makefile
+diff -Nur original-glibc/sysdeps/riscv/rv32/Makefile glibc/sysdeps/riscv/rv32/Makefile
+--- original-glibc/sysdeps/riscv/rv32/Makefile 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/rv32/Makefile 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,3 @@
+ifeq ($(filter -m32,$(CC)),)
+CC += -m32
+endif
-diff --git a/sysdeps/riscv/rv32/bits/wordsize.h b/sysdeps/riscv/rv32/bits/wordsize.h
-new file mode 100644
-index 0000000..24a8e7d
---- /dev/null
-+++ b/sysdeps/riscv/rv32/bits/wordsize.h
-@@ -0,0 +1,25 @@
-+/* Copyright (C) 2002, 2003 Free Software Foundation, Inc.
-+ This file is part of the GNU C Library.
-+
-+ The GNU C Library is free software; you can redistribute it and/or
-+ modify it under the terms of the GNU Lesser General Public
-+ License as published by the Free Software Foundation; either
-+ version 2.1 of the License, or (at your option) any later version.
-+
-+ The GNU C Library is distributed in the hope that it will be useful,
-+ but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ Lesser General Public License for more details.
-+
-+ You should have received a copy of the GNU Lesser General Public
-+ License along with the GNU C Library; if not, write to the Free
-+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
-+ 02111-1307 USA. */
-+
-+#define __WORDSIZE 32
-+
-+#ifdef _RISCV_SIM
-+# if _RISCV_SIM == _ABI64
-+# define __WORDSIZE_COMPAT32 1
-+# endif
-+#endif
-diff --git a/sysdeps/riscv/rv64/Implies b/sysdeps/riscv/rv64/Implies
-new file mode 100644
-index 0000000..fae63bc
---- /dev/null
-+++ b/sysdeps/riscv/rv64/Implies
-@@ -0,0 +1,6 @@
-+ieee754/flt-32
-+ieee754/dbl-64
-+riscv/rv64/soft-fp
-+riscv/rv64
-+riscv
-+wordsize-64
-diff --git a/sysdeps/riscv/rv64/Makefile b/sysdeps/riscv/rv64/Makefile
-new file mode 100644
-index 0000000..26b6a49
---- /dev/null
-+++ b/sysdeps/riscv/rv64/Makefile
-@@ -0,0 +1,6 @@
-+# Link libc.so at its likely load address for faster dynamic linking
-+LDLIBS-c.so += -Wl,--section-start=.dynamic=0x40100270
-+
-+ifeq ($(filter -m64,$(CC)),)
-+CC += -m64
-+endif
-diff --git a/sysdeps/riscv/rv64/Versions b/sysdeps/riscv/rv64/Versions
-new file mode 100644
-index 0000000..253a65f
---- /dev/null
-+++ b/sysdeps/riscv/rv64/Versions
-@@ -0,0 +1,7 @@
-+libm {
-+ GLIBC_2.1 {
-+ # A generic bug got this omitted from other configurations' version
-+ # sets, but we always had it.
-+ exp2l;
-+ }
-+}
-diff --git a/sysdeps/riscv/rv64/bits/wordsize.h b/sysdeps/riscv/rv64/bits/wordsize.h
-new file mode 100644
-index 0000000..df16738
---- /dev/null
-+++ b/sysdeps/riscv/rv64/bits/wordsize.h
-@@ -0,0 +1,25 @@
-+/* Copyright (C) 2002, 2003 Free Software Foundation, Inc.
-+ This file is part of the GNU C Library.
-+
-+ The GNU C Library is free software; you can redistribute it and/or
-+ modify it under the terms of the GNU Lesser General Public
-+ License as published by the Free Software Foundation; either
-+ version 2.1 of the License, or (at your option) any later version.
-+
-+ The GNU C Library is distributed in the hope that it will be useful,
-+ but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ Lesser General Public License for more details.
-+
-+ You should have received a copy of the GNU Lesser General Public
-+ License along with the GNU C Library; if not, write to the Free
-+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
-+ 02111-1307 USA. */
-+
-+#define __WORDSIZE 64
-+
-+#ifdef _RISCV_SIM
-+# if _RISCV_SIM == _ABI64
-+# define __WORDSIZE_COMPAT32 1
-+# endif
-+#endif
-diff --git a/sysdeps/riscv/rv64/gmp-mparam.h b/sysdeps/riscv/rv64/gmp-mparam.h
-new file mode 100644
-index 0000000..7666137
---- /dev/null
-+++ b/sysdeps/riscv/rv64/gmp-mparam.h
+diff -Nur original-glibc/sysdeps/riscv/rv64/gmp-mparam.h glibc/sysdeps/riscv/rv64/gmp-mparam.h
+--- original-glibc/sysdeps/riscv/rv64/gmp-mparam.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/rv64/gmp-mparam.h 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,31 @@
+/* gmp-mparam.h -- Compiler/machine parameter header file.
+
@@ -4629,20 +4359,36 @@ index 0000000..7666137
+#define BITS_PER_INT 32
+#define BITS_PER_SHORTINT 16
+#define BITS_PER_CHAR 8
-diff --git a/sysdeps/riscv/rv64/soft-fp/Makefile b/sysdeps/riscv/rv64/soft-fp/Makefile
-new file mode 100644
-index 0000000..ada13e8
---- /dev/null
-+++ b/sysdeps/riscv/rv64/soft-fp/Makefile
+diff -Nur original-glibc/sysdeps/riscv/rv64/Implies glibc/sysdeps/riscv/rv64/Implies
+--- original-glibc/sysdeps/riscv/rv64/Implies 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/rv64/Implies 2014-12-09 14:31:16.765856331 -0800
+@@ -0,0 +1,6 @@
++ieee754/flt-32
++ieee754/dbl-64
++riscv/rv64/soft-fp
++riscv/rv64
++riscv
++wordsize-64
+diff -Nur original-glibc/sysdeps/riscv/rv64/Makefile glibc/sysdeps/riscv/rv64/Makefile
+--- original-glibc/sysdeps/riscv/rv64/Makefile 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/rv64/Makefile 2014-12-09 14:31:16.765856331 -0800
+@@ -0,0 +1,6 @@
++# Link libc.so at its likely load address for faster dynamic linking
++LDLIBS-c.so += -Wl,--section-start=.dynamic=0x40100270
++
++ifeq ($(filter -m64,$(CC)),)
++CC += -m64
++endif
+diff -Nur original-glibc/sysdeps/riscv/rv64/soft-fp/Makefile glibc/sysdeps/riscv/rv64/soft-fp/Makefile
+--- original-glibc/sysdeps/riscv/rv64/soft-fp/Makefile 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/rv64/soft-fp/Makefile 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,3 @@
+ifeq ($(subdir),math)
+CPPFLAGS += -I../soft-fp
+endif
-diff --git a/sysdeps/riscv/rv64/soft-fp/sfp-machine.h b/sysdeps/riscv/rv64/soft-fp/sfp-machine.h
-new file mode 100644
-index 0000000..0bf2776
---- /dev/null
-+++ b/sysdeps/riscv/rv64/soft-fp/sfp-machine.h
+diff -Nur original-glibc/sysdeps/riscv/rv64/soft-fp/sfp-machine.h glibc/sysdeps/riscv/rv64/soft-fp/sfp-machine.h
+--- original-glibc/sysdeps/riscv/rv64/soft-fp/sfp-machine.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/rv64/soft-fp/sfp-machine.h 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,74 @@
+#include <fenv.h>
+#include <fpu_control.h>
@@ -4718,12 +4464,21 @@ index 0000000..0bf2776
+#else
+#define FP_INIT_ROUNDMODE _fcw = 0 /* no exceptions; FP_RND_NEAREST */
+#endif
-diff --git a/sysdeps/riscv/setjmp.S b/sysdeps/riscv/setjmp.S
-new file mode 100644
-index 0000000..07559c5
---- /dev/null
-+++ b/sysdeps/riscv/setjmp.S
-@@ -0,0 +1,83 @@
+diff -Nur original-glibc/sysdeps/riscv/rv64/Versions glibc/sysdeps/riscv/rv64/Versions
+--- original-glibc/sysdeps/riscv/rv64/Versions 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/rv64/Versions 2014-12-09 14:31:16.765856331 -0800
+@@ -0,0 +1,7 @@
++libm {
++ GLIBC_2.1 {
++ # A generic bug got this omitted from other configurations' version
++ # sets, but we always had it.
++ exp2l;
++ }
++}
+diff -Nur original-glibc/sysdeps/riscv/setjmp.S glibc/sysdeps/riscv/setjmp.S
+--- original-glibc/sysdeps/riscv/setjmp.S 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/setjmp.S 2014-12-09 14:38:38.665778707 -0800
+@@ -0,0 +1,79 @@
+/* Copyright (C) 1996, 1997, 2000, 2002, 2003, 2004
+ Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
@@ -4786,17 +4541,13 @@ index 0000000..07559c5
+ fsd fs9, 16*SZREG+ 9*8(a0)
+ fsd fs10,16*SZREG+10*8(a0)
+ fsd fs11,16*SZREG+11*8(a0)
-+ fsd fs12,16*SZREG+12*8(a0)
-+ fsd fs13,16*SZREG+13*8(a0)
-+ fsd fs14,16*SZREG+14*8(a0)
-+ fsd fs15,16*SZREG+15*8(a0)
+
+ REG_S a3, 15*SZREG(a0)
+#endif
+
+#if defined NOT_IN_libc && defined IS_IN_rtld
+ /* In ld.so we never save the signal mask. */
-+ li v0, 0
++ li a0, 0
+ ret
+#else
+ /* Make a tail call to __sigjmp_save; it takes the same args. */
@@ -4807,11 +4558,9 @@ index 0000000..07559c5
+END(__sigsetjmp)
+
+weak_alias(_setjmp, __GI__setjmp)
-diff --git a/sysdeps/riscv/sgidefs.h b/sysdeps/riscv/sgidefs.h
-new file mode 100644
-index 0000000..34a6e61
---- /dev/null
-+++ b/sysdeps/riscv/sgidefs.h
+diff -Nur original-glibc/sysdeps/riscv/sgidefs.h glibc/sysdeps/riscv/sgidefs.h
+--- original-glibc/sysdeps/riscv/sgidefs.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/sgidefs.h 2014-12-09 14:32:35.932301937 -0800
@@ -0,0 +1,41 @@
+/* Copyright (C) 1996, 1997, 1998, 2003, 2004 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
@@ -4854,11 +4603,9 @@ index 0000000..34a6e61
+#define _RISCV_SIM_ABI64 _ABI64
+
+#endif /* sgidefs.h */
-diff --git a/sysdeps/riscv/soft-fp/sfp-machine.h b/sysdeps/riscv/soft-fp/sfp-machine.h
-new file mode 100644
-index 0000000..3b2a40f
---- /dev/null
-+++ b/sysdeps/riscv/soft-fp/sfp-machine.h
+diff -Nur original-glibc/sysdeps/riscv/soft-fp/sfp-machine.h glibc/sysdeps/riscv/soft-fp/sfp-machine.h
+--- original-glibc/sysdeps/riscv/soft-fp/sfp-machine.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/soft-fp/sfp-machine.h 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,47 @@
+#define _FP_W_TYPE_SIZE 32
+#define _FP_W_TYPE unsigned long
@@ -4907,11 +4654,9 @@ index 0000000..3b2a40f
+#define FP_EX_OVERFLOW (1 << 2)
+#define FP_EX_UNDERFLOW (1 << 1)
+#define FP_EX_INEXACT (1 << 0)
-diff --git a/sysdeps/riscv/stackinfo.h b/sysdeps/riscv/stackinfo.h
-new file mode 100644
-index 0000000..7a5e3e0
---- /dev/null
-+++ b/sysdeps/riscv/stackinfo.h
+diff -Nur original-glibc/sysdeps/riscv/stackinfo.h glibc/sysdeps/riscv/stackinfo.h
+--- original-glibc/sysdeps/riscv/stackinfo.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/stackinfo.h 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,34 @@
+/* Copyright (C) 2000, 2010 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
@@ -4947,12 +4692,10 @@ index 0000000..7a5e3e0
+#define DEFAULT_STACK_PERMS (PF_R|PF_W|PF_X)
+
+#endif /* stackinfo.h */
-diff --git a/sysdeps/riscv/start.S b/sysdeps/riscv/start.S
-new file mode 100644
-index 0000000..95f2406
---- /dev/null
-+++ b/sysdeps/riscv/start.S
-@@ -0,0 +1,98 @@
+diff -Nur original-glibc/sysdeps/riscv/start.S glibc/sysdeps/riscv/start.S
+--- original-glibc/sysdeps/riscv/start.S 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/start.S 2014-12-09 14:38:38.665778707 -0800
+@@ -0,0 +1,66 @@
+/* Startup code compliant to the ELF Mips ABI.
+ Copyright (C) 1995, 1997, 2000, 2001, 2002, 2003, 2004
+ Free Software Foundation, Inc.
@@ -4992,71 +4735,37 @@ index 0000000..95f2406
+
+#define __ASSEMBLY__ 1
+#include <entry.h>
-+#include <sgidefs.h>
++#include <sysdep.h>
+#include <sys/asm.h>
+
-+#ifndef ENTRY_POINT
-+#error ENTRY_POINT needs to be defined for start.S on MIPS/ELF.
-+#endif
-+
-+/* This is the canonical entry point, usually the first thing in the text
-+ segment. The SVR4/Mips ABI (pages 3-31, 3-32) says that when the entry
-+ point runs, most registers' values are unspecified, except for:
-+
-+ v0 ($2) Contains a function pointer to be registered with `atexit'.
-+ This is how the dynamic linker arranges to have DT_FINI
-+ functions called for shared libraries that have been loaded
-+ before this code runs.
-+
-+ sp ($29) The stack contains the arguments and environment:
-+ 0(%esp) argc
-+ 4(%esp) argv[0]
-+ ...
-+ (4*argc)(%esp) NULL
-+ (4*(argc+1))(%esp) envp[0]
-+ ...
-+ NULL
-+ ra ($31) The return address register is set to zero so that programs
-+ that search backword through stack frames recognize the last
-+ stack frame.
-+*/
-+
++/* The entry point's job is to call __libc_start_main. Per the ABI,
++ a0 contains the address of a function to be passed to atexit.
++ __libc_start_main wants this in a5. */
+
-+/* We need to call:
-+ __libc_start_main (int (*main) (int, char **, char **), int argc,
-+ char **argv, void (*init) (void), void (*fini) (void),
-+ void (*rtld_fini) (void), void *stack_end)
-+*/
-+
-+ .text
-+ .globl ENTRY_POINT
-+ .type ENTRY_POINT,@function
-+ENTRY_POINT:
++ENTRY(ENTRY_POINT)
+ lla gp, _gp
++ move a5, a0 /* rtld_fini */
+ lla a0, main
+ REG_L a1, 0(sp) /* argc */
+ addi a2, sp, SZREG /* argv */
+ andi sp, sp, ALMASK /* Align stack. */
+ lla a3, __libc_csu_init
+ lla a4, __libc_csu_fini
-+ move a5, v0 /* rtld_fini */
+ move a6, sp /* stack_end */
+
+ jump __libc_start_main@
++END(ENTRY_POINT)
+
+/* Define a symbol for the first piece of initialized data. */
+ .data
+ .globl __data_start
+__data_start:
-+ .long 0
+ .weak data_start
+ data_start = __data_start
-diff --git a/sysdeps/riscv/strcmp.S b/sysdeps/riscv/strcmp.S
-new file mode 100644
-index 0000000..2db21ea
---- /dev/null
-+++ b/sysdeps/riscv/strcmp.S
-@@ -0,0 +1,129 @@
+diff -Nur original-glibc/sysdeps/riscv/strcmp.S glibc/sysdeps/riscv/strcmp.S
+--- original-glibc/sysdeps/riscv/strcmp.S 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/strcmp.S 2014-12-09 14:38:38.665778707 -0800
+@@ -0,0 +1,127 @@
+# Artisanally coded in California by A. Shell Waterman
+
+#include <sysdep.h>
@@ -5067,11 +4776,10 @@ index 0000000..2db21ea
+#endif
+
+ENTRY(strcmp)
-+ or v1, a0, a1
++ or a4, a0, a1
+ li t2, -1
-+ and v1, v1, SZREG-1
-+ li v0, 0
-+ bnez v1, .Lmisaligned
++ and a4, a4, SZREG-1
++ bnez a4, .Lmisaligned
+
+#if SZREG == 4
+ li t3, 0x7f7f7f7f
@@ -5108,16 +4816,16 @@ index 0000000..2db21ea
+ .Lnull0:
+ .endif
+ bne a2, a3, .Lmisaligned
++ li a0, 0
+ ret
+ .endif
+ .endm
+
+.Lloop:
+ # examine full words
-+ check_one_word 0 4
-+ check_one_word 1 4
-+ check_one_word 2 4
-+ check_one_word 3 4
++ check_one_word 0 3
++ check_one_word 1 3
++ check_one_word 2 3
+ # backwards branch to .Lloop contained above
+
+.Lmismatch:
@@ -5136,42 +4844,41 @@ index 0000000..2db21ea
+
+ srl a0, a2, 8*SZREG-16
+ srl a1, a3, 8*SZREG-16
-+ sub v0, a0, a1
-+ and v1, v0, 0xff
-+ bnez v1, 1f
++ sub a0, a0, a1
++ and a4, a0, 0xff
++ bnez a4, 1f
+ ret
+
+.Lmismatch_upper:
+ srl a0, a0, 8*SZREG-16
+ srl a1, a1, 8*SZREG-16
-+ sub v0, a0, a1
-+ and v1, v0, 0xff
-+ bnez v1, 1f
++ sub a2, a0, a1
++ and a3, a2, 0xff
++ bnez a3, 1f
+ ret
+
+1:and a0, a0, 0xff
+ and a1, a1, 0xff
-+ sub v0, a0, a1
++ sub a0, a0, a1
+ ret
+
+.Lmisaligned:
+ # misaligned
-+ lbu v0, 0(a0)
-+ lbu v1, 0(a1)
++ lbu a2, 0(a0)
++ lbu a3, 0(a1)
+ add a0, a0, 1
+ add a1, a1, 1
-+ bne v0, v1, 1f
-+ bnez v0, .Lmisaligned
++ bne a2, a3, 1f
++ bnez a2, .Lmisaligned
+
+1:
-+ sub v0, v0, v1
++ sub a0, a2, a3
+ ret
+
+ # cases in which a null byte was detected
-+ foundnull 0, 4
-+ foundnull 1, 4
-+ foundnull 2, 4
-+ foundnull 3, 4
++ foundnull 0, 3
++ foundnull 1, 3
++ foundnull 2, 3
+
+END(strcmp)
+
@@ -5186,11 +4893,9 @@ index 0000000..2db21ea
+.align 3
+mask: .8byte 0x7f7f7f7f7f7f7f7f
+#endif
-diff --git a/sysdeps/riscv/strcpy.c b/sysdeps/riscv/strcpy.c
-new file mode 100644
-index 0000000..c01c506
---- /dev/null
-+++ b/sysdeps/riscv/strcpy.c
+diff -Nur original-glibc/sysdeps/riscv/strcpy.c glibc/sysdeps/riscv/strcpy.c
+--- original-glibc/sysdeps/riscv/strcpy.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/strcpy.c 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,54 @@
+#include <string.h>
+#include <stdint.h>
@@ -5246,11 +4951,9 @@ index 0000000..c01c506
+ return dst0;
+}
+libc_hidden_def(strcpy)
-diff --git a/sysdeps/riscv/strlen.c b/sysdeps/riscv/strlen.c
-new file mode 100644
-index 0000000..2630f46
---- /dev/null
-+++ b/sysdeps/riscv/strlen.c
+diff -Nur original-glibc/sysdeps/riscv/strlen.c glibc/sysdeps/riscv/strlen.c
+--- original-glibc/sysdeps/riscv/strlen.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/strlen.c 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,38 @@
+#include <string.h>
+#include <stdint.h>
@@ -5290,11 +4993,9 @@ index 0000000..2630f46
+ return ret + 7 - sl;
+}
+libc_hidden_def(strlen)
-diff --git a/sysdeps/riscv/sys/asm.h b/sysdeps/riscv/sys/asm.h
-new file mode 100644
-index 0000000..fc30999
---- /dev/null
-+++ b/sysdeps/riscv/sys/asm.h
+diff -Nur original-glibc/sysdeps/riscv/sys/asm.h glibc/sysdeps/riscv/sys/asm.h
+--- original-glibc/sysdeps/riscv/sys/asm.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/sys/asm.h 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,69 @@
+/* copyright (c) 1997, 1998, 2002, 2003, 2004, 2005
+ Free Software Foundation, Inc.
@@ -5365,11 +5066,9 @@ index 0000000..fc30999
+#define ALMASK ~15
+
+#endif /* sys/asm.h */
-diff --git a/sysdeps/riscv/tcb-offsets.sym b/sysdeps/riscv/tcb-offsets.sym
-new file mode 100644
-index 0000000..e0e71dc
---- /dev/null
-+++ b/sysdeps/riscv/tcb-offsets.sym
+diff -Nur original-glibc/sysdeps/riscv/tcb-offsets.sym glibc/sysdeps/riscv/tcb-offsets.sym
+--- original-glibc/sysdeps/riscv/tcb-offsets.sym 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/tcb-offsets.sym 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,11 @@
+#include <sysdep.h>
+#include <tls.h>
@@ -5382,11 +5081,9 @@ index 0000000..e0e71dc
+MULTIPLE_THREADS_OFFSET thread_offsetof (header.multiple_threads)
+PID_OFFSET thread_offsetof (pid)
+TID_OFFSET thread_offsetof (tid)
-diff --git a/sysdeps/riscv/tst-audit.h b/sysdeps/riscv/tst-audit.h
-new file mode 100644
-index 0000000..ac011fc
---- /dev/null
-+++ b/sysdeps/riscv/tst-audit.h
+diff -Nur original-glibc/sysdeps/riscv/tst-audit.h glibc/sysdeps/riscv/tst-audit.h
+--- original-glibc/sysdeps/riscv/tst-audit.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/tst-audit.h 2014-12-09 14:32:35.932301937 -0800
@@ -0,0 +1,33 @@
+/* Definitions for testing PLT entry/exit auditing. ARM version.
+
@@ -5421,19 +5118,24 @@ index 0000000..ac011fc
+#define La_regs La_mips_64_regs
+#define La_retval La_mips_64_retval
+#define int_retval lrv_v0
-diff --git a/sysdeps/unix/riscv/rt-sysdep.c b/sysdeps/unix/riscv/rt-sysdep.c
-new file mode 100644
-index 0000000..3ff5595
---- /dev/null
-+++ b/sysdeps/unix/riscv/rt-sysdep.c
+diff -Nur original-glibc/sysdeps/riscv/Versions glibc/sysdeps/riscv/Versions
+--- original-glibc/sysdeps/riscv/Versions 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/riscv/Versions 2014-12-09 14:31:16.755856778 -0800
+@@ -0,0 +1,5 @@
++libc {
++ GLIBC_2.14 {
++ __memcpy_g;
++ }
++}
+diff -Nur original-glibc/sysdeps/unix/riscv/rt-sysdep.c glibc/sysdeps/unix/riscv/rt-sysdep.c
+--- original-glibc/sysdeps/unix/riscv/rt-sysdep.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/riscv/rt-sysdep.c 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1 @@
+#include <sysdep.c>
-diff --git a/sysdeps/unix/riscv/sysdep.c b/sysdeps/unix/riscv/sysdep.c
-new file mode 100644
-index 0000000..308eced
---- /dev/null
-+++ b/sysdeps/unix/riscv/sysdep.c
-@@ -0,0 +1,43 @@
+diff -Nur original-glibc/sysdeps/unix/riscv/sysdep.c glibc/sysdeps/unix/riscv/sysdep.c
+--- original-glibc/sysdeps/unix/riscv/sysdep.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/riscv/sysdep.c 2014-12-09 14:38:38.665778707 -0800
+@@ -0,0 +1,41 @@
+/* Copyright (C) 1992, 1993, 1994, 1997, 1998, 1999, 2000, 2002, 2003
+ Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
@@ -5457,12 +5159,10 @@ index 0000000..308eced
+#include <sysdep.h>
+#include <errno.h>
+
-+long __syscall_error()
++long __syscall_error(long a0)
+{
-+ register long v0 asm("v0");
-+
-+ /* Referencing errno may call a function, clobbering v0. */
-+ long errno_val = -v0;
++ /* Referencing errno may call a function, clobbering a0. */
++ long errno_val = -a0;
+
+#if defined (EWOULDBLOCK_sys) && EWOULDBLOCK_sys != EAGAIN
+ /* We translate the system's EWOULDBLOCK error into EAGAIN.
@@ -5477,11 +5177,9 @@ index 0000000..308eced
+
+ return -1;
+}
-diff --git a/sysdeps/unix/riscv/sysdep.h b/sysdeps/unix/riscv/sysdep.h
-new file mode 100644
-index 0000000..910afd5
---- /dev/null
-+++ b/sysdeps/unix/riscv/sysdep.h
+diff -Nur original-glibc/sysdeps/unix/riscv/sysdep.h glibc/sysdeps/unix/riscv/sysdep.h
+--- original-glibc/sysdeps/unix/riscv/sysdep.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/riscv/sysdep.h 2014-12-09 14:38:38.665778707 -0800
@@ -0,0 +1,72 @@
+/* Copyright (C) 1992, 1995, 1997, 1999, 2000, 2002, 2003, 2004
+ Free Software Foundation, Inc.
@@ -5523,7 +5221,7 @@ index 0000000..910afd5
+#define PSEUDO_NOERRNO(name, syscall_name, args) \
+ .align 2; \
+ ENTRY(name) \
-+ li v0, SYS_ify(syscall_name); \
++ li a7, SYS_ify(syscall_name); \
+ scall
+
+#undef PSEUDO_END_NOERRNO
@@ -5539,8 +5237,8 @@ index 0000000..910afd5
+
+#define ret_ERRVAL ret
+
-+#define r0 v0
-+#define r1 v1
++#define r0 a0
++#define r1 a1
+#define MOVE(x,y) move y , x
+
+#define L(label) .L ## label
@@ -5549,152 +5247,20 @@ index 0000000..910afd5
+ .align 2; \
+ 99: j __syscall_error; \
+ ENTRY(name) \
-+ li v0, SYS_ify(syscall_name); \
++ li a7, SYS_ify(syscall_name); \
+ scall; \
-+ bltz v0, 99b; \
++ bltz a0, 99b; \
+L(syse1):
+
+#endif
-diff --git a/sysdeps/unix/sysv/linux/riscv/Implies b/sysdeps/unix/sysv/linux/riscv/Implies
-new file mode 100644
-index 0000000..0f2fab4
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/Implies
-@@ -0,0 +1,5 @@
-+unix/sysv/linux/generic
-+riscv/nptl
-+
-+# This needs to change to support rv32
-+unix/sysv/linux/riscv/rv64
-diff --git a/sysdeps/unix/sysv/linux/riscv/Makefile b/sysdeps/unix/sysv/linux/riscv/Makefile
-new file mode 100644
-index 0000000..396053f
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/Makefile
-@@ -0,0 +1,13 @@
-+ifeq ($(subdir),elf)
-+ifeq ($(build-shared),yes)
-+# This is needed for DSO loading from static binaries.
-+sysdep-dl-routines += dl-static
-+sysdep_routines += dl-static
-+sysdep-rtld-routines += dl-static
-+endif
-+endif
-+
-+ifeq ($(subdir),stdlib)
-+sysdep_routines += __start_context
-+gen-as-const-headers += ucontext_i.sym
-+endif
-diff --git a/sysdeps/unix/sysv/linux/riscv/Versions b/sysdeps/unix/sysv/linux/riscv/Versions
-new file mode 100644
-index 0000000..a56322a
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/Versions
-@@ -0,0 +1,40 @@
-+ld {
-+ GLIBC_PRIVATE {
-+ # used for loading by static libraries
-+ _dl_var_init;
-+ }
-+}
-+libc {
-+ # The comment lines with "#errlist-compat" are magic; see errlist-compat.awk.
-+ # When you get an error from errlist-compat.awk, you need to add a new
-+ # version here. Don't do this blindly, since this means changing the ABI
-+ # for all GNU/Linux configurations.
-+
-+ GLIBC_2.0 {
-+ #errlist-compat 123
-+ _sys_errlist; sys_errlist; _sys_nerr; sys_nerr;
-+
-+ # Exception handling support functions from libgcc
-+ __register_frame; __register_frame_table; __deregister_frame;
-+ __frame_state_for; __register_frame_info_table;
-+
-+ # Needed by gcc:
-+ _flush_cache;
-+
-+ # c*
-+ cachectl; cacheflush;
-+
-+ # s*
-+ sysmips;
-+ }
-+ GLIBC_2.2 {
-+ #errlist-compat 1134
-+ _sys_errlist; sys_errlist; _sys_nerr; sys_nerr;
-+
-+ # _*
-+ _test_and_set;
-+ }
-+ GLIBC_2.11 {
-+ fallocate64;
-+ }
-+}
-diff --git a/sysdeps/unix/sysv/linux/riscv/____longjmp_chk.S b/sysdeps/unix/sysv/linux/riscv/____longjmp_chk.S
-new file mode 100644
-index 0000000..e903c7e
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/____longjmp_chk.S
-@@ -0,0 +1,2 @@
-+#define __longjmp ____longjmp_chk
-+#include <__longjmp.S>
-diff --git a/sysdeps/unix/sysv/linux/riscv/__start_context.S b/sysdeps/unix/sysv/linux/riscv/__start_context.S
-new file mode 100644
-index 0000000..7408289
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/__start_context.S
-@@ -0,0 +1,38 @@
-+/* Modify saved context.
-+ Copyright (C) 2009 Free Software Foundation, Inc.
-+ This file is part of the GNU C Library.
-+ Contributed by Maciej W. Rozycki <macro@codesourcery.com>.
-+
-+ The GNU C Library is free software; you can redistribute it and/or
-+ modify it under the terms of the GNU Lesser General Public
-+ License as published by the Free Software Foundation; either
-+ version 2.1 of the License, or (at your option) any later version.
-+
-+ The GNU C Library is distributed in the hope that it will be useful,
-+ but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ Lesser General Public License for more details.
-+
-+ You should have received a copy of the GNU Lesser General Public
-+ License along with the GNU C Library; if not, write to the Free
-+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
-+ 02110-1301, USA. */
-+
-+#include <sysdep.h>
-+#include <sys/asm.h>
-+
-+#include "ucontext_i.h"
-+
-+ .text
-+LEAF (__start_context)
-+ move a0, zero
-+ beqz s0, 1f
-+
-+ /* setcontext (ucp) */
-+ move a0, s0
-+ jal __setcontext
-+ move a0, v0
-+
-+1: jal HIDDEN_JUMPTARGET (exit)
-+
-+PSEUDO_END (__start_context)
-diff --git a/sysdeps/unix/sysv/linux/riscv/arch-fork.h b/sysdeps/unix/sysv/linux/riscv/arch-fork.h
-new file mode 100644
-index 0000000..5f94537
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/arch-fork.h
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/arch-fork.h glibc/sysdeps/unix/sysv/linux/riscv/arch-fork.h
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/arch-fork.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/arch-fork.h 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1 @@
+#include <sysdeps/unix/sysv/linux/i386/arch-fork.h>
-diff --git a/sysdeps/unix/sysv/linux/riscv/bits/atomic.h b/sysdeps/unix/sysv/linux/riscv/bits/atomic.h
-new file mode 100644
-index 0000000..82b9006
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/bits/atomic.h
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/bits/atomic.h glibc/sysdeps/unix/sysv/linux/riscv/bits/atomic.h
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/bits/atomic.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/bits/atomic.h 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,53 @@
+/* Low-level functions for atomic operations. Mips version.
+ Copyright (C) 2005 Free Software Foundation, Inc.
@@ -5749,11 +5315,9 @@ index 0000000..82b9006
+#endif /* __riscv_atomic */
+
+#endif /* bits/atomic.h */
-diff --git a/sysdeps/unix/sysv/linux/riscv/bits/endian.h b/sysdeps/unix/sysv/linux/riscv/bits/endian.h
-new file mode 100644
-index 0000000..6caa0bd
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/bits/endian.h
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/bits/endian.h glibc/sysdeps/unix/sysv/linux/riscv/bits/endian.h
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/bits/endian.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/bits/endian.h 2014-12-09 14:32:35.932301937 -0800
@@ -0,0 +1,16 @@
+/* The MIPS architecture has selectable endianness.
+ Linux/MIPS exists in two both little and big endian flavours and we
@@ -5771,11 +5335,9 @@ index 0000000..6caa0bd
+# define __BYTE_ORDER __LITTLE_ENDIAN
+# endif
+#endif
-diff --git a/sysdeps/unix/sysv/linux/riscv/bits/mman.h b/sysdeps/unix/sysv/linux/riscv/bits/mman.h
-new file mode 100644
-index 0000000..8ee3d96
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/bits/mman.h
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/bits/mman.h glibc/sysdeps/unix/sysv/linux/riscv/bits/mman.h
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/bits/mman.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/bits/mman.h 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,38 @@
+/* Definitions for POSIX memory map interface. Linux/MIPS version.
+ Copyright (C) 1997, 2000, 2003, 2004, 2005, 2006, 2009, 2011
@@ -5815,11 +5377,9 @@ index 0000000..8ee3d96
+
+/* Include generic Linux declarations. */
+#include <bits/mman-linux.h>
-diff --git a/sysdeps/unix/sysv/linux/riscv/bits/sigcontext.h b/sysdeps/unix/sysv/linux/riscv/bits/sigcontext.h
-new file mode 100644
-index 0000000..3e9d7f0
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/bits/sigcontext.h
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/bits/sigcontext.h glibc/sysdeps/unix/sysv/linux/riscv/bits/sigcontext.h
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/bits/sigcontext.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/bits/sigcontext.h 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,33 @@
+/* Copyright (C) 1996, 1997, 1998, 2003, 2004, 2006 Free Software
+ Foundation, Inc. This file is part of the GNU C Library.
@@ -5854,12 +5414,10 @@ index 0000000..3e9d7f0
+};
+
+#endif
-diff --git a/sysdeps/unix/sysv/linux/riscv/clone.S b/sysdeps/unix/sysv/linux/riscv/clone.S
-new file mode 100644
-index 0000000..67b2146
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/clone.S
-@@ -0,0 +1,119 @@
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/clone.S glibc/sysdeps/unix/sysv/linux/riscv/clone.S
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/clone.S 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/clone.S 2014-12-09 14:38:38.665778707 -0800
+@@ -0,0 +1,117 @@
+/* Copyright (C) 1996, 1997, 2000, 2003, 2005 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+ Contributed by Ralf Baechle <ralf@linux-mips.org>, 1996.
@@ -5901,35 +5459,34 @@ index 0000000..67b2146
+LEAF(__clone)
+
+ /* Sanity check arguments. */
-+ li v0,EINVAL
-+ beqz a0,L(error) /* No NULL function pointers. */
-+ beqz a1,L(error) /* No NULL stack pointers. */
++ beqz a0,L(invalid) /* No NULL function pointers. */
++ beqz a1,L(invalid) /* No NULL stack pointers. */
+
-+ addi a1,a1,-32 /* Reserve argument save space. */
++ addi a1,a1,-32 /* Reserve argument save space. */
+ REG_S a0,0(a1) /* Save function pointer. */
+ REG_S a3,SZREG(a1) /* Save argument pointer. */
+#ifdef RESET_PID
+ REG_S a2,(SZREG*2)(a1) /* Save clone flags. */
+#endif
+
++ /* The syscall expects the args to be in different slots. */
+ move a0,a2
-+
-+ /* Shuffle in the last three arguments - arguments 5, 6, and 7 to
-+ this function, but arguments 3, 4, and 5 to the syscall. */
+ move a2,a4
+ move a3,a5
+ move a4,a6
+
+ /* Do the system call */
-+ li v0,__NR_clone
++ li a7,__NR_clone
+ scall
+
-+ bltz v0,L(error)
-+ beqz v0,L(thread_start)
++ bltz a0,L(error)
++ beqz a0,L(thread_start)
+
+ /* Successful return from the parent */
+ ret
+
++L(invalid):
++ li a0, 0
+ /* Something bad happened -- no child created */
+L(error):
+ j __syscall_error
@@ -5953,37 +5510,34 @@ index 0000000..67b2146
+#endif
+
+ /* Restore the arg for user's function. */
-+ REG_L v0,0(sp) /* Function pointer. */
++ REG_L a1,0(sp) /* Function pointer. */
+ REG_L a0,SZREG(sp) /* Argument pointer. */
+
+ /* Call the user's function. */
-+ jalr v0
++ jalr a1
+
-+ /* Call _exit rather than doing it inline for breakpoint purposes. */
-+ move a0,v0
++ /* Call _exit with the function's return value. */
+ j _exit
+
+#ifdef RESET_PID
+L(restore_pid):
+ and a1,a0,CLONE_VM
-+ li v0,-1
++ li a2,-1
+ bnez a1,L(gotpid)
-+ li v0,__NR_getpid
++ li a2,__NR_getpid
+ scall
+L(gotpid):
-+ sw v0,PID_OFFSET(tp)
-+ sw v0,TID_OFFSET(tp)
-+ b L(donepid)
++ sw a2,PID_OFFSET(tp)
++ sw a2,TID_OFFSET(tp)
++ j L(donepid)
+#endif
+
+ END(__thread_start)
+
+weak_alias (__clone, clone)
-diff --git a/sysdeps/unix/sysv/linux/riscv/configure b/sysdeps/unix/sysv/linux/riscv/configure
-new file mode 100644
-index 0000000..038022f
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/configure
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/configure glibc/sysdeps/unix/sysv/linux/riscv/configure
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/configure 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/configure 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,28 @@
+# This file is generated from configure.in by Autoconf. DO NOT EDIT!
+ # Local configure fragment for sysdeps/unix/sysv/linux/riscv.
@@ -6013,11 +5567,9 @@ index 0000000..038022f
+ arch_minimum_kernel=2.4.1
+ libc_cv_gcc_unwind_find_fde=no
+fi
-diff --git a/sysdeps/unix/sysv/linux/riscv/configure.in b/sysdeps/unix/sysv/linux/riscv/configure.in
-new file mode 100644
-index 0000000..87d0cd3
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/configure.in
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/configure.in glibc/sysdeps/unix/sysv/linux/riscv/configure.in
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/configure.in 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/configure.in 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,29 @@
+sinclude(./aclocal.m4)dnl Autoconf lossage
+GLIBC_PROVIDES dnl See aclocal.m4 in the top level source directory.
@@ -6048,11 +5600,9 @@ index 0000000..87d0cd3
+ arch_minimum_kernel=2.4.1
+ libc_cv_gcc_unwind_find_fde=no
+fi
-diff --git a/sysdeps/unix/sysv/linux/riscv/dl-cache.h b/sysdeps/unix/sysv/linux/riscv/dl-cache.h
-new file mode 100644
-index 0000000..8ef4822
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/dl-cache.h
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/dl-cache.h glibc/sysdeps/unix/sysv/linux/riscv/dl-cache.h
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/dl-cache.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/dl-cache.h 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,45 @@
+/* Support for reading /etc/ld.so.cache files written by Linux ldconfig.
+ Copyright (C) 2003, 2007 Free Software Foundation, Inc.
@@ -6099,11 +5649,9 @@ index 0000000..8ef4822
+ } while (0)
+
+#include_next <dl-cache.h>
-diff --git a/sysdeps/unix/sysv/linux/riscv/dl-static.c b/sysdeps/unix/sysv/linux/riscv/dl-static.c
-new file mode 100644
-index 0000000..3a99e7e
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/dl-static.c
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/dl-static.c glibc/sysdeps/unix/sysv/linux/riscv/dl-static.c
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/dl-static.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/dl-static.c 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,92 @@
+/* Variable initialization. MIPS version.
+ Copyright (C) 2001, 2002, 2003, 2005 Free Software Foundation, Inc.
@@ -6197,12 +5745,10 @@ index 0000000..3a99e7e
+}
+
+#endif
-diff --git a/sysdeps/unix/sysv/linux/riscv/getcontext.S b/sysdeps/unix/sysv/linux/riscv/getcontext.S
-new file mode 100644
-index 0000000..c849ddd
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/getcontext.S
-@@ -0,0 +1,86 @@
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/getcontext.S glibc/sysdeps/unix/sysv/linux/riscv/getcontext.S
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/getcontext.S 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/getcontext.S 2014-12-09 14:38:38.665778707 -0800
+@@ -0,0 +1,82 @@
+/* Save current context.
+ Copyright (C) 2009 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
@@ -6234,42 +5780,38 @@ index 0000000..c849ddd
+LEAF (__getcontext)
+ REG_S ra, MCONTEXT_PC(a0)
+ REG_S ra, ( 1 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S s0, ( 2 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S s1, ( 3 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S s2, ( 4 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S s3, ( 5 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S s4, ( 6 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S s5, ( 7 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S s6, ( 8 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S s7, ( 9 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S s8, (10 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S s9, (11 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S s10,(12 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S s11,(13 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S sp, (14 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S tp, (15 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S sp, ( 2 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S tp, ( 4 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S s0, ( 8 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S s1, ( 9 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S s2, (18 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S s3, (19 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S s4, (20 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S s5, (21 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S s6, (22 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S s7, (23 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S s8, (24 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S s9, (25 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S s10,(26 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S s11,(27 * SZREG + MCONTEXT_GREGS)(a0)
+
+#ifdef __riscv_hard_float
-+ frsr v1
-+
-+ fsd fs0, ( 0 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs1, ( 1 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs2, ( 2 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs3, ( 3 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs4, ( 4 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs5, ( 5 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs6, ( 6 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs7, ( 7 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs8, ( 8 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs9, ( 9 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs10,(10 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs11,(11 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs12,(12 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs13,(13 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs14,(14 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs15,(15 * 8 + MCONTEXT_FPREGS)(a0)
-+
-+ sw v1, MCONTEXT_FSR(a0)
++ frsr a1
++
++ fsd fs0, ( 8 * 8 + MCONTEXT_FPREGS)(a0)
++ fsd fs1, ( 9 * 8 + MCONTEXT_FPREGS)(a0)
++ fsd fs2, (18 * 8 + MCONTEXT_FPREGS)(a0)
++ fsd fs3, (19 * 8 + MCONTEXT_FPREGS)(a0)
++ fsd fs4, (20 * 8 + MCONTEXT_FPREGS)(a0)
++ fsd fs5, (21 * 8 + MCONTEXT_FPREGS)(a0)
++ fsd fs6, (22 * 8 + MCONTEXT_FPREGS)(a0)
++ fsd fs7, (23 * 8 + MCONTEXT_FPREGS)(a0)
++ fsd fs8, (24 * 8 + MCONTEXT_FPREGS)(a0)
++ fsd fs9, (25 * 8 + MCONTEXT_FPREGS)(a0)
++ fsd fs10,(26 * 8 + MCONTEXT_FPREGS)(a0)
++ fsd fs11,(27 * 8 + MCONTEXT_FPREGS)(a0)
++
++ sw a1, MCONTEXT_FSR(a0)
+#endif /* __mips_hard_float */
+
+/* rt_sigprocmask (SIG_BLOCK, NULL, &ucp->uc_sigmask, _NSIG8) */
@@ -6278,9 +5820,9 @@ index 0000000..c849ddd
+ move a1, zero
+ li a0, SIG_BLOCK
+
-+ li v0, SYS_ify (rt_sigprocmask)
++ li a7, SYS_ify (rt_sigprocmask)
+ scall
-+ bltz v0, 99f
++ bltz a0, 99f
+
+ ret
+
@@ -6289,18 +5831,23 @@ index 0000000..c849ddd
+PSEUDO_END (__getcontext)
+
+weak_alias (__getcontext, getcontext)
-diff --git a/sysdeps/unix/sysv/linux/riscv/getmsg.c b/sysdeps/unix/sysv/linux/riscv/getmsg.c
-new file mode 100644
-index 0000000..3a1fa08
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/getmsg.c
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/getmsg.c glibc/sysdeps/unix/sysv/linux/riscv/getmsg.c
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/getmsg.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/getmsg.c 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1 @@
+#include <sysdeps/unix/sysv/linux/i386/getmsg.c>
-diff --git a/sysdeps/unix/sysv/linux/riscv/kernel-features.h b/sysdeps/unix/sysv/linux/riscv/kernel-features.h
-new file mode 100644
-index 0000000..9283b3f
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/kernel-features.h
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/Implies glibc/sysdeps/unix/sysv/linux/riscv/Implies
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/Implies 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/Implies 2014-12-09 14:31:16.765856331 -0800
+@@ -0,0 +1,5 @@
++unix/sysv/linux/generic
++riscv/nptl
++
++# This needs to change to support rv32
++unix/sysv/linux/riscv/rv64
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/kernel-features.h glibc/sysdeps/unix/sysv/linux/riscv/kernel-features.h
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/kernel-features.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/kernel-features.h 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,29 @@
+/* Copyright (C) 2014 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
@@ -6331,11 +5878,9 @@ index 0000000..9283b3f
+/* Define this if your 32-bit syscall API requires 64-bit register
+ pairs to start with an even-number register. */
+#define __ASSUME_ALIGNED_REGISTER_PAIRS 1
-diff --git a/sysdeps/unix/sysv/linux/riscv/ldsodefs.h b/sysdeps/unix/sysv/linux/riscv/ldsodefs.h
-new file mode 100644
-index 0000000..8d5efec
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/ldsodefs.h
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/ldsodefs.h glibc/sysdeps/unix/sysv/linux/riscv/ldsodefs.h
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/ldsodefs.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/ldsodefs.h 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,33 @@
+/* Run-time dynamic linker data structures for loaded ELF shared objects. MIPS.
+ Copyright (C) 2001, 2003 Free Software Foundation, Inc.
@@ -6370,11 +5915,9 @@ index 0000000..8d5efec
+#define DL_STATIC_INIT(map) _dl_static_init (map)
+
+#endif /* ldsodefs.h */
-diff --git a/sysdeps/unix/sysv/linux/riscv/libc-abis b/sysdeps/unix/sysv/linux/riscv/libc-abis
-new file mode 100644
-index 0000000..f180a03
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/libc-abis
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/libc-abis glibc/sysdeps/unix/sysv/linux/riscv/libc-abis
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/libc-abis 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/libc-abis 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,13 @@
+# See the copy of this file in libc for detailed explanations. This
+# copy needs to include all libc definitions applicable to MIPS; only
@@ -6389,11 +5932,15 @@ index 0000000..f180a03
+# Unique symbol definitions for C++.
+# Architecture independent, all ELF targets (== all targets)
+UNIQUE
-diff --git a/sysdeps/unix/sysv/linux/riscv/makecontext.c b/sysdeps/unix/sysv/linux/riscv/makecontext.c
-new file mode 100644
-index 0000000..a0f0304
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/makecontext.c
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/____longjmp_chk.S glibc/sysdeps/unix/sysv/linux/riscv/____longjmp_chk.S
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/____longjmp_chk.S 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/____longjmp_chk.S 2014-12-09 14:31:16.765856331 -0800
+@@ -0,0 +1,2 @@
++#define __longjmp ____longjmp_chk
++#include <__longjmp.S>
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/makecontext.c glibc/sysdeps/unix/sysv/linux/riscv/makecontext.c
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/makecontext.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/makecontext.c 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,43 @@
+#include <sysdep.h>
+#include <sys/asm.h>
@@ -6438,26 +5985,37 @@ index 0000000..a0f0304
+}
+
+weak_alias (__makecontext, makecontext)
-diff --git a/sysdeps/unix/sysv/linux/riscv/profil-counter.h b/sysdeps/unix/sysv/linux/riscv/profil-counter.h
-new file mode 100644
-index 0000000..8a6a0bc
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/profil-counter.h
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/Makefile glibc/sysdeps/unix/sysv/linux/riscv/Makefile
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/Makefile 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/Makefile 2014-12-09 14:31:16.765856331 -0800
+@@ -0,0 +1,13 @@
++ifeq ($(subdir),elf)
++ifeq ($(build-shared),yes)
++# This is needed for DSO loading from static binaries.
++sysdep-dl-routines += dl-static
++sysdep_routines += dl-static
++sysdep-rtld-routines += dl-static
++endif
++endif
++
++ifeq ($(subdir),stdlib)
++sysdep_routines += __start_context
++gen-as-const-headers += ucontext_i.sym
++endif
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/profil-counter.h glibc/sysdeps/unix/sysv/linux/riscv/profil-counter.h
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/profil-counter.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/profil-counter.h 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,2 @@
+/* We can use the ix86 version. */
+#include <sysdeps/unix/sysv/linux/i386/profil-counter.h>
-diff --git a/sysdeps/unix/sysv/linux/riscv/putmsg.c b/sysdeps/unix/sysv/linux/riscv/putmsg.c
-new file mode 100644
-index 0000000..ebc1680
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/putmsg.c
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/putmsg.c glibc/sysdeps/unix/sysv/linux/riscv/putmsg.c
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/putmsg.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/putmsg.c 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1 @@
+#include <sysdeps/unix/sysv/linux/i386/putmsg.c>
-diff --git a/sysdeps/unix/sysv/linux/riscv/register-dump.h b/sysdeps/unix/sysv/linux/riscv/register-dump.h
-new file mode 100644
-index 0000000..4b498a5
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/register-dump.h
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/register-dump.h glibc/sysdeps/unix/sysv/linux/riscv/register-dump.h
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/register-dump.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/register-dump.h 2014-12-09 14:38:38.665778707 -0800
@@ -0,0 +1,65 @@
+/* Dump registers.
+ Copyright (C) 2000, 2001, 2002, 2006 Free Software Foundation, Inc.
@@ -6502,10 +6060,10 @@ index 0000000..4b498a5
+ char str[82 * ((REGDUMP_NREGS + REGDUMP_PER_LINE - 1) / REGDUMP_PER_LINE)];
+
+ static const char names[REGDUMP_NREGS][4] = {
-+ "pc", "ra", "s0", "s1", "s2", "s3", "s4", "s5",
-+ "s6", "s7", "s8", "s9", "sA", "sB", "sp", "tp",
-+ "v0", "v1", "a0", "a1", "a2", "a3", "a4", "a5",
-+ "a6", "a7", "t0", "t1", "t2", "t3", "t4", "gp"
++ "pc", "ra", "sp", "gp", "tp", "t0", "t1", "t2",
++ "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5",
++ "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7",
++ "s8", "s9", "sA", "sB", "t3", "t4", "t5", "t6"
+ };
+
+ str[0] = 0;
@@ -6524,54 +6082,29 @@ index 0000000..4b498a5
+}
+
+#define REGISTER_DUMP register_dump (fd, ctx)
-diff --git a/sysdeps/unix/sysv/linux/riscv/rv32/lockf64.c b/sysdeps/unix/sysv/linux/riscv/rv32/lockf64.c
-new file mode 100644
-index 0000000..a88f5a7
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/rv32/lockf64.c
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/rv32/lockf64.c glibc/sysdeps/unix/sysv/linux/riscv/rv32/lockf64.c
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/rv32/lockf64.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/rv32/lockf64.c 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1 @@
+#include <sysdeps/unix/sysv/linux/i386/lockf64.c>
-diff --git a/sysdeps/unix/sysv/linux/riscv/rv32/readahead.c b/sysdeps/unix/sysv/linux/riscv/rv32/readahead.c
-new file mode 100644
-index 0000000..80170c3
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/rv32/readahead.c
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/rv32/readahead.c glibc/sysdeps/unix/sysv/linux/riscv/rv32/readahead.c
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/rv32/readahead.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/rv32/readahead.c 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1 @@
+#include <sysdeps/unix/sysv/linux/arm/readahead.c>
-diff --git a/sysdeps/unix/sysv/linux/riscv/rv32/sync_file_range.c b/sysdeps/unix/sysv/linux/riscv/rv32/sync_file_range.c
-new file mode 100644
-index 0000000..4213dce
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/rv32/sync_file_range.c
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/rv32/sync_file_range.c glibc/sysdeps/unix/sysv/linux/riscv/rv32/sync_file_range.c
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/rv32/sync_file_range.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/rv32/sync_file_range.c 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1 @@
+#include <sysdeps/unix/sysv/linux/mips/mips32/sync_file_range.c>
-diff --git a/sysdeps/unix/sysv/linux/riscv/rv64/Implies b/sysdeps/unix/sysv/linux/riscv/rv64/Implies
-new file mode 100644
-index 0000000..8d91c80
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/rv64/Implies
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/rv64/Implies glibc/sysdeps/unix/sysv/linux/riscv/rv64/Implies
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/rv64/Implies 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/rv64/Implies 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1 @@
+unix/sysv/linux/wordsize-64
-diff --git a/sysdeps/unix/sysv/linux/riscv/rv64/Makefile b/sysdeps/unix/sysv/linux/riscv/rv64/Makefile
-new file mode 100644
-index 0000000..0a37c5b
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/rv64/Makefile
-@@ -0,0 +1,9 @@
-+ifeq ($(subdir),socket)
-+CFLAGS-recv.c += -fexceptions
-+CFLAGS-send.c += -fexceptions
-+endif
-+
-+ifeq ($(subdir),nptl)
-+CFLAGS-recv.c += -fexceptions
-+CFLAGS-send.c += -fexceptions
-+endif
-diff --git a/sysdeps/unix/sysv/linux/riscv/rv64/ldconfig.h b/sysdeps/unix/sysv/linux/riscv/rv64/ldconfig.h
-new file mode 100644
-index 0000000..43fca83
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/rv64/ldconfig.h
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/rv64/ldconfig.h glibc/sysdeps/unix/sysv/linux/riscv/rv64/ldconfig.h
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/rv64/ldconfig.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/rv64/ldconfig.h 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,26 @@
+/* Copyright (C) 2001, 2002, 2003 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
@@ -6599,19 +6132,28 @@ index 0000000..43fca83
+#define SYSDEP_KNOWN_LIBRARY_NAMES \
+ { "libc.so.6", FLAG_ELF_LIBC6 }, \
+ { "libm.so.6", FLAG_ELF_LIBC6 },
-diff --git a/sysdeps/unix/sysv/linux/riscv/rv64/ldd-rewrite.sed b/sysdeps/unix/sysv/linux/riscv/rv64/ldd-rewrite.sed
-new file mode 100644
-index 0000000..2c32732
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/rv64/ldd-rewrite.sed
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/rv64/ldd-rewrite.sed glibc/sysdeps/unix/sysv/linux/riscv/rv64/ldd-rewrite.sed
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/rv64/ldd-rewrite.sed 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/rv64/ldd-rewrite.sed 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1 @@
+s_^\(RTLDLIST=\)\(.*lib\)\(\|32\|64\)\(/[^/]*\.so\.[0-9.]*\)[ ]*$_\1"\232\4 \264\4 \2\4"_
-diff --git a/sysdeps/unix/sysv/linux/riscv/setcontext.S b/sysdeps/unix/sysv/linux/riscv/setcontext.S
-new file mode 100644
-index 0000000..07b6f71
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/setcontext.S
-@@ -0,0 +1,100 @@
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/rv64/Makefile glibc/sysdeps/unix/sysv/linux/riscv/rv64/Makefile
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/rv64/Makefile 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/rv64/Makefile 2014-12-09 14:31:16.765856331 -0800
+@@ -0,0 +1,9 @@
++ifeq ($(subdir),socket)
++CFLAGS-recv.c += -fexceptions
++CFLAGS-send.c += -fexceptions
++endif
++
++ifeq ($(subdir),nptl)
++CFLAGS-recv.c += -fexceptions
++CFLAGS-send.c += -fexceptions
++endif
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/setcontext.S glibc/sysdeps/unix/sysv/linux/riscv/setcontext.S
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/setcontext.S 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/setcontext.S 2014-12-09 14:38:38.665778707 -0800
+@@ -0,0 +1,96 @@
+/* Set current context.
+ Copyright (C) 2009 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
@@ -6650,73 +6192,67 @@ index 0000000..07b6f71
+ add a1, a0, UCONTEXT_SIGMASK
+ li a0, SIG_SETMASK
+
-+ li v0, SYS_ify (rt_sigprocmask)
++ li a7, SYS_ify (rt_sigprocmask)
+ scall
+
-+ bltz v0, 99f
++ bltz a0, 99f
+
+#ifdef __riscv_hard_float
-+ lw v1, MCONTEXT_FSR(t0)
-+
-+ fld fs0, ( 0 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs1, ( 1 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs2, ( 2 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs3, ( 3 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs4, ( 4 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs5, ( 5 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs6, ( 6 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs7, ( 7 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs8, ( 8 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs9, ( 9 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs10,(10 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs11,(11 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs12,(12 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs13,(13 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs14,(14 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs15,(15 * 8 + MCONTEXT_FPREGS)(t0)
-+
-+ fssr v1
-+#endif /* __mips_hard_float */
++ lw t1, MCONTEXT_FSR(t0)
++
++ fld fs0, ( 8 * 8 + MCONTEXT_FPREGS)(t0)
++ fld fs1, ( 9 * 8 + MCONTEXT_FPREGS)(t0)
++ fld fs2, (18 * 8 + MCONTEXT_FPREGS)(t0)
++ fld fs3, (19 * 8 + MCONTEXT_FPREGS)(t0)
++ fld fs4, (20 * 8 + MCONTEXT_FPREGS)(t0)
++ fld fs5, (21 * 8 + MCONTEXT_FPREGS)(t0)
++ fld fs6, (22 * 8 + MCONTEXT_FPREGS)(t0)
++ fld fs7, (23 * 8 + MCONTEXT_FPREGS)(t0)
++ fld fs8, (24 * 8 + MCONTEXT_FPREGS)(t0)
++ fld fs9, (25 * 8 + MCONTEXT_FPREGS)(t0)
++ fld fs10,(26 * 8 + MCONTEXT_FPREGS)(t0)
++ fld fs11,(27 * 8 + MCONTEXT_FPREGS)(t0)
++
++ fssr t1
++#endif /* __riscv_hard_float */
+
+ /* Note the contents of argument registers will be random
+ unless makecontext() has been called. */
-+ REG_L v1, MCONTEXT_PC(t0)
++ REG_L t1, MCONTEXT_PC(t0)
+ REG_L ra, ( 1 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L s0, ( 2 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L s1, ( 3 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L s2, ( 4 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L s3, ( 5 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L s4, ( 6 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L s5, ( 7 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L s6, ( 8 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L s7, ( 9 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L s8, (10 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L s9, (11 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L s10,(12 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L s11,(13 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L sp, (14 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L tp, (15 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L a0, (18 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L a1, (19 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L a2, (20 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L a3, (21 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L a4, (22 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L a5, (23 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L a6, (24 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L a7, (25 * SZREG + MCONTEXT_GREGS)(t0)
-+
-+ jr v1
++ REG_L sp, ( 2 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L tp, ( 4 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L s0, ( 8 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L s1, ( 9 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L a0, (10 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L a1, (11 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L a2, (12 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L a3, (13 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L a4, (14 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L a5, (15 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L a6, (16 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L a7, (17 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L s2, (18 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L s3, (19 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L s4, (20 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L s5, (21 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L s6, (22 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L s7, (23 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L s8, (24 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L s9, (25 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L s10,(26 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L s11,(27 * SZREG + MCONTEXT_GREGS)(t0)
++
++ jr t1
+
+99: j __syscall_error
+
+PSEUDO_END (__setcontext)
+
+weak_alias (__setcontext, setcontext)
-diff --git a/sysdeps/unix/sysv/linux/riscv/sigcontextinfo.h b/sysdeps/unix/sysv/linux/riscv/sigcontextinfo.h
-new file mode 100644
-index 0000000..ea01f8e
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/sigcontextinfo.h
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/sigcontextinfo.h glibc/sysdeps/unix/sysv/linux/riscv/sigcontextinfo.h
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/sigcontextinfo.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/sigcontextinfo.h 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,29 @@
+/* Copyright (C) 2000, 2001, 2003, 2004 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
@@ -6747,11 +6283,9 @@ index 0000000..ea01f8e
+
+#define CALL_SIGHANDLER(handler, signo, ctx) \
+ (handler)((signo), SIGCONTEXT_EXTRA_ARGS (ctx))
-diff --git a/sysdeps/unix/sysv/linux/riscv/socket.S b/sysdeps/unix/sysv/linux/riscv/socket.S
-new file mode 100644
-index 0000000..1f66cd4
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/socket.S
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/socket.S glibc/sysdeps/unix/sysv/linux/riscv/socket.S
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/socket.S 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/socket.S 2014-12-09 14:38:38.665778707 -0800
@@ -0,0 +1,91 @@
+/* Copyright (C) 1997, 1998, 2002, 2003 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
@@ -6825,13 +6359,13 @@ index 0000000..1f66cd4
+ SINGLE_THREAD_P(a0)
+ bnez a0, 1f
+#endif
-+ li a0, P(SOCKOP_,socket) /* arg 1: socket subfunction */
++ li a0, P(SOCKOP_,socket) /* arg 1: socket subfunction */
+ move a1, sp /* arg 2: parameter block */
-+ li v0, SYS_ify (rt_sigprocmask)
++ li a7, SYS_ify (rt_sigprocmask)
+ scall
+
+ addi sp, sp, SZREG*NARGS
-+ bltz v0, 99f
++ bltz a0, 99f
+
+#if defined NEED_CANCELLATION && defined CENABLE
+1:sbreak
@@ -6844,12 +6378,50 @@ index 0000000..1f66cd4
+#ifndef NO_WEAK_ALIAS
+weak_alias (__socket, socket)
+#endif
-diff --git a/sysdeps/unix/sysv/linux/riscv/swapcontext.S b/sysdeps/unix/sysv/linux/riscv/swapcontext.S
-new file mode 100644
-index 0000000..76ec343
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/swapcontext.S
-@@ -0,0 +1,138 @@
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/__start_context.S glibc/sysdeps/unix/sysv/linux/riscv/__start_context.S
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/__start_context.S 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/__start_context.S 2014-12-09 14:38:38.665778707 -0800
+@@ -0,0 +1,36 @@
++/* Modify saved context.
++ Copyright (C) 2009 Free Software Foundation, Inc.
++ This file is part of the GNU C Library.
++ Contributed by Maciej W. Rozycki <macro@codesourcery.com>.
++
++ The GNU C Library is free software; you can redistribute it and/or
++ modify it under the terms of the GNU Lesser General Public
++ License as published by the Free Software Foundation; either
++ version 2.1 of the License, or (at your option) any later version.
++
++ The GNU C Library is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ Lesser General Public License for more details.
++
++ You should have received a copy of the GNU Lesser General Public
++ License along with the GNU C Library; if not, write to the Free
++ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
++ 02110-1301, USA. */
++
++#include <sysdep.h>
++#include <sys/asm.h>
++
++#include "ucontext_i.h"
++
++ .text
++LEAF (__start_context)
++ move a0, zero
++ beqz s0, 1f
++
++ /* setcontext (ucp) */
++ move a0, s0
++ jal __setcontext
++1: jal HIDDEN_JUMPTARGET (exit)
++
++PSEUDO_END (__start_context)
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/swapcontext.S glibc/sysdeps/unix/sysv/linux/riscv/swapcontext.S
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/swapcontext.S 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/swapcontext.S 2014-12-09 14:38:38.665778707 -0800
+@@ -0,0 +1,131 @@
+/* Save and set current context.
+ Copyright (C) 2009 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
@@ -6882,117 +6454,108 @@ index 0000000..76ec343
+
+ REG_S ra, MCONTEXT_PC(a0)
+ REG_S ra, ( 1 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S s0, ( 2 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S s1, ( 3 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S s2, ( 4 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S s3, ( 5 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S s4, ( 6 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S s5, ( 7 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S s6, ( 8 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S s7, ( 9 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S s8, (10 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S s9, (11 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S s10,(12 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S s11,(13 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S sp, (14 * SZREG + MCONTEXT_GREGS)(a0)
-+ REG_S tp, (15 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S sp, ( 2 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S tp, ( 4 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S s0, ( 8 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S s1, ( 9 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S s2, (18 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S s3, (19 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S s4, (20 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S s5, (21 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S s6, (22 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S s7, (23 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S s8, (24 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S s9, (25 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S s10,(26 * SZREG + MCONTEXT_GREGS)(a0)
++ REG_S s11,(27 * SZREG + MCONTEXT_GREGS)(a0)
+
+#ifdef __riscv_hard_float
-+ frsr v1
-+
-+ fsd fs0, ( 0 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs1, ( 1 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs2, ( 2 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs3, ( 3 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs4, ( 4 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs5, ( 5 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs6, ( 6 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs7, ( 7 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs8, ( 8 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs9, ( 9 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs10,(10 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs11,(11 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs12,(12 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs13,(13 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs14,(14 * 8 + MCONTEXT_FPREGS)(a0)
-+ fsd fs15,(15 * 8 + MCONTEXT_FPREGS)(a0)
-+
-+ sw v1, MCONTEXT_FSR(a0)
-+#endif /* __mips_hard_float */
++ frsr a1
++
++ fsd fs0, ( 8 * 8 + MCONTEXT_FPREGS)(a0)
++ fsd fs1, ( 9 * 8 + MCONTEXT_FPREGS)(a0)
++ fsd fs2, (18 * 8 + MCONTEXT_FPREGS)(a0)
++ fsd fs3, (19 * 8 + MCONTEXT_FPREGS)(a0)
++ fsd fs4, (20 * 8 + MCONTEXT_FPREGS)(a0)
++ fsd fs5, (21 * 8 + MCONTEXT_FPREGS)(a0)
++ fsd fs6, (22 * 8 + MCONTEXT_FPREGS)(a0)
++ fsd fs7, (23 * 8 + MCONTEXT_FPREGS)(a0)
++ fsd fs8, (24 * 8 + MCONTEXT_FPREGS)(a0)
++ fsd fs9, (25 * 8 + MCONTEXT_FPREGS)(a0)
++ fsd fs10,(26 * 8 + MCONTEXT_FPREGS)(a0)
++ fsd fs11,(27 * 8 + MCONTEXT_FPREGS)(a0)
++
++ sw a1, MCONTEXT_FSR(a0)
++#endif /* __riscv_hard_float */
+
+/* rt_sigprocmask (SIG_SETMASK, &ucp->uc_sigmask, NULL, _NSIG8) */
+ li a3, _NSIG8
-+ add a2, a0, UCONTEXT_SIGMASK
-+ add a1, a1, UCONTEXT_SIGMASK
++ move a2, zero
++ add a1, a0, UCONTEXT_SIGMASK
+ li a0, SIG_SETMASK
+
-+ li v0, SYS_ify (rt_sigprocmask)
++ li a7, SYS_ify (rt_sigprocmask)
+ scall
+
-+ bltz v0, 99f
++ bltz a0, 99f
+
+#ifdef __riscv_hard_float
-+ lw v1, MCONTEXT_FSR(t0)
-+
-+ fld fs0, ( 0 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs1, ( 1 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs2, ( 2 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs3, ( 3 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs4, ( 4 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs5, ( 5 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs6, ( 6 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs7, ( 7 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs8, ( 8 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs9, ( 9 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs10,(10 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs11,(11 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs12,(12 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs13,(13 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs14,(14 * 8 + MCONTEXT_FPREGS)(t0)
-+ fld fs15,(15 * 8 + MCONTEXT_FPREGS)(t0)
-+
-+ fssr v1
-+#endif /* __mips_hard_float */
++ lw t1, MCONTEXT_FSR(t0)
++
++ fld fs0, ( 8 * 8 + MCONTEXT_FPREGS)(t0)
++ fld fs1, ( 9 * 8 + MCONTEXT_FPREGS)(t0)
++ fld fs2, (18 * 8 + MCONTEXT_FPREGS)(t0)
++ fld fs3, (19 * 8 + MCONTEXT_FPREGS)(t0)
++ fld fs4, (20 * 8 + MCONTEXT_FPREGS)(t0)
++ fld fs5, (21 * 8 + MCONTEXT_FPREGS)(t0)
++ fld fs6, (22 * 8 + MCONTEXT_FPREGS)(t0)
++ fld fs7, (23 * 8 + MCONTEXT_FPREGS)(t0)
++ fld fs8, (24 * 8 + MCONTEXT_FPREGS)(t0)
++ fld fs9, (25 * 8 + MCONTEXT_FPREGS)(t0)
++ fld fs10,(26 * 8 + MCONTEXT_FPREGS)(t0)
++ fld fs11,(27 * 8 + MCONTEXT_FPREGS)(t0)
++
++ fssr t1
++#endif /* __riscv_hard_float */
+
+ /* Note the contents of argument registers will be random
+ unless makecontext() has been called. */
-+ REG_L v1, MCONTEXT_PC(t0)
++ REG_L t1, MCONTEXT_PC(t0)
+ REG_L ra, ( 1 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L s0, ( 2 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L s1, ( 3 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L s2, ( 4 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L s3, ( 5 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L s4, ( 6 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L s5, ( 7 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L s6, ( 8 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L s7, ( 9 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L s8, (10 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L s9, (11 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L s10,(12 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L s11,(13 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L sp, (14 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L tp, (15 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L a0, (18 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L a1, (19 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L a2, (20 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L a3, (21 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L a4, (22 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L a5, (23 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L a6, (24 * SZREG + MCONTEXT_GREGS)(t0)
-+ REG_L a7, (25 * SZREG + MCONTEXT_GREGS)(t0)
-+
-+ jr v1
++ REG_L sp, ( 2 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L tp, ( 4 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L s0, ( 8 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L s1, ( 9 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L a0, (10 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L a1, (11 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L a2, (12 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L a3, (13 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L a4, (14 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L a5, (15 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L a6, (16 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L a7, (17 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L s2, (18 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L s3, (19 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L s4, (20 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L s5, (21 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L s6, (22 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L s7, (23 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L s8, (24 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L s9, (25 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L s10,(26 * SZREG + MCONTEXT_GREGS)(t0)
++ REG_L s11,(27 * SZREG + MCONTEXT_GREGS)(t0)
++
++ jr t1
++
+
+99: j __syscall_error
+
+PSEUDO_END (__swapcontext)
+
+weak_alias (__swapcontext, swapcontext)
-diff --git a/sysdeps/unix/sysv/linux/riscv/sys/procfs.h b/sysdeps/unix/sysv/linux/riscv/sys/procfs.h
-new file mode 100644
-index 0000000..ce11419
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/sys/procfs.h
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/sys/procfs.h glibc/sysdeps/unix/sysv/linux/riscv/sys/procfs.h
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/sys/procfs.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/sys/procfs.h 2014-12-09 14:32:35.932301937 -0800
@@ -0,0 +1,128 @@
+/* Copyright (C) 1996, 1997, 1999, 2000, 2002, 2003, 2004
+ Free Software Foundation, Inc.
@@ -7122,11 +6685,9 @@ index 0000000..ce11419
+__END_DECLS
+
+#endif /* sys/procfs.h */
-diff --git a/sysdeps/unix/sysv/linux/riscv/sys/ucontext.h b/sysdeps/unix/sysv/linux/riscv/sys/ucontext.h
-new file mode 100644
-index 0000000..b81ce52
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/sys/ucontext.h
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/sys/ucontext.h glibc/sysdeps/unix/sysv/linux/riscv/sys/ucontext.h
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/sys/ucontext.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/sys/ucontext.h 2014-12-09 14:38:38.665778707 -0800
@@ -0,0 +1,66 @@
+/* Copyright (C) 1997, 1998, 2000, 2003, 2004, 2006, 2009 Free Software
+ Foundation, Inc. This file is part of the GNU C Library.
@@ -7168,11 +6729,11 @@ index 0000000..b81ce52
+
+#define REG_PC 0
+#define REG_RA 1
-+#define REG_S0 2
-+#define REG_A0 18
++#define REG_SP 2
++#define REG_TP 4
++#define REG_S0 8
++#define REG_A0 10
+#define REG_NARGS 8
-+#define REG_SP 14
-+#define REG_TP 15
+
+/* Container for all general registers. */
+typedef greg_t gregset_t[NGREG];
@@ -7194,18 +6755,14 @@ index 0000000..b81ce52
+ } ucontext_t;
+
+#endif /* sys/ucontext.h */
-diff --git a/sysdeps/unix/sysv/linux/riscv/sys/user.h b/sysdeps/unix/sysv/linux/riscv/sys/user.h
-new file mode 100644
-index 0000000..c871f1a
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/sys/user.h
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/sys/user.h glibc/sysdeps/unix/sysv/linux/riscv/sys/user.h
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/sys/user.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/sys/user.h 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1 @@
+/* This file is not needed, but in practice gdb might try to include it. */
-diff --git a/sysdeps/unix/sysv/linux/riscv/syscall.c b/sysdeps/unix/sysv/linux/riscv/syscall.c
-new file mode 100644
-index 0000000..ea5e209
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/syscall.c
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/syscall.c glibc/sysdeps/unix/sysv/linux/riscv/syscall.c
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/syscall.c 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/syscall.c 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,36 @@
+/* Copyright (C) 2001, 2002, 2003, 2005 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
@@ -7243,12 +6800,10 @@ index 0000000..ea5e209
+
+ return ret;
+}
-diff --git a/sysdeps/unix/sysv/linux/riscv/sysdep.h b/sysdeps/unix/sysv/linux/riscv/sysdep.h
-new file mode 100644
-index 0000000..fa92ccb
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/sysdep.h
-@@ -0,0 +1,234 @@
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/sysdep.h glibc/sysdeps/unix/sysv/linux/riscv/sysdep.h
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/sysdep.h 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/sysdep.h 2014-12-09 14:38:38.665778707 -0800
+@@ -0,0 +1,235 @@
+/* Copyright (C) 2011-2014
+ This file is part of the GNU C Library.
+
@@ -7324,13 +6879,14 @@ index 0000000..fa92ccb
+ long _sys_result; \
+ \
+ { \
-+ register long __v0 asm("v0") = number; \
++ register long __a7 asm("a7") = number; \
++ register long __a0 asm("a0"); \
+ __asm__ volatile ( \
+ "scall\n\t" \
-+ : "+r" (__v0) \
-+ : "r" (__v0) \
++ : "=r" (__a0) \
++ : "r" (__a7) \
+ : __SYSCALL_CLOBBERS); \
-+ _sys_result = __v0; \
++ _sys_result = __a0; \
+ } \
+ _sys_result; \
+})
@@ -7340,14 +6896,14 @@ index 0000000..fa92ccb
+ long _sys_result; \
+ \
+ { \
-+ register long __v0 asm("v0") = number; \
-+ register long __a0 asm("a0") = (long) (arg0); \
++ register long __a7 asm("a7") = number; \
++ register long __a0 asm("a0") = (long) (arg0); \
+ __asm__ volatile ( \
+ "scall\n\t" \
-+ : "+r" (__v0) \
-+ : "r" (__v0), "r"(__a0) \
++ : "+r" (__a0) \
++ : "r" (__a7) \
+ : __SYSCALL_CLOBBERS); \
-+ _sys_result = __v0; \
++ _sys_result = __a0; \
+ } \
+ _sys_result; \
+})
@@ -7357,15 +6913,15 @@ index 0000000..fa92ccb
+ long _sys_result; \
+ \
+ { \
-+ register long __v0 asm("v0") = number; \
-+ register long __a0 asm("a0") = (long) (arg0); \
-+ register long __a1 asm("a1") = (long) (arg1); \
++ register long __a7 asm("a7") = number; \
++ register long __a0 asm("a0") = (long) (arg0); \
++ register long __a1 asm("a1") = (long) (arg1); \
+ __asm__ volatile ( \
+ "scall\n\t" \
-+ : "+r" (__v0) \
-+ : "r" (__v0), "r"(__a0), "r"(__a1) \
++ : "+r" (__a0) \
++ : "r" (__a7), "r"(__a1) \
+ : __SYSCALL_CLOBBERS); \
-+ _sys_result = __v0; \
++ _sys_result = __a0; \
+ } \
+ _sys_result; \
+})
@@ -7375,16 +6931,16 @@ index 0000000..fa92ccb
+ long _sys_result; \
+ \
+ { \
-+ register long __v0 asm("v0") = number; \
-+ register long __a0 asm("a0") = (long) (arg0); \
-+ register long __a1 asm("a1") = (long) (arg1); \
-+ register long __a2 asm("a2") = (long) (arg2); \
++ register long __a7 asm("a7") = number; \
++ register long __a0 asm("a0") = (long) (arg0); \
++ register long __a1 asm("a1") = (long) (arg1); \
++ register long __a2 asm("a2") = (long) (arg2); \
+ __asm__ volatile ( \
+ "scall\n\t" \
-+ : "+r" (__v0) \
-+ : "r" (__v0), "r"(__a0), "r"(__a1), "r"(__a2) \
++ : "+r" (__a0) \
++ : "r" (__a7), "r"(__a1), "r"(__a2) \
+ : __SYSCALL_CLOBBERS); \
-+ _sys_result = __v0; \
++ _sys_result = __a0; \
+ } \
+ _sys_result; \
+})
@@ -7394,17 +6950,17 @@ index 0000000..fa92ccb
+ long _sys_result; \
+ \
+ { \
-+ register long __v0 asm("v0") = number; \
-+ register long __a0 asm("a0") = (long) (arg0); \
-+ register long __a1 asm("a1") = (long) (arg1); \
-+ register long __a2 asm("a2") = (long) (arg2); \
-+ register long __a3 asm("a3") = (long) (arg3); \
++ register long __a7 asm("a7") = number; \
++ register long __a0 asm("a0") = (long) (arg0); \
++ register long __a1 asm("a1") = (long) (arg1); \
++ register long __a2 asm("a2") = (long) (arg2); \
++ register long __a3 asm("a3") = (long) (arg3); \
+ __asm__ volatile ( \
+ "scall\n\t" \
-+ : "+r" (__v0) \
-+ : "r" (__v0), "r"(__a0), "r"(__a1), "r"(__a2), "r"(__a3) \
++ : "+r" (__a0) \
++ : "r" (__a7), "r"(__a1), "r"(__a2), "r"(__a3) \
+ : __SYSCALL_CLOBBERS); \
-+ _sys_result = __v0; \
++ _sys_result = __a0; \
+ } \
+ _sys_result; \
+})
@@ -7414,18 +6970,18 @@ index 0000000..fa92ccb
+ long _sys_result; \
+ \
+ { \
-+ register long __v0 asm("v0") = number; \
-+ register long __a0 asm("a0") = (long) (arg0); \
-+ register long __a1 asm("a1") = (long) (arg1); \
-+ register long __a2 asm("a2") = (long) (arg2); \
-+ register long __a3 asm("a3") = (long) (arg3); \
-+ register long __a4 asm("a4") = (long) (arg4); \
++ register long __a7 asm("a7") = number; \
++ register long __a0 asm("a0") = (long) (arg0); \
++ register long __a1 asm("a1") = (long) (arg1); \
++ register long __a2 asm("a2") = (long) (arg2); \
++ register long __a3 asm("a3") = (long) (arg3); \
++ register long __a4 asm("a4") = (long) (arg4); \
+ __asm__ volatile ( \
+ "scall\n\t" \
-+ : "+r" (__v0) \
-+ : "r" (__v0), "r"(__a0), "r"(__a1), "r"(__a2), "r"(__a3), "r"(__a4) \
++ : "+r" (__a0) \
++ : "r" (__a7), "r"(__a1), "r"(__a2), "r"(__a3), "r"(__a4) \
+ : __SYSCALL_CLOBBERS); \
-+ _sys_result = __v0; \
++ _sys_result = __a0; \
+ } \
+ _sys_result; \
+})
@@ -7435,19 +6991,19 @@ index 0000000..fa92ccb
+ long _sys_result; \
+ \
+ { \
-+ register long __v0 asm("v0") = number; \
-+ register long __a0 asm("a0") = (long) (arg0); \
-+ register long __a1 asm("a1") = (long) (arg1); \
-+ register long __a2 asm("a2") = (long) (arg2); \
-+ register long __a3 asm("a3") = (long) (arg3); \
-+ register long __a4 asm("a4") = (long) (arg4); \
-+ register long __a5 asm("a5") = (long) (arg5); \
++ register long __a7 asm("a7") = number; \
++ register long __a0 asm("a0") = (long) (arg0); \
++ register long __a1 asm("a1") = (long) (arg1); \
++ register long __a2 asm("a2") = (long) (arg2); \
++ register long __a3 asm("a3") = (long) (arg3); \
++ register long __a4 asm("a4") = (long) (arg4); \
++ register long __a5 asm("a5") = (long) (arg5); \
+ __asm__ volatile ( \
+ "scall\n\t" \
-+ : "+r" (__v0) \
-+ : "r" (__v0), "r"(__a0), "r"(__a1), "r"(__a2), "r"(__a3), "r"(__a4), "r"(__a5) \
++ : "+r" (__a0) \
++ : "r" (__a7), "r"(__a1), "r"(__a2), "r"(__a3), "r"(__a4), "r"(__a5) \
+ : __SYSCALL_CLOBBERS); \
-+ _sys_result = __v0; \
++ _sys_result = __a0; \
+ } \
+ _sys_result; \
+})
@@ -7457,25 +7013,25 @@ index 0000000..fa92ccb
+ long _sys_result; \
+ \
+ { \
-+ register long __v0 asm("v0") = number; \
-+ register long __a0 asm("a0") = (long) (arg0); \
-+ register long __a1 asm("a1") = (long) (arg1); \
-+ register long __a2 asm("a2") = (long) (arg2); \
-+ register long __a3 asm("a3") = (long) (arg3); \
-+ register long __a4 asm("a4") = (long) (arg4); \
-+ register long __a5 asm("a5") = (long) (arg5); \
-+ register long __a6 asm("a6") = (long) (arg6); \
++ register long __a7 asm("a7") = number; \
++ register long __a0 asm("a0") = (long) (arg0); \
++ register long __a1 asm("a1") = (long) (arg1); \
++ register long __a2 asm("a2") = (long) (arg2); \
++ register long __a3 asm("a3") = (long) (arg3); \
++ register long __a4 asm("a4") = (long) (arg4); \
++ register long __a5 asm("a5") = (long) (arg5); \
++ register long __a6 asm("a6") = (long) (arg6); \
+ __asm__ volatile ( \
+ "scall\n\t" \
-+ : "+r" (__v0) \
-+ : "r" (__v0), "r"(__a0), "r"(__a1), "r"(__a2), "r"(__a3), "r"(__a4), "r"(__a5), "r"(__a6) \
++ : "+r" (__a0) \
++ : "r" (__a7), "r"(__a1), "r"(__a2), "r"(__a3), "r"(__a4), "r"(__a5), "r"(__a6) \
+ : __SYSCALL_CLOBBERS); \
-+ _sys_result = __v0; \
++ _sys_result = __a0; \
+ } \
+ _sys_result; \
+})
+
-+#define __SYSCALL_CLOBBERS "v1", "memory"
++#define __SYSCALL_CLOBBERS "memory"
+#endif /* ! __ASSEMBLER__ */
+
+/* Pointer mangling is not supported. */
@@ -7483,11 +7039,9 @@ index 0000000..fa92ccb
+#define PTR_DEMANGLE(var) (void) (var)
+
+#endif /* linux/mips/sysdep.h */
-diff --git a/sysdeps/unix/sysv/linux/riscv/ucontext_i.sym b/sysdeps/unix/sysv/linux/riscv/ucontext_i.sym
-new file mode 100644
-index 0000000..67f50d4
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/ucontext_i.sym
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/ucontext_i.sym glibc/sysdeps/unix/sysv/linux/riscv/ucontext_i.sym
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/ucontext_i.sym 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/ucontext_i.sym 2014-12-09 14:31:16.765856331 -0800
@@ -0,0 +1,33 @@
+#include <inttypes.h>
+#include <signal.h>
@@ -7522,12 +7076,54 @@ index 0000000..67f50d4
+MCONTEXT_FSR mcontext (fsr)
+
+UCONTEXT_SIZE sizeof (ucontext_t)
-diff --git a/sysdeps/unix/sysv/linux/riscv/vfork.S b/sysdeps/unix/sysv/linux/riscv/vfork.S
-new file mode 100644
-index 0000000..cc30fe5
---- /dev/null
-+++ b/sysdeps/unix/sysv/linux/riscv/vfork.S
-@@ -0,0 +1,65 @@
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/Versions glibc/sysdeps/unix/sysv/linux/riscv/Versions
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/Versions 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/Versions 2014-12-09 14:31:16.765856331 -0800
+@@ -0,0 +1,40 @@
++ld {
++ GLIBC_PRIVATE {
++ # used for loading by static libraries
++ _dl_var_init;
++ }
++}
++libc {
++ # The comment lines with "#errlist-compat" are magic; see errlist-compat.awk.
++ # When you get an error from errlist-compat.awk, you need to add a new
++ # version here. Don't do this blindly, since this means changing the ABI
++ # for all GNU/Linux configurations.
++
++ GLIBC_2.0 {
++ #errlist-compat 123
++ _sys_errlist; sys_errlist; _sys_nerr; sys_nerr;
++
++ # Exception handling support functions from libgcc
++ __register_frame; __register_frame_table; __deregister_frame;
++ __frame_state_for; __register_frame_info_table;
++
++ # Needed by gcc:
++ _flush_cache;
++
++ # c*
++ cachectl; cacheflush;
++
++ # s*
++ sysmips;
++ }
++ GLIBC_2.2 {
++ #errlist-compat 1134
++ _sys_errlist; sys_errlist; _sys_nerr; sys_nerr;
++
++ # _*
++ _test_and_set;
++ }
++ GLIBC_2.11 {
++ fallocate64;
++ }
++}
+diff -Nur original-glibc/sysdeps/unix/sysv/linux/riscv/vfork.S glibc/sysdeps/unix/sysv/linux/riscv/vfork.S
+--- original-glibc/sysdeps/unix/sysv/linux/riscv/vfork.S 1969-12-31 16:00:00.000000000 -0800
++++ glibc/sysdeps/unix/sysv/linux/riscv/vfork.S 2014-12-09 14:38:38.665778707 -0800
+@@ -0,0 +1,69 @@
+/* Copyright (C) 2005 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
@@ -7550,8 +7146,9 @@ index 0000000..cc30fe5
+
+#include <sys/asm.h>
+#include <sysdep.h>
-+#include <asm/unistd.h>
-+#include <sgidefs.h>
++#define __ASSEMBLY__
++#include <linux/sched.h>
++#include <asm/signal.h>
+
+#ifndef SAVE_PID
+#define SAVE_PID
@@ -7569,17 +7166,20 @@ index 0000000..cc30fe5
+
+ SAVE_PID
+
-+ li a0, 0x4111 /* CLONE_VM | CLONE_VFORK | SIGCHLD */
++#if (CLONE_VFORK | CLONE_VM | SIGCHLD) != 0x4111
++# error
++#endif
++ li a0, (CLONE_VFORK | CLONE_VM | SIGCHLD)
+ move a1, sp
+ li a2, 0
+ li a3, 0
+ li a4, 0
+
+ /* Do the system call */
-+ li v0,__NR_clone
++ li a7,__NR_clone
+ scall
+
-+ bltz v0,L(error)
++ bltz a0,L(error)
+
+ RESTORE_PID
+