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| author |   Andreas K. Hüttel <dilfridge@gentoo.org> | 2022-03-29 16:31:32 +0200 |
|---|---|---|
| committer | Andreas K. Hüttel <dilfridge@gentoo.org> | 2022-03-29 16:31:32 +0200 |
| commit | cc3a1c0d6535d7c5c494d8377cd27c18ce68059b (patch) | |
| tree | 5f81880787673279b7c715ae67a66bcbad66229f | |
| parent | Add mips64el-n32 specs, build, upload (diff) | |
| download | releng-cc3a1c0d6535d7c5c494d8377cd27c18ce68059b.tar.gz releng-cc3a1c0d6535d7c5c494d8377cd27c18ce68059b.tar.bz2 releng-cc3a1c0d6535d7c5c494d8377cd27c18ce68059b.zip | |
Add more mips n32 builds and uploads
Signed-off-by: Andreas K. Hüttel <dilfridge@gentoo.org>
| -rw-r--r-- | tools/catalyst-auto-qemu-mips.conf | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/tools/catalyst-auto-qemu-mips.conf b/tools/catalyst-auto-qemu-mips.conf index 21c70aca..3caeb5c3 100644 --- a/tools/catalyst-auto-qemu-mips.conf +++ b/tools/catalyst-auto-qemu-mips.conf @@ -6,7 +6,7 @@ UPLOAD_KEY=/root/.ssh/id_rsa SPECS_DIR=${REPO_DIR}/releases/specs-qemu/mips EMAIL_SUBJECT_PREPEND="[mips-qemu-auto]" -SETS="mips2o32openrc mipsel2o32openrc mips32o32openrc mips32elo32openrc mipsel3n32openrc mips3n64openrc mipsel3n64openrc mipsel3n64systemd mips64eln32openrc mips64n64openrc mips64eln64openrc mips64eln64systemd" +SETS="mips2o32openrc mipsel2o32openrc mips32o32openrc mips32elo32openrc mips3n32openrc mipsel3n32openrc mips3n64openrc mipsel3n64openrc mipsel3n64systemd mips64n32openrc mips64eln32openrc mips64n64openrc mips64eln64openrc mips64eln64systemd" SET_mips2o32openrc_SPECS="stage1-mips2-o32-openrc.spec stage3-mips2-o32-openrc.spec" SET_mipsel2o32openrc_SPECS="stage1-mipsel2-o32-openrc.spec stage3-mipsel2-o32-openrc.spec" @@ -14,12 +14,14 @@ SET_mipsel2o32openrc_SPECS="stage1-mipsel2-o32-openrc.spec stage3-mipsel2-o32-op SET_mips32o32openrc_SPECS="stage1-mips32-o32-openrc.spec stage3-mips32-o32-openrc.spec" SET_mips32elo32openrc_SPECS="stage1-mips32el-o32-openrc.spec stage3-mips32el-o32-openrc.spec" +SET_mips3n32openrc_SPECS="stage1-mips3-n32-openrc.spec stage3-mips3-n32-openrc.spec" SET_mipsel3n32openrc_SPECS="stage1-mipsel3-n32-openrc.spec stage3-mipsel3-n32-openrc.spec" SET_mips3n64openrc_SPECS="stage1-mips3-n64-openrc.spec stage3-mips3-n64-openrc.spec" SET_mipsel3n64openrc_SPECS="stage1-mipsel3-n64-openrc.spec stage3-mipsel3-n64-openrc.spec" SET_mipsel3n64systemd_SPECS="stage1-mipsel3-n64-systemd.spec stage3-mipsel3-n64-systemd.spec" +SET_mips64n32openrc_SPECS="stage1-mips64-n32-openrc.spec stage3-mips64-n32-openrc.spec" SET_mips64eln32openrc_SPECS="stage1-mips64el-n32-openrc.spec stage3-mips64el-n32-openrc.spec" SET_mips64n64openrc_SPECS="stage1-mips64-n64-openrc.spec stage3-mips64-n64-openrc.spec" @@ -60,6 +62,9 @@ post_build() { stage3-mips32el-o32-openrc.spec) upload stage3-mips32el-openrc-${TIMESTAMP}.tar.xz* ;; + stage3-mips3-n32-openrc.spec) + upload stage3-mips3_n32-openrc-${TIMESTAMP}.tar.xz* + ;; stage3-mipsel3-n32-openrc.spec) upload stage3-mipsel3_n32-openrc-${TIMESTAMP}.tar.xz* ;; @@ -72,6 +77,12 @@ post_build() { stage3-mipsel3-n64-systemd.spec) upload stage3-mipsel3_n64-systemd-${TIMESTAMP}.tar.xz* ;; + stage3-mips64-n32-openrc.spec) + upload stage3-mips64_n32-openrc-${TIMESTAMP}.tar.xz* + ;; + stage3-mips64el-n32-openrc.spec) + upload stage3-mips64el_n32-openrc-${TIMESTAMP}.tar.xz* + ;; stage3-mips64-n64-openrc.spec) upload stage3-mips64_n64-openrc-${TIMESTAMP}.tar.xz* ;; |