diff options
| author |   Robert Buchholz <rbu@gentoo.org> | 2008-06-10 20:41:31 +0000 |
|---|---|---|
| committer | Robert Buchholz <rbu@gentoo.org> | 2008-06-10 20:41:31 +0000 |
| commit | 5d1b91e560a3a4b20feca43fcb7f6123580df50d (patch) | |
| tree | e3685d0c084b4b5276481c5bd61c5c05ccfaacf1 | |
| parent | Bumping 2.6.18 patchset to Debian 2.6.18.dfsg.1-18etch6 (diff) | |
| download | xen-5d1b91e560a3a4b20feca43fcb7f6123580df50d.tar.gz xen-5d1b91e560a3a4b20feca43fcb7f6123580df50d.tar.bz2 xen-5d1b91e560a3a4b20feca43fcb7f6123580df50d.zip | |
Add backported e1000 driver from kernel-xen-2.6-2.6.21.7-3.fc8
svn path=/patches/; revision=79
| -rw-r--r-- | trunk/2.6.21/00000_README | 10 | ||||
| -rw-r--r-- | trunk/2.6.21/21350_linux-2.6-netdev-e1000e-01.patch | 18137 | ||||
| -rw-r--r-- | trunk/2.6.21/21351_linux-2.6-netdev-e1000e-02.patch | 4358 | ||||
| -rw-r--r-- | trunk/2.6.21/21352_linux-2.6-netdev-e1000e-03.patch | 95 | ||||
| -rw-r--r-- | trunk/2.6.21/21353_linux-2.6-netdev-e1000e-04.patch | 23 | ||||
| -rw-r--r-- | trunk/2.6.21/21354_linux-2.6-netdev-e1000e-05.patch | 146 | ||||
| -rw-r--r-- | trunk/2.6.21/21355_linux-2.6-netdev-e1000e-06.patch | 3777 | ||||
| -rw-r--r-- | trunk/2.6.21/21356_linux-2.6-netdev-e1000e-07.patch | 93 | ||||
| -rw-r--r-- | trunk/2.6.21/21357_linux-2.6-netdev-e1000e-08.patch | 24 | ||||
| -rw-r--r-- | trunk/2.6.21/21358_linux-2.6-netdev-e1000e-09.patch | 197 | ||||
| -rw-r--r-- | trunk/2.6.21/21359_linux-2.6-netdev-e1000e-10.patch | 46 | ||||
| -rw-r--r-- | trunk/2.6.21/21360_linux-2.6-netdev-e1000e-backport.patch | 97 |
12 files changed, 27003 insertions, 0 deletions
diff --git a/trunk/2.6.21/00000_README b/trunk/2.6.21/00000_README index f8255d6..5c1fb72 100644 --- a/trunk/2.6.21/00000_README +++ b/trunk/2.6.21/00000_README @@ -28,6 +28,16 @@ Patches 20xxx-? Various bug-fix patches from Redhat. +21351_linux-2.6-netdev-e1000e-02.patch +... +21360_linux-2.6-netdev-e1000e-backport.patch + Add e1000e driver (bug #360691) + Fri Feb 15 2008 Mark McLoughlin <markmc@redhat.com> + +26000_linux-2.6-cve-2008-0600.patch + CVE-2008-0600 fix (bug #432517) + * Tue Feb 12 2008 Eduardo Habkost <ehabkost@redhat.com> + 30037_amd64-zero-extend-32bit-ptrace-xen.patch [SECURITY] Zero extend all registers after ptrace in 32-bit entry path (Xen). diff --git a/trunk/2.6.21/21350_linux-2.6-netdev-e1000e-01.patch b/trunk/2.6.21/21350_linux-2.6-netdev-e1000e-01.patch new file mode 100644 index 0000000..3464638 --- /dev/null +++ b/trunk/2.6.21/21350_linux-2.6-netdev-e1000e-01.patch @@ -0,0 +1,18137 @@ +From: Auke Kok <auke-jan.h.kok@intel.com> +Date: Mon, 6 Aug 2007 21:14:44 +0000 (-0700) +Subject: e1000e: New pci-express e1000 driver (currently for ICH9 devices only) +X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fjgarzik%2Fnetdev-2.6.git;a=commitdiff_plain;h=5b663b9d5d5d56209c2ea0cf636c8aea172065b8 + +e1000e: New pci-express e1000 driver (currently for ICH9 devices only) + +This driver implements support for the ICH9 on-board LAN ethernet +device. The device is similar to ICH8. + +The driver encompasses code to support 82571/2/3, es2lan and ICH8 +devices as well, but those device IDs are disabled and will be +"lifted" from the e1000 driver over one at a time once this driver +receives some more live time. + +Changes to the last snapshot posted are exclusively in the internal +hardware API organization. Many thanks to Jeff Garzik for jumping in +and getting this organized with a keen eye on the future layout. + +Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> +Signed-off-by: Jeff Garzik <jeff@garzik.org> +--- + +diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig +index 81ef81c..e5f2f02 100644 +--- a/drivers/net/Kconfig ++++ b/drivers/net/Kconfig +@@ -2059,6 +2059,29 @@ config E1000_DISABLE_PACKET_SPLIT + + If in doubt, say N. + ++config E1000E ++ tristate "Intel(R) PRO/1000 PCI-Express Gigabit Ethernet support" ++ depends on PCI ++ ---help--- ++ This driver supports the PCI-Express Intel(R) PRO/1000 gigabit ++ ethernet family of adapters. For PCI or PCI-X e1000 adapters, ++ use the regular e1000 driver For more information on how to ++ identify your adapter, go to the Adapter & Driver ID Guide at: ++ ++ <http://support.intel.com/support/network/adapter/pro100/21397.htm> ++ ++ For general information and support, go to the Intel support ++ website at: ++ ++ <http://support.intel.com> ++ ++ More specific information on configuring the driver is in ++ <file:Documentation/networking/e1000e.txt>. ++ ++ To compile this driver as a module, choose M here and read ++ <file:Documentation/networking/net-modules.txt>. The module ++ will be called e1000e. ++ + source "drivers/net/ixp2000/Kconfig" + + config MYRI_SBUS +diff --git a/drivers/net/Makefile b/drivers/net/Makefile +index e684212..4140a0c 100644 +--- a/drivers/net/Makefile ++++ b/drivers/net/Makefile +@@ -3,6 +3,7 @@ + # + + obj-$(CONFIG_E1000) += e1000/ ++obj-$(CONFIG_E1000E) += e1000e/ + obj-$(CONFIG_IBM_EMAC) += ibm_emac/ + obj-$(CONFIG_IXGB) += ixgb/ + obj-$(CONFIG_CHELSIO_T1) += chelsio/ +diff --git a/drivers/net/e1000e/82571.c b/drivers/net/e1000e/82571.c +new file mode 100644 +index 0000000..a1b9d16 +--- /dev/null ++++ b/drivers/net/e1000e/82571.c +@@ -0,0 +1,1382 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2007 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS <linux.nics@intel.com> ++ e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++/* ++ * 82571EB Gigabit Ethernet Controller ++ * 82571EB Gigabit Ethernet Controller (Fiber) ++ * 82572EI Gigabit Ethernet Controller (Copper) ++ * 82572EI Gigabit Ethernet Controller (Fiber) ++ * 82572EI Gigabit Ethernet Controller ++ * 82573V Gigabit Ethernet Controller (Copper) ++ * 82573E Gigabit Ethernet Controller (Copper) ++ * 82573L Gigabit Ethernet Controller ++ */ ++ ++#include "e1000.h" ++ ++#define ID_LED_RESERVED_F746 0xF746 ++#define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \ ++ (ID_LED_OFF1_ON2 << 8) | \ ++ (ID_LED_DEF1_DEF2 << 4) | \ ++ (ID_LED_DEF1_DEF2)) ++ ++#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 ++ ++static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); ++static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); ++static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); ++static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); ++static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, ++ u16 words, u16 *data); ++static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); ++static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); ++static s32 e1000_setup_link_82571(struct e1000_hw *hw); ++static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); ++ ++/** ++ * e1000_init_phy_params_82571 - Init PHY func ptrs. ++ * @hw: pointer to the HW structure ++ * ++ * This is a function pointer entry point called by the api module. ++ **/ ++static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (hw->media_type != e1000_media_type_copper) { ++ phy->type = e1000_phy_none; ++ goto out; ++ } ++ ++ phy->addr = 1; ++ phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; ++ phy->reset_delay_us = 100; ++ ++ switch (hw->mac.type) { ++ case e1000_82571: ++ case e1000_82572: ++ phy->type = e1000_phy_igp_2; ++ break; ++ case e1000_82573: ++ phy->type = e1000_phy_m88; ++ break; ++ default: ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ break; ++ } ++ ++ /* This can only be done after all function pointers are setup. */ ++ ret_val = e1000_get_phy_id_82571(hw); ++ ++ /* Verify phy id */ ++ switch (hw->mac.type) { ++ case e1000_82571: ++ case e1000_82572: ++ if (phy->id != IGP01E1000_I_PHY_ID) { ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ break; ++ case e1000_82573: ++ if (phy->id != M88E1111_I_PHY_ID) { ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ break; ++ default: ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ break; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_init_nvm_params_82571 - Init NVM func ptrs. ++ * @hw: pointer to the HW structure ++ * ++ * This is a function pointer entry point called by the api module. ++ **/ ++static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ u32 eecd = er32(EECD); ++ u16 size; ++ ++ nvm->opcode_bits = 8; ++ nvm->delay_usec = 1; ++ switch (nvm->override) { ++ case e1000_nvm_override_spi_large: ++ nvm->page_size = 32; ++ nvm->address_bits = 16; ++ break; ++ case e1000_nvm_override_spi_small: ++ nvm->page_size = 8; ++ nvm->address_bits = 8; ++ break; ++ default: ++ nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; ++ nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; ++ break; ++ } ++ ++ switch (hw->mac.type) { ++ case e1000_82573: ++ if (((eecd >> 15) & 0x3) == 0x3) { ++ nvm->type = e1000_nvm_flash_hw; ++ nvm->word_size = 2048; ++ /* Autonomous Flash update bit must be cleared due ++ * to Flash update issue. ++ */ ++ eecd &= ~E1000_EECD_AUPDEN; ++ ew32(EECD, eecd); ++ break; ++ } ++ /* Fall Through */ ++ default: ++ nvm->type = e1000_nvm_eeprom_spi; ++ size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> ++ E1000_EECD_SIZE_EX_SHIFT); ++ /* Added to a constant, "size" becomes the left-shift value ++ * for setting word_size. ++ */ ++ size += NVM_WORD_SIZE_BASE_SHIFT; ++ nvm->word_size = 1 << size; ++ break; ++ } ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_init_mac_params_82571 - Init MAC func ptrs. ++ * @hw: pointer to the HW structure ++ * ++ * This is a function pointer entry point called by the api module. ++ **/ ++static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ struct e1000_mac_info *mac = &hw->mac; ++ struct e1000_mac_operations *func = &mac->ops; ++ s32 ret_val = E1000_SUCCESS; ++ ++ /* Set media type */ ++ switch (adapter->pdev->device) { ++ case E1000_DEV_ID_82571EB_FIBER: ++ case E1000_DEV_ID_82572EI_FIBER: ++ case E1000_DEV_ID_82571EB_QUAD_FIBER: ++ hw->media_type = e1000_media_type_fiber; ++ break; ++ case E1000_DEV_ID_82571EB_SERDES: ++ case E1000_DEV_ID_82572EI_SERDES: ++ hw->media_type = e1000_media_type_internal_serdes; ++ break; ++ default: ++ hw->media_type = e1000_media_type_copper; ++ break; ++ } ++ ++ /* Set mta register count */ ++ mac->mta_reg_count = 128; ++ /* Set rar entry count */ ++ mac->rar_entry_count = E1000_RAR_ENTRIES; ++ /* Set if manageability features are enabled. */ ++ mac->arc_subsystem_valid = ++ (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0; ++ ++ /* check for link */ ++ switch (hw->media_type) { ++ case e1000_media_type_copper: ++ func->setup_physical_interface = e1000_setup_copper_link_82571; ++ func->check_for_link = e1000_check_for_copper_link; ++ func->get_link_up_info = e1000_get_speed_and_duplex_copper; ++ break; ++ case e1000_media_type_fiber: ++ func->setup_physical_interface = e1000_setup_fiber_serdes_link_82571; ++ func->check_for_link = e1000_check_for_fiber_link; ++ func->get_link_up_info = e1000_get_speed_and_duplex_fiber_serdes; ++ break; ++ case e1000_media_type_internal_serdes: ++ func->setup_physical_interface = e1000_setup_fiber_serdes_link_82571; ++ func->check_for_link = e1000_check_for_serdes_link; ++ func->get_link_up_info = e1000_get_speed_and_duplex_fiber_serdes; ++ break; ++ default: ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ break; ++ } ++ ++out: ++ return ret_val; ++} ++ ++static s32 e1000_get_invariants_82571(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ static int global_quad_port_a; /* global port a indication */ ++ struct pci_dev *pdev = adapter->pdev; ++ u16 eeprom_data = 0; ++ int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1; ++ s32 rc; ++ ++ rc = e1000_init_mac_params_82571(adapter); ++ if (rc) ++ return rc; ++ ++ rc = e1000_init_nvm_params_82571(hw); ++ if (rc) ++ return rc; ++ ++ rc = e1000_init_phy_params_82571(hw); ++ if (rc) ++ return rc; ++ ++ /* tag quad port adapters first, it's used below */ ++ switch (pdev->device) { ++ case E1000_DEV_ID_82571EB_QUAD_COPPER: ++ case E1000_DEV_ID_82571EB_QUAD_FIBER: ++ case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: ++ adapter->flags |= FLAG_IS_QUAD_PORT; ++ /* mark the first port */ ++ if (global_quad_port_a == 0) ++ adapter->flags |= FLAG_IS_QUAD_PORT_A; ++ /* Reset for multiple quad port adapters */ ++ global_quad_port_a++; ++ if (global_quad_port_a == 4) ++ global_quad_port_a = 0; ++ break; ++ default: ++ break; ++ } ++ ++ switch (adapter->hw.mac.type) { ++ case e1000_82571: ++ /* these dual ports don't have WoL on port B at all */ ++ if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) || ++ (pdev->device == E1000_DEV_ID_82571EB_SERDES) || ++ (pdev->device == E1000_DEV_ID_82571EB_COPPER)) && ++ (is_port_b)) ++ adapter->flags &= ~FLAG_HAS_WOL; ++ /* quad ports only support WoL on port A */ ++ if (adapter->flags & FLAG_IS_QUAD_PORT && ++ (!adapter->flags & FLAG_IS_QUAD_PORT_A)) ++ adapter->flags &= ~FLAG_HAS_WOL; ++ break; ++ ++ case e1000_82573: ++ if (pdev->device == E1000_DEV_ID_82573L) { ++ e1000_read_nvm(&adapter->hw, NVM_INIT_3GIO_3, 1, ++ &eeprom_data); ++ if (eeprom_data & NVM_WORD1A_ASPM_MASK) ++ adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; ++ } ++ break; ++ default: ++ break; ++ } ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision ++ * @hw: pointer to the HW structure ++ * ++ * Reads the PHY registers and stores the PHY ID and possibly the PHY ++ * revision in the hardware structure. ++ **/ ++static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val = E1000_SUCCESS; ++ ++ switch (hw->mac.type) { ++ case e1000_82571: ++ case e1000_82572: ++ /* The 82571 firmware may still be configuring the PHY. ++ * In this case, we cannot access the PHY until the ++ * configuration is done. So we explicitly set the ++ * PHY ID. */ ++ phy->id = IGP01E1000_I_PHY_ID; ++ break; ++ case e1000_82573: ++ ret_val = e1000_get_phy_id(hw); ++ break; ++ default: ++ ret_val = -E1000_ERR_PHY; ++ break; ++ } ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore ++ * @hw: pointer to the HW structure ++ * ++ * Acquire the HW semaphore to access the PHY or NVM ++ **/ ++static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) ++{ ++ u32 swsm; ++ s32 ret_val = E1000_SUCCESS; ++ s32 timeout = hw->nvm.word_size + 1; ++ s32 i = 0; ++ ++ /* Get the FW semaphore. */ ++ for (i = 0; i < timeout; i++) { ++ swsm = er32(SWSM); ++ ew32(SWSM, swsm | E1000_SWSM_SWESMBI); ++ ++ /* Semaphore acquired if bit latched */ ++ if (er32(SWSM) & E1000_SWSM_SWESMBI) ++ break; ++ ++ udelay(50); ++ } ++ ++ if (i == timeout) { ++ /* Release semaphores */ ++ e1000_put_hw_semaphore(hw); ++ hw_dbg(hw, "Driver can't access the NVM\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_put_hw_semaphore_82571 - Release hardware semaphore ++ * @hw: pointer to the HW structure ++ * ++ * Release hardware semaphore used to access the PHY or NVM ++ **/ ++static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) ++{ ++ u32 swsm; ++ ++ swsm = er32(SWSM); ++ ++ swsm &= ~E1000_SWSM_SWESMBI; ++ ++ ew32(SWSM, swsm); ++} ++ ++/** ++ * e1000_acquire_nvm_82571 - Request for access to the EEPROM ++ * @hw: pointer to the HW structure ++ * ++ * To gain access to the EEPROM, first we must obtain a hardware semaphore. ++ * Then for non-82573 hardware, set the EEPROM access request bit and wait ++ * for EEPROM access grant bit. If the access grant bit is not set, release ++ * hardware semaphore. ++ **/ ++static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) ++{ ++ s32 ret_val; ++ ++ ret_val = e1000_get_hw_semaphore_82571(hw); ++ if (ret_val) ++ goto out; ++ ++ if (hw->mac.type != e1000_82573) ++ ret_val = e1000_acquire_nvm(hw); ++ ++ if (ret_val) ++ e1000_put_hw_semaphore_82571(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_release_nvm_82571 - Release exclusive access to EEPROM ++ * @hw: pointer to the HW structure ++ * ++ * Stop any current commands to the EEPROM and clear the EEPROM request bit. ++ **/ ++static void e1000_release_nvm_82571(struct e1000_hw *hw) ++{ ++ e1000_release_nvm(hw); ++ e1000_put_hw_semaphore_82571(hw); ++} ++ ++/** ++ * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface ++ * @hw: pointer to the HW structure ++ * @offset: offset within the EEPROM to be written to ++ * @words: number of words to write ++ * @data: 16 bit word(s) to be written to the EEPROM ++ * ++ * For non-82573 silicon, write data to EEPROM at offset using SPI interface. ++ * ++ * If e1000_update_nvm_checksum is not called after this function, the ++ * EEPROM will most likley contain an invalid checksum. ++ **/ ++static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, ++ u16 *data) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ switch (hw->mac.type) { ++ case e1000_82573: ++ ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); ++ break; ++ case e1000_82571: ++ case e1000_82572: ++ ret_val = e1000_write_nvm_spi(hw, offset, words, data); ++ break; ++ default: ++ ret_val = -E1000_ERR_NVM; ++ break; ++ } ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_update_nvm_checksum_82571 - Update EEPROM checksum ++ * @hw: pointer to the HW structure ++ * ++ * Updates the EEPROM checksum by reading/adding each word of the EEPROM ++ * up to the checksum. Then calculates the EEPROM checksum and writes the ++ * value to the EEPROM. ++ **/ ++static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) ++{ ++ u32 eecd; ++ s32 ret_val; ++ u16 i; ++ ++ ret_val = e1000_update_nvm_checksum_generic(hw); ++ if (ret_val) ++ goto out; ++ ++ /* If our nvm is an EEPROM, then we're done ++ * otherwise, commit the checksum to the flash NVM. */ ++ if (hw->nvm.type != e1000_nvm_flash_hw) ++ goto out; ++ ++ /* Check for pending operations. */ ++ for (i = 0; i < E1000_FLASH_UPDATES; i++) { ++ msleep(1); ++ if ((er32(EECD) & E1000_EECD_FLUPD) == 0) ++ break; ++ } ++ ++ if (i == E1000_FLASH_UPDATES) { ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++ /* Reset the firmware if using STM opcode. */ ++ if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) { ++ /* The enabling of and the actual reset must be done ++ * in two write cycles. ++ */ ++ ew32(HICR, E1000_HICR_FW_RESET_ENABLE); ++ e1e_flush(); ++ ew32(HICR, E1000_HICR_FW_RESET); ++ } ++ ++ /* Commit the write to flash */ ++ eecd = er32(EECD) | E1000_EECD_FLUPD; ++ ew32(EECD, eecd); ++ ++ for (i = 0; i < E1000_FLASH_UPDATES; i++) { ++ msleep(1); ++ if ((er32(EECD) & E1000_EECD_FLUPD) == 0) ++ break; ++ } ++ ++ if (i == E1000_FLASH_UPDATES) { ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum ++ * @hw: pointer to the HW structure ++ * ++ * Calculates the EEPROM checksum by reading/adding each word of the EEPROM ++ * and then verifies that the sum of the EEPROM is equal to 0xBABA. ++ **/ ++static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) ++{ ++ if (hw->nvm.type == e1000_nvm_flash_hw) ++ e1000_fix_nvm_checksum_82571(hw); ++ ++ return e1000_validate_nvm_checksum_generic(hw); ++} ++ ++/** ++ * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon ++ * @hw: pointer to the HW structure ++ * @offset: offset within the EEPROM to be written to ++ * @words: number of words to write ++ * @data: 16 bit word(s) to be written to the EEPROM ++ * ++ * After checking for invalid values, poll the EEPROM to ensure the previous ++ * command has completed before trying to write the next word. After write ++ * poll for completion. ++ * ++ * If e1000_update_nvm_checksum is not called after this function, the ++ * EEPROM will most likley contain an invalid checksum. ++ **/ ++static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, ++ u16 words, u16 *data) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ u32 i; ++ u32 eewr = 0; ++ s32 ret_val = 0; ++ ++ /* A check for invalid values: offset too large, too many words, ++ * and not enough words. */ ++ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || ++ (words == 0)) { ++ hw_dbg(hw, "nvm parameter(s) out of bounds\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++ for (i = 0; i < words; i++) { ++ eewr = (data[i] << E1000_NVM_RW_REG_DATA) | ++ ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | ++ E1000_NVM_RW_REG_START; ++ ++ ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); ++ if (ret_val) ++ break; ++ ++ ew32(EEWR, eewr); ++ ++ ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); ++ if (ret_val) ++ break; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_cfg_done_82571 - Poll for configuration done ++ * @hw: pointer to the HW structure ++ * ++ * Reads the management control register for the config done bit to be set. ++ **/ ++static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) ++{ ++ s32 timeout = PHY_CFG_TIMEOUT; ++ s32 ret_val = E1000_SUCCESS; ++ ++ while (timeout) { ++ if (er32(EEMNGCTL) & ++ E1000_NVM_CFG_DONE_PORT_0) ++ break; ++ msleep(1); ++ timeout--; ++ } ++ if (!timeout) { ++ hw_dbg(hw, "MNG configuration cycle has not completed.\n"); ++ ret_val = -E1000_ERR_RESET; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state ++ * @hw: pointer to the HW structure ++ * @active: TRUE to enable LPLU, FALSE to disable ++ * ++ * Sets the LPLU D0 state according to the active flag. When activating LPLU ++ * this function also disables smart speed and vice versa. LPLU will not be ++ * activated unless the device autonegotiation advertisement meets standards ++ * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function ++ * pointer entry point only called by PHY setup routines. ++ **/ ++static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 data; ++ ++ ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); ++ if (ret_val) ++ goto out; ++ ++ if (active) { ++ data |= IGP02E1000_PM_D0_LPLU; ++ ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); ++ if (ret_val) ++ goto out; ++ ++ /* When LPLU is enabled, we should disable SmartSpeed */ ++ ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); ++ data &= ~IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); ++ if (ret_val) ++ goto out; ++ } else { ++ data &= ~IGP02E1000_PM_D0_LPLU; ++ ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); ++ /* LPLU and SmartSpeed are mutually exclusive. LPLU is used ++ * during Dx states where the power conservation is most ++ * important. During driver activity we should enable ++ * SmartSpeed, so performance is maintained. */ ++ if (phy->smart_speed == e1000_smart_speed_on) { ++ ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data |= IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ if (ret_val) ++ goto out; ++ } else if (phy->smart_speed == e1000_smart_speed_off) { ++ ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ if (ret_val) ++ goto out; ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_reset_hw_82571 - Reset hardware ++ * @hw: pointer to the HW structure ++ * ++ * This resets the hardware into a known state. This is a ++ * function pointer entry point called by the api module. ++ **/ ++static s32 e1000_reset_hw_82571(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ u32 extcnf_ctrl; ++ u32 ctrl_ext; ++ u32 icr; ++ s32 ret_val; ++ u16 i = 0; ++ ++ /* Prevent the PCI-E bus from sticking if there is no TLP connection ++ * on the last TLP read/write transaction when MAC is reset. ++ */ ++ ret_val = e1000_disable_pcie_master(hw); ++ if (ret_val) ++ hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); ++ ++ hw_dbg(hw, "Masking off all interrupts\n"); ++ ew32(IMC, 0xffffffff); ++ ++ ew32(RCTL, 0); ++ ew32(TCTL, E1000_TCTL_PSP); ++ e1e_flush(); ++ ++ msleep(10); ++ ++ /* Must acquire the MDIO ownership before MAC reset. ++ * Ownership defaults to firmware after a reset. */ ++ if (hw->mac.type == e1000_82573) { ++ extcnf_ctrl = er32(EXTCNF_CTRL); ++ extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; ++ ++ do { ++ ew32(EXTCNF_CTRL, extcnf_ctrl); ++ extcnf_ctrl = er32(EXTCNF_CTRL); ++ ++ if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) ++ break; ++ ++ extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; ++ ++ msleep(2); ++ i++; ++ } while (i < MDIO_OWNERSHIP_TIMEOUT); ++ } ++ ++ ctrl = er32(CTRL); ++ ++ hw_dbg(hw, "Issuing a global reset to MAC\n"); ++ ew32(CTRL, ctrl | E1000_CTRL_RST); ++ ++ if (hw->nvm.type == e1000_nvm_flash_hw) { ++ udelay(10); ++ ctrl_ext = er32(CTRL_EXT); ++ ctrl_ext |= E1000_CTRL_EXT_EE_RST; ++ ew32(CTRL_EXT, ctrl_ext); ++ e1e_flush(); ++ } ++ ++ ret_val = e1000_get_auto_rd_done(hw); ++ if (ret_val) ++ /* We don't want to continue accessing MAC registers. */ ++ goto out; ++ ++ /* Phy configuration from NVM just starts after EECD_AUTO_RD is set. ++ * Need to wait for Phy configuration completion before accessing ++ * NVM and Phy. ++ */ ++ if (hw->mac.type == e1000_82573) ++ msleep(25); ++ ++ /* Clear any pending interrupt events. */ ++ ew32(IMC, 0xffffffff); ++ icr = er32(ICR); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_init_hw_82571 - Initialize hardware ++ * @hw: pointer to the HW structure ++ * ++ * This inits the hardware readying it for operation. ++ **/ ++static s32 e1000_init_hw_82571(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 reg_data; ++ s32 ret_val; ++ u16 i; ++ u16 rar_count = mac->rar_entry_count; ++ ++ e1000_initialize_hw_bits_82571(hw); ++ ++ /* Initialize identification LED */ ++ ret_val = e1000_id_led_init(hw); ++ if (ret_val) { ++ hw_dbg(hw, "Error initializing identification LED\n"); ++ goto out; ++ } ++ ++ /* Disabling VLAN filtering */ ++ hw_dbg(hw, "Initializing the IEEE VLAN\n"); ++ e1000_clear_vfta(hw); ++ ++ /* Setup the receive address. */ ++ /* If, however, a locally administered address was assigned to the ++ * 82571, we must reserve a RAR for it to work around an issue where ++ * resetting one port will reload the MAC on the other port. ++ */ ++ if (e1000_get_laa_state_82571(hw)) ++ rar_count--; ++ e1000_init_rx_addrs(hw, rar_count); ++ ++ /* Zero out the Multicast HASH table */ ++ hw_dbg(hw, "Zeroing the MTA\n"); ++ for (i = 0; i < mac->mta_reg_count; i++) ++ E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); ++ ++ /* Setup link and flow control */ ++ ret_val = e1000_setup_link_82571(hw); ++ ++ /* Set the transmit descriptor write-back policy */ ++ reg_data = er32(TXDCTL); ++ reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | ++ E1000_TXDCTL_FULL_TX_DESC_WB | ++ E1000_TXDCTL_COUNT_DESC; ++ ew32(TXDCTL, reg_data); ++ ++ /* ...for both queues. */ ++ if (mac->type != e1000_82573) { ++ reg_data = er32(TXDCTL1); ++ reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | ++ E1000_TXDCTL_FULL_TX_DESC_WB | ++ E1000_TXDCTL_COUNT_DESC; ++ ew32(TXDCTL1, reg_data); ++ } else { ++ e1000_enable_tx_pkt_filtering(hw); ++ reg_data = er32(GCR); ++ reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; ++ ew32(GCR, reg_data); ++ } ++ ++ /* Clear all of the statistics registers (clear on read). It is ++ * important that we do this after we have tried to establish link ++ * because the symbol error count will increment wildly if there ++ * is no link. ++ */ ++ e1000_clear_hw_cntrs_82571(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits ++ * @hw: pointer to the HW structure ++ * ++ * Initializes required hardware-dependent bits needed for normal operation. ++ **/ ++static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) ++{ ++ u32 reg; ++ ++ /* Transmit Descriptor Control 0 */ ++ reg = er32(TXDCTL); ++ reg |= (1 << 22); ++ ew32(TXDCTL, reg); ++ ++ /* Transmit Descriptor Control 1 */ ++ reg = er32(TXDCTL1); ++ reg |= (1 << 22); ++ ew32(TXDCTL1, reg); ++ ++ /* Transmit Arbitration Control 0 */ ++ reg = er32(TARC0); ++ reg &= ~(0xF << 27); /* 30:27 */ ++ switch (hw->mac.type) { ++ case e1000_82571: ++ case e1000_82572: ++ reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); ++ break; ++ default: ++ break; ++ } ++ ew32(TARC0, reg); ++ ++ /* Transmit Arbitration Control 1 */ ++ reg = er32(TARC1); ++ switch (hw->mac.type) { ++ case e1000_82571: ++ case e1000_82572: ++ reg &= ~((1 << 29) | (1 << 30)); ++ reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); ++ if (er32(TCTL) & E1000_TCTL_MULR) ++ reg &= ~(1 << 28); ++ else ++ reg |= (1 << 28); ++ ew32(TARC1, reg); ++ break; ++ default: ++ break; ++ } ++ ++ /* Device Control */ ++ if (hw->mac.type == e1000_82573) { ++ reg = er32(CTRL); ++ reg &= ~(1 << 29); ++ ew32(CTRL, reg); ++ } ++ ++ /* Extended Device Control */ ++ if (hw->mac.type == e1000_82573) { ++ reg = er32(CTRL_EXT); ++ reg &= ~(1 << 23); ++ reg |= (1 << 22); ++ ew32(CTRL_EXT, reg); ++ } ++} ++ ++/** ++ * e1000_clear_vfta - Clear VLAN filter table ++ * @hw: pointer to the HW structure ++ * ++ * Clears the register array which contains the VLAN filter table by ++ * setting all the values to 0. ++ **/ ++void e1000_clear_vfta(struct e1000_hw *hw) ++{ ++ u32 offset; ++ u32 vfta_value = 0; ++ u32 vfta_offset = 0; ++ u32 vfta_bit_in_reg = 0; ++ ++ if (hw->mac.type == e1000_82573) { ++ if (hw->mng_cookie.vlan_id != 0) { ++ /* The VFTA is a 4096b bit-field, each identifying ++ * a single VLAN ID. The following operations ++ * determine which 32b entry (i.e. offset) into the ++ * array we want to set the VLAN ID (i.e. bit) of ++ * the manageability unit. ++ */ ++ vfta_offset = (hw->mng_cookie.vlan_id >> ++ E1000_VFTA_ENTRY_SHIFT) & ++ E1000_VFTA_ENTRY_MASK; ++ vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & ++ E1000_VFTA_ENTRY_BIT_SHIFT_MASK); ++ } ++ } ++ for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { ++ /* If the offset we want to clear is the same offset of the ++ * manageability VLAN ID, then clear all bits except that of ++ * the manageability unit. ++ */ ++ vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; ++ E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); ++ e1e_flush(); ++ } ++} ++ ++/** ++ * e1000_mc_addr_list_update_82571 - Update Multicast addresses ++ * @hw: pointer to the HW structure ++ * @mc_addr_list: array of multicast addresses to program ++ * @mc_addr_count: number of multicast addresses to program ++ * @rar_used_count: the first RAR register free to program ++ * @rar_count: total number of supported Receive Address Registers ++ * ++ * Updates the Receive Address Registers and Multicast Table Array. ++ * The caller must have a packed mc_addr_list of multicast addresses. ++ * The parameter rar_count will usually be hw->mac.rar_entry_count ++ * unless there are workarounds that change this. ++ **/ ++static void e1000_mc_addr_list_update_82571(struct e1000_hw *hw, ++ u8 *mc_addr_list, ++ u32 mc_addr_count, ++ u32 rar_used_count, ++ u32 rar_count) ++{ ++ if (e1000_get_laa_state_82571(hw)) ++ rar_count--; ++ ++ e1000_mc_addr_list_update_generic(hw, mc_addr_list, mc_addr_count, ++ rar_used_count, rar_count); ++} ++ ++/** ++ * e1000_setup_link_82571 - Setup flow control and link settings ++ * @hw: pointer to the HW structure ++ * ++ * Determines which flow control settings to use, then configures flow ++ * control. Calls the appropriate media-specific link configuration ++ * function. Assuming the adapter has a valid link partner, a valid link ++ * should be established. Assumes the hardware has previously been reset ++ * and the transmitter and receiver are not enabled. ++ **/ ++static s32 e1000_setup_link_82571(struct e1000_hw *hw) ++{ ++ /* 82573 does not have a word in the NVM to determine ++ * the default flow control setting, so we explicitly ++ * set it to full. ++ */ ++ if (hw->mac.type == e1000_82573) ++ hw->mac.fc = e1000_fc_full; ++ ++ return e1000_setup_link(hw); ++} ++ ++/** ++ * e1000_setup_copper_link_82571 - Configure copper link settings ++ * @hw: pointer to the HW structure ++ * ++ * Configures the link for auto-neg or forced speed and duplex. Then we check ++ * for link, once link is established calls to configure collision distance ++ * and flow control are called. ++ **/ ++static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ u32 led_ctrl; ++ s32 ret_val; ++ ++ ctrl = er32(CTRL); ++ ctrl |= E1000_CTRL_SLU; ++ ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); ++ ew32(CTRL, ctrl); ++ ++ switch (hw->phy.type) { ++ case e1000_phy_m88: ++ ret_val = e1000_copper_link_setup_m88(hw); ++ break; ++ case e1000_phy_igp_2: ++ ret_val = e1000_copper_link_setup_igp(hw); ++ /* Setup activity LED */ ++ led_ctrl = er32(LEDCTL); ++ led_ctrl &= IGP_ACTIVITY_LED_MASK; ++ led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); ++ ew32(LEDCTL, led_ctrl); ++ break; ++ default: ++ ret_val = -E1000_ERR_PHY; ++ break; ++ } ++ ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000_setup_copper_link(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes ++ * @hw: pointer to the HW structure ++ * ++ * Configures collision distance and flow control for fiber and serdes links. ++ * Upon successful setup, poll for link. ++ **/ ++static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) ++{ ++ switch (hw->mac.type) { ++ case e1000_82571: ++ case e1000_82572: ++ /* If SerDes loopback mode is entered, there is no form ++ * of reset to take the adapter out of that mode. So we ++ * have to explicitly take the adapter out of loopback ++ * mode. This prevents drivers from twidling their thumbs ++ * if another tool failed to take it out of loopback mode. ++ */ ++ ew32(SCTL, ++ E1000_SCTL_DISABLE_SERDES_LOOPBACK); ++ break; ++ default: ++ break; ++ } ++ ++ return e1000_setup_fiber_serdes_link(hw); ++} ++ ++/** ++ * e1000_valid_led_default_82571 - Verify a valid default LED config ++ * @hw: pointer to the HW structure ++ * @data: pointer to the NVM (EEPROM) ++ * ++ * Read the EEPROM for the current default LED configuration. If the ++ * LED configuration is not valid, set to a valid LED configuration. ++ **/ ++static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) ++{ ++ s32 ret_val; ++ ++ ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); ++ if (ret_val) { ++ hw_dbg(hw, "NVM Read Error\n"); ++ goto out; ++ } ++ ++ if (hw->mac.type == e1000_82573 && ++ *data == ID_LED_RESERVED_F746) ++ *data = ID_LED_DEFAULT_82573; ++ else if (*data == ID_LED_RESERVED_0000 || ++ *data == ID_LED_RESERVED_FFFF) ++ *data = ID_LED_DEFAULT; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_laa_state_82571 - Get locally administered address state ++ * @hw: pointer to the HW structure ++ * ++ * Retrieve and return the current locally administed address state. ++ **/ ++bool e1000_get_laa_state_82571(struct e1000_hw *hw) ++{ ++ if (hw->mac.type != e1000_82571) ++ return 0; ++ ++ return hw->dev_spec.e82571.laa_is_present; ++} ++ ++/** ++ * e1000_set_laa_state_82571 - Set locally administered address state ++ * @hw: pointer to the HW structure ++ * @state: enable/disable locally administered address ++ * ++ * Enable/Disable the current locally administed address state. ++ **/ ++void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) ++{ ++ if (hw->mac.type != e1000_82571) ++ goto out; ++ ++ hw->dev_spec.e82571.laa_is_present = state; ++ ++ /* If workaround is activated... */ ++ if (state) ++ /* Hold a copy of the LAA in RAR[14] This is done so that ++ * between the time RAR[0] gets clobbered and the time it ++ * gets fixed, the actual LAA is in one of the RARs and no ++ * incoming packets directed to this port are dropped. ++ * Eventually the LAA will be in RAR[0] and RAR[14]. ++ */ ++ e1000_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1); ++ ++out: ++ return; ++} ++ ++/** ++ * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum ++ * @hw: pointer to the HW structure ++ * ++ * Verifies that the EEPROM has completed the update. After updating the ++ * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If ++ * the checksum fix is not implemented, we need to set the bit and update ++ * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, ++ * we need to return bad checksum. ++ **/ ++static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ s32 ret_val = E1000_SUCCESS; ++ u16 data; ++ ++ if (nvm->type != e1000_nvm_flash_hw) ++ goto out; ++ ++ /* Check bit 4 of word 10h. If it is 0, firmware is done updating ++ * 10h-12h. Checksum may need to be fixed. ++ */ ++ ret_val = e1000_read_nvm(hw, 0x10, 1, &data); ++ if (ret_val) ++ goto out; ++ ++ if (!(data & 0x10)) { ++ /* Read 0x23 and check bit 15. This bit is a 1 ++ * when the checksum has already been fixed. If ++ * the checksum is still wrong and this bit is a ++ * 1, we need to return bad checksum. Otherwise, ++ * we need to set this bit to a 1 and update the ++ * checksum. ++ */ ++ ret_val = e1000_read_nvm(hw, 0x23, 1, &data); ++ if (ret_val) ++ goto out; ++ ++ if (!(data & 0x8000)) { ++ data |= 0x8000; ++ ret_val = e1000_write_nvm(hw, 0x23, 1, &data); ++ if (ret_val) ++ goto out; ++ ret_val = e1000_update_nvm_checksum(hw); ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters ++ * @hw: pointer to the HW structure ++ * ++ * Clears the hardware counters by reading the counter registers. ++ **/ ++static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) ++{ ++ u32 temp; ++ ++ e1000_clear_hw_cntrs_base(hw); ++ ++ temp = er32(PRC64); ++ temp = er32(PRC127); ++ temp = er32(PRC255); ++ temp = er32(PRC511); ++ temp = er32(PRC1023); ++ temp = er32(PRC1522); ++ temp = er32(PTC64); ++ temp = er32(PTC127); ++ temp = er32(PTC255); ++ temp = er32(PTC511); ++ temp = er32(PTC1023); ++ temp = er32(PTC1522); ++ ++ temp = er32(ALGNERRC); ++ temp = er32(RXERRC); ++ temp = er32(TNCRS); ++ temp = er32(CEXTERR); ++ temp = er32(TSCTC); ++ temp = er32(TSCTFC); ++ ++ temp = er32(MGTPRC); ++ temp = er32(MGTPDC); ++ temp = er32(MGTPTC); ++ ++ temp = er32(IAC); ++ temp = er32(ICRXOC); ++ ++ temp = er32(ICRXPTC); ++ temp = er32(ICRXATC); ++ temp = er32(ICTXPTC); ++ temp = er32(ICTXATC); ++ temp = er32(ICTXQEC); ++ temp = er32(ICTXQMTC); ++ temp = er32(ICRXDMTC); ++} ++ ++static struct e1000_mac_operations e82571_mac_ops = { ++ .mng_mode_enab = E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT, ++ /* .check_for_link: media type dependent */ ++ .cleanup_led = e1000_cleanup_led_generic, ++ .clear_hw_cntrs = e1000_clear_hw_cntrs_82571, ++ .get_bus_info = e1000_get_bus_info_pcie, ++ /* .get_link_up_info: media type dependent */ ++ .led_on = e1000_led_on_generic, ++ .led_off = e1000_led_off_generic, ++ .mc_addr_list_update = e1000_mc_addr_list_update_82571, ++ .reset_hw = e1000_reset_hw_82571, ++ .init_hw = e1000_init_hw_82571, ++ .setup_link = e1000_setup_link_82571, ++ /* .setup_physical_interface: media type dependent */ ++}; ++ ++static struct e1000_phy_operations e82_phy_ops_igp = { ++ .acquire_phy = e1000_get_hw_semaphore_82571, ++ .check_reset_block = e1000_check_reset_block_generic, ++ .commit_phy = NULL, ++ .force_speed_duplex = e1000_phy_force_speed_duplex_igp, ++ .get_cfg_done = e1000_get_cfg_done_82571, ++ .get_cable_length = e1000_get_cable_length_igp_2, ++ .get_phy_info = e1000_get_phy_info_igp, ++ .read_phy_reg = e1000_read_phy_reg_igp, ++ .release_phy = e1000_put_hw_semaphore_82571, ++ .reset_phy = e1000_phy_hw_reset_generic, ++ .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, ++ .set_d3_lplu_state = e1000_set_d3_lplu_state, ++ .write_phy_reg = e1000_write_phy_reg_igp, ++}; ++ ++static struct e1000_phy_operations e82_phy_ops_m88 = { ++ .acquire_phy = e1000_get_hw_semaphore_82571, ++ .check_reset_block = e1000_check_reset_block_generic, ++ .commit_phy = e1000_phy_sw_reset, ++ .force_speed_duplex = e1000_phy_force_speed_duplex_m88, ++ .get_cfg_done = e1000_get_cfg_done, ++ .get_cable_length = e1000_get_cable_length_m88, ++ .get_phy_info = e1000_get_phy_info_m88, ++ .read_phy_reg = e1000_read_phy_reg_m88, ++ .release_phy = e1000_put_hw_semaphore_82571, ++ .reset_phy = e1000_phy_hw_reset_generic, ++ .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, ++ .set_d3_lplu_state = e1000_set_d3_lplu_state, ++ .write_phy_reg = e1000_write_phy_reg_m88, ++}; ++ ++static struct e1000_nvm_operations e82571_nvm_ops = { ++ .acquire_nvm = e1000_acquire_nvm_82571, ++ .read_nvm = e1000_read_nvm_spi, ++ .release_nvm = e1000_release_nvm_82571, ++ .update_nvm = e1000_update_nvm_checksum_82571, ++ .valid_led_default = e1000_valid_led_default_82571, ++ .validate_nvm = e1000_validate_nvm_checksum_82571, ++ .write_nvm = e1000_write_nvm_82571, ++}; ++ ++static struct e1000_nvm_operations e82573_nvm_ops = { ++ .acquire_nvm = e1000_acquire_nvm_82571, ++ .read_nvm = e1000_read_nvm_eerd, ++ .release_nvm = e1000_release_nvm_82571, ++ .update_nvm = e1000_update_nvm_checksum_82571, ++ .valid_led_default = e1000_valid_led_default_82571, ++ .validate_nvm = e1000_validate_nvm_checksum_82571, ++ .write_nvm = e1000_write_nvm_82571, ++}; ++ ++struct e1000_info e1000_82571_info = { ++ .mac = e1000_82571, ++ .flags = FLAG_HAS_HW_VLAN_FILTER ++ | FLAG_HAS_JUMBO_FRAMES ++ | FLAG_HAS_STATS_PTC_PRC ++ | FLAG_HAS_WOL ++ | FLAG_APME_IN_CTRL3 ++ | FLAG_RX_CSUM_ENABLED ++ | FLAG_HAS_CTRLEXT_ON_LOAD ++ | FLAG_HAS_STATS_ICR_ICT ++ | FLAG_HAS_SMART_POWER_DOWN ++ | FLAG_RESET_OVERWRITES_LAA /* errata */ ++ | FLAG_TARC_SPEED_MODE_BIT /* errata */ ++ | FLAG_APME_CHECK_PORT_B, ++ .pba = 38, ++ .get_invariants = e1000_get_invariants_82571, ++ .mac_ops = &e82571_mac_ops, ++ .phy_ops = &e82_phy_ops_igp, ++ .nvm_ops = &e82571_nvm_ops, ++}; ++ ++struct e1000_info e1000_82572_info = { ++ .mac = e1000_82572, ++ .flags = FLAG_HAS_HW_VLAN_FILTER ++ | FLAG_HAS_JUMBO_FRAMES ++ | FLAG_HAS_STATS_PTC_PRC ++ | FLAG_HAS_WOL ++ | FLAG_APME_IN_CTRL3 ++ | FLAG_RX_CSUM_ENABLED ++ | FLAG_HAS_CTRLEXT_ON_LOAD ++ | FLAG_HAS_STATS_ICR_ICT ++ | FLAG_TARC_SPEED_MODE_BIT, /* errata */ ++ .pba = 38, ++ .get_invariants = e1000_get_invariants_82571, ++ .mac_ops = &e82571_mac_ops, ++ .phy_ops = &e82_phy_ops_igp, ++ .nvm_ops = &e82571_nvm_ops, ++}; ++ ++struct e1000_info e1000_82573_info = { ++ .mac = e1000_82573, ++ .flags = FLAG_HAS_HW_VLAN_FILTER ++ | FLAG_HAS_JUMBO_FRAMES ++ | FLAG_HAS_STATS_PTC_PRC ++ | FLAG_HAS_WOL ++ | FLAG_APME_IN_CTRL3 ++ | FLAG_RX_CSUM_ENABLED ++ | FLAG_HAS_STATS_ICR_ICT ++ | FLAG_HAS_SMART_POWER_DOWN ++ | FLAG_HAS_AMT ++ | FLAG_HAS_ASPM ++ | FLAG_HAS_ERT ++ | FLAG_HAS_SWSM_ON_LOAD, ++ .pba = 20, ++ .get_invariants = e1000_get_invariants_82571, ++ .mac_ops = &e82571_mac_ops, ++ .phy_ops = &e82_phy_ops_m88, ++ .nvm_ops = &e82573_nvm_ops, ++}; ++ +diff --git a/drivers/net/e1000e/Makefile b/drivers/net/e1000e/Makefile +new file mode 100644 +index 0000000..650f866 +--- /dev/null ++++ b/drivers/net/e1000e/Makefile +@@ -0,0 +1,37 @@ ++################################################################################ ++# ++# Intel PRO/1000 Linux driver ++# Copyright(c) 1999 - 2007 Intel Corporation. ++# ++# This program is free software; you can redistribute it and/or modify it ++# under the terms and conditions of the GNU General Public License, ++# version 2, as published by the Free Software Foundation. ++# ++# This program is distributed in the hope it will be useful, but WITHOUT ++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++# more details. ++# ++# You should have received a copy of the GNU General Public License along with ++# this program; if not, write to the Free Software Foundation, Inc., ++# 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++# ++# The full GNU General Public License is included in this distribution in ++# the file called "COPYING". ++# ++# Contact Information: ++# Linux NICS <linux.nics@intel.com> ++# e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> ++# Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++# ++################################################################################ ++ ++# ++# Makefile for the Intel(R) PRO/1000 ethernet driver ++# ++ ++obj-$(CONFIG_E1000E) += e1000e.o ++ ++e1000e-objs := 82571.o ich8lan.o es2lan.o \ ++ lib.o phy.o param.o ethtool.o netdev.o ++ +diff --git a/drivers/net/e1000e/defines.h b/drivers/net/e1000e/defines.h +new file mode 100644 +index 0000000..e0a36f1 +--- /dev/null ++++ b/drivers/net/e1000e/defines.h +@@ -0,0 +1,738 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2007 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS <linux.nics@intel.com> ++ e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _E1000_DEFINES_H_ ++#define _E1000_DEFINES_H_ ++ ++#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ ++#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ ++#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ ++#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ ++#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ ++#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ ++#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ ++#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ ++#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ ++#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ ++#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ ++#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ ++#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ ++#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ ++#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ ++#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ ++#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ ++#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ ++ ++/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ ++#define REQ_TX_DESCRIPTOR_MULTIPLE 8 ++#define REQ_RX_DESCRIPTOR_MULTIPLE 8 ++ ++/* Definitions for power management and wakeup registers */ ++/* Wake Up Control */ ++#define E1000_WUC_APME 0x00000001 /* APM Enable */ ++#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ ++ ++/* Wake Up Filter Control */ ++#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ ++#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ ++#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ ++#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ ++#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ ++ ++/* Extended Device Control */ ++#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ ++#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ ++#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ ++#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 ++#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 ++#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ ++#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ ++#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ ++ ++/* Receive Decriptor bit definitions */ ++#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ ++#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ ++#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ ++#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ ++#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */ ++#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ ++#define E1000_RXD_ERR_CE 0x01 /* CRC Error */ ++#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ ++#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ ++#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ ++#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ ++#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ ++#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ ++ ++#define E1000_RXDEXT_STATERR_CE 0x01000000 ++#define E1000_RXDEXT_STATERR_SE 0x02000000 ++#define E1000_RXDEXT_STATERR_SEQ 0x04000000 ++#define E1000_RXDEXT_STATERR_CXE 0x10000000 ++#define E1000_RXDEXT_STATERR_RXE 0x80000000 ++ ++/* mask to determine if packets should be dropped due to frame errors */ ++#define E1000_RXD_ERR_FRAME_ERR_MASK ( \ ++ E1000_RXD_ERR_CE | \ ++ E1000_RXD_ERR_SE | \ ++ E1000_RXD_ERR_SEQ | \ ++ E1000_RXD_ERR_CXE | \ ++ E1000_RXD_ERR_RXE) ++ ++/* Same mask, but for extended and packet split descriptors */ ++#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ ++ E1000_RXDEXT_STATERR_CE | \ ++ E1000_RXDEXT_STATERR_SE | \ ++ E1000_RXDEXT_STATERR_SEQ | \ ++ E1000_RXDEXT_STATERR_CXE | \ ++ E1000_RXDEXT_STATERR_RXE) ++ ++#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 ++ ++/* Management Control */ ++#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ ++#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ ++#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ ++#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ ++#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ ++#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address ++ * filtering */ ++#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host ++ * memory */ ++ ++/* Receive Control */ ++#define E1000_RCTL_EN 0x00000002 /* enable */ ++#define E1000_RCTL_SBP 0x00000004 /* store bad packet */ ++#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ ++#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ ++#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ ++#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ ++#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ ++#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ ++#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ ++#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ ++#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ ++#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ ++/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ ++#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ ++#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ ++#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ ++#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ ++/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ ++#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ ++#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ ++#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ ++#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ ++#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ ++#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ ++#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ ++#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ ++ ++/* Use byte values for the following shift parameters ++ * Usage: ++ * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & ++ * E1000_PSRCTL_BSIZE0_MASK) | ++ * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & ++ * E1000_PSRCTL_BSIZE1_MASK) | ++ * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & ++ * E1000_PSRCTL_BSIZE2_MASK) | ++ * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; ++ * E1000_PSRCTL_BSIZE3_MASK)) ++ * where value0 = [128..16256], default=256 ++ * value1 = [1024..64512], default=4096 ++ * value2 = [0..64512], default=4096 ++ * value3 = [0..64512], default=0 ++ */ ++ ++#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F ++#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 ++#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 ++#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 ++ ++#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ ++#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ ++#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ ++#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ ++ ++/* SWFW_SYNC Definitions */ ++#define E1000_SWFW_EEP_SM 0x1 ++#define E1000_SWFW_PHY0_SM 0x2 ++#define E1000_SWFW_PHY1_SM 0x4 ++ ++/* Device Control */ ++#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ ++#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ ++#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ ++#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ ++#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ ++#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ ++#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ ++#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ ++#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ ++#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ ++#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ ++#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ ++#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ ++#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ ++#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ ++#define E1000_CTRL_RST 0x04000000 /* Global reset */ ++#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ ++#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ ++#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ ++#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ ++ ++/* Bit definitions for the Management Data IO (MDIO) and Management Data ++ * Clock (MDC) pins in the Device Control Register. ++ */ ++ ++/* Device Status */ ++#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ ++#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ ++#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ ++#define E1000_STATUS_FUNC_SHIFT 2 ++#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ ++#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ ++#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ ++#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ ++#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ ++#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */ ++#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ ++ ++/* Constants used to intrepret the masked PCI-X bus speed. */ ++ ++#define HALF_DUPLEX 1 ++#define FULL_DUPLEX 2 ++ ++ ++#define ADVERTISE_10_HALF 0x0001 ++#define ADVERTISE_10_FULL 0x0002 ++#define ADVERTISE_100_HALF 0x0004 ++#define ADVERTISE_100_FULL 0x0008 ++#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ ++#define ADVERTISE_1000_FULL 0x0020 ++ ++/* 1000/H is not supported, nor spec-compliant. */ ++#define E1000_ALL_SPEED_DUPLEX ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ ++ ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ ++ ADVERTISE_1000_FULL) ++#define E1000_ALL_NOT_GIG ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ ++ ADVERTISE_100_HALF | ADVERTISE_100_FULL) ++#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) ++#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) ++#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) ++ ++#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX ++ ++/* LED Control */ ++#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F ++#define E1000_LEDCTL_LED0_MODE_SHIFT 0 ++#define E1000_LEDCTL_LED0_IVRT 0x00000040 ++#define E1000_LEDCTL_LED0_BLINK 0x00000080 ++ ++#define E1000_LEDCTL_MODE_LED_ON 0xE ++#define E1000_LEDCTL_MODE_LED_OFF 0xF ++ ++/* Transmit Descriptor bit definitions */ ++#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ ++#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ ++#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ ++#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ ++#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ ++#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ ++#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ ++#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ ++#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ ++#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ ++#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ ++#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ ++#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ ++#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ ++#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ ++#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ ++#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ ++#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ ++#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ ++ ++/* Transmit Control */ ++#define E1000_TCTL_EN 0x00000002 /* enable tx */ ++#define E1000_TCTL_PSP 0x00000008 /* pad short packets */ ++#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ ++#define E1000_TCTL_COLD 0x003ff000 /* collision distance */ ++#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ ++#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ ++ ++/* Transmit Arbitration Count */ ++ ++/* SerDes Control */ ++#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 ++ ++/* Receive Checksum Control */ ++#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ ++#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ ++ ++/* Header split receive */ ++#define E1000_RFCTL_EXTEN 0x00008000 ++#define E1000_RFCTL_IPV6_EX_DIS 0x00010000 ++#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 ++ ++/* Collision related configuration parameters */ ++#define E1000_COLLISION_THRESHOLD 15 ++#define E1000_CT_SHIFT 4 ++#define E1000_COLLISION_DISTANCE 63 ++#define E1000_COLD_SHIFT 12 ++ ++/* Default values for the transmit IPG register */ ++#define DEFAULT_82543_TIPG_IPGT_COPPER 8 ++ ++#define E1000_TIPG_IPGT_MASK 0x000003FF ++ ++#define DEFAULT_82543_TIPG_IPGR1 8 ++#define E1000_TIPG_IPGR1_SHIFT 10 ++ ++#define DEFAULT_82543_TIPG_IPGR2 6 ++#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 ++#define E1000_TIPG_IPGR2_SHIFT 20 ++ ++#define MAX_JUMBO_FRAME_SIZE 0x3F00 ++ ++/* Extended Configuration Control and Size */ ++#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 ++#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 ++#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 ++#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 ++#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 ++#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 ++#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 ++ ++#define E1000_PHY_CTRL_D0A_LPLU 0x00000002 ++#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 ++#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 ++#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 ++ ++#define E1000_KABGTXD_BGSQLBIAS 0x00050000 ++ ++/* PBA constants */ ++#define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */ ++#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ ++ ++#define E1000_PBS_16K E1000_PBA_16K ++ ++#define IFS_MAX 80 ++#define IFS_MIN 40 ++#define IFS_RATIO 4 ++#define IFS_STEP 10 ++#define MIN_NUM_XMITS 1000 ++ ++/* SW Semaphore Register */ ++#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ ++#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ ++#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ ++ ++/* Interrupt Cause Read */ ++#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ ++#define E1000_ICR_LSC 0x00000004 /* Link Status Change */ ++#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ ++#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ ++#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ ++#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ ++ ++/* This defines the bits that are set in the Interrupt Mask ++ * Set/Read Register. Each bit is documented below: ++ * o RXT0 = Receiver Timer Interrupt (ring 0) ++ * o TXDW = Transmit Descriptor Written Back ++ * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) ++ * o RXSEQ = Receive Sequence Error ++ * o LSC = Link Status Change ++ */ ++#define IMS_ENABLE_MASK ( \ ++ E1000_IMS_RXT0 | \ ++ E1000_IMS_TXDW | \ ++ E1000_IMS_RXDMT0 | \ ++ E1000_IMS_RXSEQ | \ ++ E1000_IMS_LSC) ++ ++/* Interrupt Mask Set */ ++#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ ++#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ ++#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ ++#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ ++#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ ++ ++/* Interrupt Cause Set */ ++#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ ++#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ ++ ++/* Transmit Descriptor Control */ ++#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ ++#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ ++#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ ++#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ ++#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc. ++ still to be processed. */ ++ ++/* Flow Control Constants */ ++#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 ++#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 ++#define FLOW_CONTROL_TYPE 0x8808 ++ ++/* 802.1q VLAN Packet Size */ ++#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ ++ ++/* Receive Address */ ++/* Number of high/low register pairs in the RAR. The RAR (Receive Address ++ * Registers) holds the directed and multicast addresses that we monitor. ++ * Technically, we have 16 spots. However, we reserve one of these spots ++ * (RAR[15]) for our directed address used by controllers with ++ * manageability enabled, allowing us room for 15 multicast addresses. ++ */ ++#define E1000_RAR_ENTRIES 15 ++#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ ++ ++/* Error Codes */ ++#define E1000_SUCCESS 0 ++#define E1000_ERR_NVM 1 ++#define E1000_ERR_PHY 2 ++#define E1000_ERR_CONFIG 3 ++#define E1000_ERR_PARAM 4 ++#define E1000_ERR_MAC_INIT 5 ++#define E1000_ERR_PHY_TYPE 6 ++#define E1000_ERR_RESET 9 ++#define E1000_ERR_MASTER_REQUESTS_PENDING 10 ++#define E1000_ERR_HOST_INTERFACE_COMMAND 11 ++#define E1000_BLK_PHY_RESET 12 ++#define E1000_ERR_SWFW_SYNC 13 ++#define E1000_NOT_IMPLEMENTED 14 ++ ++/* Loop limit on how long we wait for auto-negotiation to complete */ ++#define FIBER_LINK_UP_LIMIT 50 ++#define COPPER_LINK_UP_LIMIT 10 ++#define PHY_AUTO_NEG_LIMIT 45 ++#define PHY_FORCE_LIMIT 20 ++/* Number of 100 microseconds we wait for PCI Express master disable */ ++#define MASTER_DISABLE_TIMEOUT 800 ++/* Number of milliseconds we wait for PHY configuration done after MAC reset */ ++#define PHY_CFG_TIMEOUT 100 ++/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ ++#define MDIO_OWNERSHIP_TIMEOUT 10 ++/* Number of milliseconds for NVM auto read done after MAC reset. */ ++#define AUTO_READ_DONE_TIMEOUT 10 ++ ++/* Flow Control */ ++#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ ++ ++/* Transmit Configuration Word */ ++#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ ++#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ ++#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ ++#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ ++#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ ++ ++/* Receive Configuration Word */ ++#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ ++#define E1000_RXCW_C 0x20000000 /* Receive config */ ++#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ ++ ++/* PCI Express Control */ ++#define E1000_GCR_RXD_NO_SNOOP 0x00000001 ++#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 ++#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 ++#define E1000_GCR_TXD_NO_SNOOP 0x00000008 ++#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 ++#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 ++ ++#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ ++ E1000_GCR_RXDSCW_NO_SNOOP | \ ++ E1000_GCR_RXDSCR_NO_SNOOP | \ ++ E1000_GCR_TXD_NO_SNOOP | \ ++ E1000_GCR_TXDSCW_NO_SNOOP | \ ++ E1000_GCR_TXDSCR_NO_SNOOP) ++ ++/* PHY Control Register */ ++#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ ++#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ ++#define MII_CR_POWER_DOWN 0x0800 /* Power down */ ++#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ ++#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ ++#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ ++#define MII_CR_SPEED_1000 0x0040 ++#define MII_CR_SPEED_100 0x2000 ++#define MII_CR_SPEED_10 0x0000 ++ ++/* PHY Status Register */ ++#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ ++#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ ++ ++/* Autoneg Advertisement Register */ ++#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ ++#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ ++#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ ++#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ ++#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ ++#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ ++ ++/* Link Partner Ability Register (Base Page) */ ++#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ ++#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ ++ ++/* Autoneg Expansion Register */ ++ ++/* 1000BASE-T Control Register */ ++#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ ++#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ ++ /* 0=DTE device */ ++#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ ++ /* 0=Configure PHY as Slave */ ++#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ ++ /* 0=Automatic Master/Slave config */ ++ ++/* 1000BASE-T Status Register */ ++#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ ++#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ ++ ++ ++/* PHY 1000 MII Register/Bit Definitions */ ++/* PHY Registers defined by IEEE */ ++#define PHY_CONTROL 0x00 /* Control Register */ ++#define PHY_STATUS 0x01 /* Status Regiser */ ++#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ ++#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ ++#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ ++#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ ++#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ ++#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ ++ ++/* NVM Control */ ++#define E1000_EECD_SK 0x00000001 /* NVM Clock */ ++#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ ++#define E1000_EECD_DI 0x00000004 /* NVM Data In */ ++#define E1000_EECD_DO 0x00000008 /* NVM Data Out */ ++#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ ++#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ ++#define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ ++#define E1000_EECD_ADDR_BITS 0x00000400 /* NVM Addressing bits based on type ++ * (0-small, 1-large) */ ++#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ ++#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ ++#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ ++#define E1000_EECD_SIZE_EX_SHIFT 11 ++#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ ++#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ ++#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ ++ ++#define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write registers */ ++#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ ++#define E1000_NVM_RW_REG_START 1 /* Start operation */ ++#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ ++#define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ ++#define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ ++#define E1000_FLASH_UPDATES 2000 ++ ++/* NVM Word Offsets */ ++#define NVM_ID_LED_SETTINGS 0x0004 ++#define NVM_INIT_CONTROL2_REG 0x000F ++#define NVM_INIT_CONTROL3_PORT_B 0x0014 ++#define NVM_INIT_3GIO_3 0x001A ++#define NVM_INIT_CONTROL3_PORT_A 0x0024 ++#define NVM_CFG 0x0012 ++#define NVM_CHECKSUM_REG 0x003F ++ ++#define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */ ++#define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */ ++ ++/* Mask bits for fields in Word 0x0f of the NVM */ ++#define NVM_WORD0F_PAUSE_MASK 0x3000 ++#define NVM_WORD0F_PAUSE 0x1000 ++#define NVM_WORD0F_ASM_DIR 0x2000 ++ ++/* Mask bits for fields in Word 0x1a of the NVM */ ++#define NVM_WORD1A_ASPM_MASK 0x000C ++ ++/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ ++#define NVM_SUM 0xBABA ++ ++#define NVM_WORD_SIZE_BASE_SHIFT 6 ++ ++/* NVM Commands - Microwire */ ++ ++/* NVM Commands - SPI */ ++#define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ ++#define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ ++#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ ++#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ ++#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ ++#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ ++ ++/* SPI NVM Status Register */ ++#define NVM_STATUS_RDY_SPI 0x01 ++ ++/* Word definitions for ID LED Settings */ ++#define ID_LED_RESERVED_0000 0x0000 ++#define ID_LED_RESERVED_FFFF 0xFFFF ++#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ ++ (ID_LED_OFF1_OFF2 << 8) | \ ++ (ID_LED_DEF1_DEF2 << 4) | \ ++ (ID_LED_DEF1_DEF2)) ++#define ID_LED_DEF1_DEF2 0x1 ++#define ID_LED_DEF1_ON2 0x2 ++#define ID_LED_DEF1_OFF2 0x3 ++#define ID_LED_ON1_DEF2 0x4 ++#define ID_LED_ON1_ON2 0x5 ++#define ID_LED_ON1_OFF2 0x6 ++#define ID_LED_OFF1_DEF2 0x7 ++#define ID_LED_OFF1_ON2 0x8 ++#define ID_LED_OFF1_OFF2 0x9 ++ ++#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF ++#define IGP_ACTIVITY_LED_ENABLE 0x0300 ++#define IGP_LED3_MODE 0x07000000 ++ ++/* PCI/PCI-X/PCI-EX Config space */ ++#define PCI_HEADER_TYPE_REGISTER 0x0E ++#define PCIE_LINK_STATUS 0x12 ++ ++#define PCI_HEADER_TYPE_MULTIFUNC 0x80 ++#define PCIE_LINK_WIDTH_MASK 0x3F0 ++#define PCIE_LINK_WIDTH_SHIFT 4 ++ ++#define PHY_REVISION_MASK 0xFFFFFFF0 ++#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ ++#define MAX_PHY_MULTI_PAGE_REG 0xF ++ ++/* Bit definitions for valid PHY IDs. */ ++/* I = Integrated ++ * E = External ++ */ ++#define M88E1000_E_PHY_ID 0x01410C50 ++#define M88E1000_I_PHY_ID 0x01410C30 ++#define M88E1011_I_PHY_ID 0x01410C20 ++#define IGP01E1000_I_PHY_ID 0x02A80380 ++#define M88E1111_I_PHY_ID 0x01410CC0 ++#define GG82563_E_PHY_ID 0x01410CA0 ++#define IGP03E1000_E_PHY_ID 0x02A80390 ++#define IFE_E_PHY_ID 0x02A80330 ++#define IFE_PLUS_E_PHY_ID 0x02A80320 ++#define IFE_C_E_PHY_ID 0x02A80310 ++ ++/* M88E1000 Specific Registers */ ++#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ ++#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ ++#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ ++ ++#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ ++#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ ++ ++/* M88E1000 PHY Specific Control Register */ ++#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ ++#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ ++ /* Manual MDI configuration */ ++#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ ++#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, ++ * 100BASE-TX/10BASE-T: ++ * MDI Mode ++ */ ++#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled ++ * all speeds. ++ */ ++ /* 1=Enable Extended 10BASE-T distance ++ * (Lower 10BASE-T RX Threshold) ++ * 0=Normal 10BASE-T RX Threshold */ ++ /* 1=5-Bit interface in 100BASE-TX ++ * 0=MII interface in 100BASE-TX */ ++#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ ++ ++/* M88E1000 PHY Specific Status Register */ ++#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ ++#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ ++#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ ++#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M; ++ * 3=110-140M;4=>140M */ ++#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ ++#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ ++ ++#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 ++ ++/* Number of times we will attempt to autonegotiate before downshifting if we ++ * are the master */ ++#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 ++#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 ++/* Number of times we will attempt to autonegotiate before downshifting if we ++ * are the slave */ ++#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 ++#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 ++#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ ++ ++/* M88EC018 Rev 2 specific DownShift settings */ ++#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 ++#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 ++ ++/* Bits... ++ * 15-5: page ++ * 4-0: register offset ++ */ ++#define GG82563_PAGE_SHIFT 5 ++#define GG82563_REG(page, reg) \ ++ (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) ++#define GG82563_MIN_ALT_REG 30 ++ ++/* GG82563 Specific Registers */ ++#define GG82563_PHY_SPEC_CTRL \ ++ GG82563_REG(0, 16) /* PHY Specific Control */ ++#define GG82563_PHY_PAGE_SELECT \ ++ GG82563_REG(0, 22) /* Page Select */ ++#define GG82563_PHY_SPEC_CTRL_2 \ ++ GG82563_REG(0, 26) /* PHY Specific Control 2 */ ++#define GG82563_PHY_PAGE_SELECT_ALT \ ++ GG82563_REG(0, 29) /* Alternate Page Select */ ++ ++#define GG82563_PHY_MAC_SPEC_CTRL \ ++ GG82563_REG(2, 21) /* MAC Specific Control Register */ ++ ++#define GG82563_PHY_DSP_DISTANCE \ ++ GG82563_REG(5, 26) /* DSP Distance */ ++ ++/* Page 193 - Port Control Registers */ ++#define GG82563_PHY_KMRN_MODE_CTRL \ ++ GG82563_REG(193, 16) /* Kumeran Mode Control */ ++#define GG82563_PHY_PWR_MGMT_CTRL \ ++ GG82563_REG(193, 20) /* Power Management Control */ ++ ++/* Page 194 - KMRN Registers */ ++#define GG82563_PHY_INBAND_CTRL \ ++ GG82563_REG(194, 18) /* Inband Control */ ++ ++/* MDI Control */ ++#define E1000_MDIC_REG_SHIFT 16 ++#define E1000_MDIC_PHY_SHIFT 21 ++#define E1000_MDIC_OP_WRITE 0x04000000 ++#define E1000_MDIC_OP_READ 0x08000000 ++#define E1000_MDIC_READY 0x10000000 ++#define E1000_MDIC_ERROR 0x40000000 ++ ++/* SerDes Control */ ++#define E1000_GEN_POLL_TIMEOUT 640 ++ ++#endif /* _E1000_DEFINES_H_ */ +diff --git a/drivers/net/e1000e/e1000.h b/drivers/net/e1000e/e1000.h +new file mode 100644 +index 0000000..65c31d3 +--- /dev/null ++++ b/drivers/net/e1000e/e1000.h +@@ -0,0 +1,518 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2007 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS <linux.nics@intel.com> ++ e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++/* Linux PRO/1000 Ethernet Driver main header file */ ++ ++#ifndef _E1000_H_ ++#define _E1000_H_ ++ ++#include <linux/netdevice.h> ++#include <linux/ethtool.h> ++#include <linux/pci.h> ++#include <asm/io.h> ++ ++#include "hw.h" ++ ++struct e1000_info; ++ ++#define ndev_printk(level, netdev, format, arg...) \ ++ printk(level "%s: %s: " format, (netdev)->dev.parent->bus_id, \ ++ (netdev)->name, ## arg) ++ ++#ifdef DEBUG ++#define ndev_dbg(netdev, format, arg...) \ ++ ndev_printk(KERN_DEBUG , netdev, format, ## arg) ++#else ++#define ndev_dbg(netdev, format, arg...) do { (void)(netdev); } while (0) ++#endif ++ ++#define ndev_err(netdev, format, arg...) \ ++ ndev_printk(KERN_ERR , netdev, format, ## arg) ++#define ndev_info(netdev, format, arg...) \ ++ ndev_printk(KERN_INFO , netdev, format, ## arg) ++#define ndev_warn(netdev, format, arg...) \ ++ ndev_printk(KERN_WARNING , netdev, format, ## arg) ++#define ndev_notice(netdev, format, arg...) \ ++ ndev_printk(KERN_NOTICE , netdev, format, ## arg) ++ ++ ++/* TX/RX descriptor defines */ ++#define E1000_DEFAULT_TXD 256 ++#define E1000_MAX_TXD 4096 ++#define E1000_MIN_TXD 80 ++ ++#define E1000_DEFAULT_RXD 256 ++#define E1000_MAX_RXD 4096 ++#define E1000_MIN_RXD 80 ++ ++/* Early Receive defines */ ++#define E1000_ERT_2048 0x100 ++ ++#define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ ++ ++/* How many Tx Descriptors do we need to call netif_wake_queue ? */ ++/* How many Rx Buffers do we bundle into one write to the hardware ? */ ++#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */ ++ ++#define AUTO_ALL_MODES 0 ++#define E1000_EEPROM_APME 0x0400 ++ ++#define E1000_MNG_VLAN_NONE (-1) ++ ++/* Number of packet split data buffers (not including the header buffer) */ ++#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) ++ ++enum e1000_boards { ++ board_82571, ++ board_82572, ++ board_82573, ++ board_80003es2lan, ++ board_ich8lan, ++ board_ich9lan, ++}; ++ ++struct e1000_queue_stats { ++ u64 packets; ++ u64 bytes; ++}; ++ ++struct e1000_ps_page { ++ struct page *page; ++ u64 dma; /* must be u64 - written to hw */ ++}; ++ ++/* ++ * wrappers around a pointer to a socket buffer, ++ * so a DMA handle can be stored along with the buffer ++ */ ++struct e1000_buffer { ++ dma_addr_t dma; ++ struct sk_buff *skb; ++ union { ++ /* TX */ ++ struct { ++ unsigned long time_stamp; ++ u16 length; ++ u16 next_to_watch; ++ }; ++ /* RX */ ++ struct page *page; ++ }; ++ ++}; ++ ++struct e1000_ring { ++ void *desc; /* pointer to ring memory */ ++ dma_addr_t dma; /* phys address of ring */ ++ unsigned int size; /* length of ring in bytes */ ++ unsigned int count; /* number of desc. in ring */ ++ ++ u16 next_to_use; ++ u16 next_to_clean; ++ ++ u16 head; ++ u16 tail; ++ ++ /* array of buffer information structs */ ++ struct e1000_buffer *buffer_info; ++ ++ union { ++ /* for TX */ ++ struct { ++ bool last_tx_tso; /* used to mark tso desc. */ ++ }; ++ /* for RX */ ++ struct { ++ /* arrays of page information for packet split */ ++ struct e1000_ps_page *ps_pages; ++ struct sk_buff *rx_skb_top; ++ }; ++ }; ++ ++ struct e1000_queue_stats stats; ++}; ++ ++/* board specific private data structure */ ++struct e1000_adapter { ++ struct timer_list watchdog_timer; ++ struct timer_list phy_info_timer; ++ struct timer_list blink_timer; ++ ++ struct work_struct reset_task; ++ struct work_struct watchdog_task; ++ ++ const struct e1000_info *ei; ++ ++ struct vlan_group *vlgrp; ++ u32 bd_number; ++ u32 rx_buffer_len; ++ u16 mng_vlan_id; ++ u16 link_speed; ++ u16 link_duplex; ++ ++ spinlock_t tx_queue_lock; /* prevent concurrent tail updates */ ++ ++ /* this is still needed for 82571 and above */ ++ atomic_t irq_sem; ++ ++ /* track device up/down/testing state */ ++ unsigned long state; ++ ++ /* Interrupt Throttle Rate */ ++ u32 itr; ++ u32 itr_setting; ++ u16 tx_itr; ++ u16 rx_itr; ++ ++ /* ++ * TX ++ */ ++ struct e1000_ring *tx_ring /* One per active queue */ ++ ____cacheline_aligned_in_smp; ++ ++ unsigned long tx_queue_len; ++ unsigned int restart_queue; ++ u32 txd_cmd; ++ ++ bool detect_tx_hung; ++ u8 tx_timeout_factor; ++ ++ u32 tx_int_delay; ++ u32 tx_abs_int_delay; ++ ++ unsigned int total_tx_bytes; ++ unsigned int total_tx_packets; ++ unsigned int total_rx_bytes; ++ unsigned int total_rx_packets; ++ ++ /* TX stats */ ++ u64 tpt_old; ++ u64 colc_old; ++ u64 gotcl_old; ++ u32 gotcl; ++ u32 tx_timeout_count; ++ u32 tx_fifo_head; ++ u32 tx_head_addr; ++ u32 tx_fifo_size; ++ ++ /* ++ * RX ++ */ ++ bool (*clean_rx) (struct e1000_adapter *adapter, ++ int *work_done, int work_to_do) ++ ____cacheline_aligned_in_smp; ++ void (*alloc_rx_buf) (struct e1000_adapter *adapter, ++ int cleaned_count); ++ struct e1000_ring *rx_ring; ++ ++ u32 rx_int_delay; ++ u32 rx_abs_int_delay; ++ ++ /* RX stats */ ++ u64 hw_csum_err; ++ u64 hw_csum_good; ++ u64 rx_hdr_split; ++ u64 gorcl_old; ++ u32 gorcl; ++ u32 alloc_rx_buff_failed; ++ ++ unsigned int rx_ps_pages; ++ u16 rx_ps_bsize0; ++ ++ /* OS defined structs */ ++ struct net_device *netdev; ++ struct pci_dev *pdev; ++ struct net_device_stats net_stats; ++ spinlock_t stats_lock; /* prevent concurrent stats updates */ ++ ++ /* structs defined in e1000_hw.h */ ++ struct e1000_hw hw; ++ ++ struct e1000_hw_stats stats; ++ struct e1000_phy_info phy_info; ++ struct e1000_phy_stats phy_stats; ++ ++ struct e1000_ring test_tx_ring; ++ struct e1000_ring test_rx_ring; ++ u32 test_icr; ++ ++ u32 msg_enable; ++ ++ u32 eeprom_wol; ++ u32 wol; ++ u32 pba; ++ ++ u8 fc_autoneg; ++ ++ unsigned long led_status; ++ ++ unsigned int flags; ++}; ++ ++struct e1000_info { ++ enum e1000_mac_type mac; ++ unsigned int flags; ++ u32 pba; ++ s32 (*get_invariants)(struct e1000_adapter *); ++ struct e1000_mac_operations *mac_ops; ++ struct e1000_phy_operations *phy_ops; ++ struct e1000_nvm_operations *nvm_ops; ++}; ++ ++/* hardware capability, feature, and workaround flags */ ++#define FLAG_HAS_AMT (1 << 0) ++#define FLAG_HAS_FLASH (1 << 1) ++#define FLAG_HAS_HW_VLAN_FILTER (1 << 2) ++#define FLAG_HAS_WOL (1 << 3) ++#define FLAG_HAS_ERT (1 << 4) ++#define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5) ++#define FLAG_HAS_SWSM_ON_LOAD (1 << 6) ++#define FLAG_HAS_JUMBO_FRAMES (1 << 7) ++#define FLAG_HAS_ASPM (1 << 8) ++#define FLAG_HAS_STATS_ICR_ICT (1 << 9) ++#define FLAG_HAS_STATS_PTC_PRC (1 << 10) ++#define FLAG_HAS_SMART_POWER_DOWN (1 << 11) ++#define FLAG_IS_QUAD_PORT_A (1 << 12) ++#define FLAG_IS_QUAD_PORT (1 << 13) ++#define FLAG_TIPG_MEDIUM_FOR_80003ESLAN (1 << 14) ++#define FLAG_APME_IN_WUC (1 << 15) ++#define FLAG_APME_IN_CTRL3 (1 << 16) ++#define FLAG_APME_CHECK_PORT_B (1 << 17) ++#define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18) ++#define FLAG_NO_WAKE_UCAST (1 << 19) ++#define FLAG_MNG_PT_ENABLED (1 << 20) ++#define FLAG_RESET_OVERWRITES_LAA (1 << 21) ++#define FLAG_TARC_SPEED_MODE_BIT (1 << 22) ++#define FLAG_TARC_SET_BIT_ZERO (1 << 23) ++#define FLAG_RX_NEEDS_RESTART (1 << 24) ++#define FLAG_LSC_GIG_SPEED_DROP (1 << 25) ++#define FLAG_SMART_POWER_DOWN (1 << 26) ++#define FLAG_MSI_ENABLED (1 << 27) ++#define FLAG_RX_CSUM_ENABLED (1 << 28) ++#define FLAG_TSO_FORCE (1 << 29) ++ ++#define E1000_RX_DESC_PS(R, i) \ ++ (&(((union e1000_rx_desc_packet_split *)((R).desc))[i])) ++#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) ++#define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc) ++#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc) ++#define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc) ++ ++enum e1000_state_t { ++ __E1000_TESTING, ++ __E1000_RESETTING, ++ __E1000_DOWN ++}; ++ ++enum latency_range { ++ lowest_latency = 0, ++ low_latency = 1, ++ bulk_latency = 2, ++ latency_invalid = 255 ++}; ++ ++extern char e1000_driver_name[]; ++extern const char e1000_driver_version[]; ++ ++extern void e1000_check_options(struct e1000_adapter *adapter); ++extern void e1000_set_ethtool_ops(struct net_device *netdev); ++ ++extern int e1000_up(struct e1000_adapter *adapter); ++extern void e1000_down(struct e1000_adapter *adapter); ++extern void e1000_reinit_locked(struct e1000_adapter *adapter); ++extern void e1000_reset(struct e1000_adapter *adapter); ++extern void e1000_power_up_phy(struct e1000_adapter *adapter); ++extern int e1000_setup_rx_resources(struct e1000_adapter *adapter); ++extern int e1000_setup_tx_resources(struct e1000_adapter *adapter); ++extern void e1000_free_rx_resources(struct e1000_adapter *adapter); ++extern void e1000_free_tx_resources(struct e1000_adapter *adapter); ++extern void e1000_update_stats(struct e1000_adapter *adapter); ++ ++extern unsigned int copybreak; ++ ++extern char *e1000_get_hw_dev_name(struct e1000_hw *hw); ++ ++extern struct e1000_info e1000_82571_info; ++extern struct e1000_info e1000_82572_info; ++extern struct e1000_info e1000_82573_info; ++extern struct e1000_info e1000_ich8_info; ++extern struct e1000_info e1000_ich9_info; ++extern struct e1000_info e1000_es2_info; ++ ++extern s32 e1000_commit_phy(struct e1000_hw *hw); ++extern s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active); ++ ++extern bool e1000_enable_mng_pass_thru(struct e1000_hw *hw); ++ ++extern bool e1000_get_laa_state_82571(struct e1000_hw *hw); ++extern void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state); ++ ++extern void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, ++ bool state); ++extern void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); ++extern void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw); ++ ++extern s32 e1000_check_for_copper_link(struct e1000_hw *hw); ++extern s32 e1000_check_for_fiber_link(struct e1000_hw *hw); ++extern s32 e1000_check_for_serdes_link(struct e1000_hw *hw); ++extern s32 e1000_cleanup_led_generic(struct e1000_hw *hw); ++extern s32 e1000_led_on_generic(struct e1000_hw *hw); ++extern s32 e1000_led_off_generic(struct e1000_hw *hw); ++extern s32 e1000_get_bus_info_pcie(struct e1000_hw *hw); ++extern s32 e1000_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex); ++extern s32 e1000_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex); ++extern s32 e1000_disable_pcie_master(struct e1000_hw *hw); ++extern s32 e1000_get_auto_rd_done(struct e1000_hw *hw); ++extern s32 e1000_id_led_init(struct e1000_hw *hw); ++extern void e1000_clear_hw_cntrs_base(struct e1000_hw *hw); ++extern s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw); ++extern s32 e1000_copper_link_setup_m88(struct e1000_hw *hw); ++extern s32 e1000_copper_link_setup_igp(struct e1000_hw *hw); ++extern s32 e1000_setup_link(struct e1000_hw *hw); ++extern void e1000_clear_vfta(struct e1000_hw *hw); ++extern void e1000_init_rx_addrs(struct e1000_hw *hw, u16 rar_count); ++extern void e1000_mc_addr_list_update_generic(struct e1000_hw *hw, ++ u8 *mc_addr_list, u32 mc_addr_count, ++ u32 rar_used_count, u32 rar_count); ++extern void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index); ++extern s32 e1000_set_fc_watermarks(struct e1000_hw *hw); ++extern void e1000_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop); ++extern s32 e1000_get_hw_semaphore(struct e1000_hw *hw); ++extern s32 e1000_valid_led_default(struct e1000_hw *hw, u16 *data); ++extern void e1000_config_collision_dist(struct e1000_hw *hw); ++extern s32 e1000_config_fc_after_link_up(struct e1000_hw *hw); ++extern s32 e1000_force_mac_fc(struct e1000_hw *hw); ++extern s32 e1000_blink_led(struct e1000_hw *hw); ++extern void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value); ++extern void e1000_reset_adaptive(struct e1000_hw *hw); ++extern void e1000_update_adaptive(struct e1000_hw *hw); ++ ++extern s32 e1000_setup_copper_link(struct e1000_hw *hw); ++extern s32 e1000_get_phy_id(struct e1000_hw *hw); ++extern void e1000_put_hw_semaphore(struct e1000_hw *hw); ++extern s32 e1000_check_reset_block_generic(struct e1000_hw *hw); ++extern s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw); ++extern s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw); ++extern s32 e1000_get_phy_info_igp(struct e1000_hw *hw); ++extern s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); ++extern s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw); ++extern s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active); ++extern s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); ++extern s32 e1000_phy_sw_reset(struct e1000_hw *hw); ++extern s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw); ++extern s32 e1000_get_cfg_done(struct e1000_hw *hw); ++extern s32 e1000_get_cable_length_m88(struct e1000_hw *hw); ++extern s32 e1000_get_phy_info_m88(struct e1000_hw *hw); ++extern s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); ++extern s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); ++extern enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id); ++extern void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); ++extern s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data); ++extern s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data); ++extern s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, ++ u32 usec_interval, bool *success); ++extern s32 e1000_phy_reset_dsp(struct e1000_hw *hw); ++extern s32 e1000_check_downshift(struct e1000_hw *hw); ++extern s32 e1000_wait_autoneg(struct e1000_hw *hw); ++ ++static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw) ++{ ++ return hw->phy.ops.reset_phy(hw); ++} ++ ++static inline s32 e1000_check_reset_block(struct e1000_hw *hw) ++{ ++ return hw->phy.ops.check_reset_block(hw); ++} ++ ++static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data) ++{ ++ return hw->phy.ops.read_phy_reg(hw, offset, data); ++} ++ ++static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data) ++{ ++ return hw->phy.ops.write_phy_reg(hw, offset, data); ++} ++ ++static inline s32 e1000_get_cable_length(struct e1000_hw *hw) ++{ ++ return hw->phy.ops.get_cable_length(hw); ++} ++ ++extern s32 e1000_acquire_nvm(struct e1000_hw *hw); ++extern s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); ++extern s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw); ++extern s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg); ++extern s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); ++extern s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); ++extern s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw); ++extern void e1000_release_nvm(struct e1000_hw *hw); ++extern void e1000_reload_nvm(struct e1000_hw *hw); ++extern s32 e1000_read_mac_addr(struct e1000_hw *hw); ++ ++static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw) ++{ ++ return hw->nvm.ops.validate_nvm(hw); ++} ++ ++static inline s32 e1000_update_nvm_checksum(struct e1000_hw *hw) ++{ ++ return hw->nvm.ops.update_nvm(hw); ++} ++ ++static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) ++{ ++ return hw->nvm.ops.read_nvm(hw, offset, words, data); ++} ++ ++static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) ++{ ++ return hw->nvm.ops.write_nvm(hw, offset, words, data); ++} ++ ++static inline s32 e1000_get_phy_info(struct e1000_hw *hw) ++{ ++ return hw->phy.ops.get_phy_info(hw); ++} ++ ++extern bool e1000_check_mng_mode(struct e1000_hw *hw); ++extern bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw); ++extern s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length); ++ ++static inline u32 __er32(struct e1000_hw *hw, unsigned long reg) ++{ ++ return readl(hw->hw_addr + reg); ++} ++ ++static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) ++{ ++ writel(val, hw->hw_addr + reg); ++} ++ ++#endif /* _E1000_H_ */ +diff --git a/drivers/net/e1000e/es2lan.c b/drivers/net/e1000e/es2lan.c +new file mode 100644 +index 0000000..b5143e9 +--- /dev/null ++++ b/drivers/net/e1000e/es2lan.c +@@ -0,0 +1,1255 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2007 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS <linux.nics@intel.com> ++ e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++/* ++ * 80003ES2LAN Gigabit Ethernet Controller (Copper) ++ * 80003ES2LAN Gigabit Ethernet Controller (Serdes) ++ */ ++ ++#include "e1000.h" ++ ++#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00 ++#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02 ++#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10 ++ ++#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008 ++#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800 ++#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010 ++ ++#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004 ++#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000 ++ ++#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ ++#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000 ++ ++#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8 ++#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9 ++ ++/* GG82563 PHY Specific Status Register (Page 0, Register 16 */ ++#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disab. */ ++#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 ++#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */ ++#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */ ++#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */ ++ ++/* PHY Specific Control Register 2 (Page 0, Register 26) */ ++#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 ++ /* 1=Reverse Auto-Negotiation */ ++ ++/* MAC Specific Control Register (Page 2, Register 21) */ ++/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ ++#define GG82563_MSCR_TX_CLK_MASK 0x0007 ++#define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004 ++#define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005 ++#define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007 ++ ++#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ ++ ++/* DSP Distance Register (Page 5, Register 26) */ ++#define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M ++ 1 = 50-80M ++ 2 = 80-110M ++ 3 = 110-140M ++ 4 = >140M */ ++ ++/* Kumeran Mode Control Register (Page 193, Register 16) */ ++#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 ++ ++/* Power Management Control Register (Page 193, Register 20) */ ++#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 ++ /* 1=Enable SERDES Electrical Idle */ ++ ++/* In-Band Control Register (Page 194, Register 18) */ ++#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */ ++ ++/* A table for the GG82563 cable length where the range is defined ++ * with a lower bound at "index" and the upper bound at ++ * "index + 5". ++ */ ++static const u16 e1000_gg82563_cable_length_table[] = ++ { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF }; ++ ++static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw); ++static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); ++static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); ++static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw); ++static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw); ++static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw); ++static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex); ++ ++/** ++ * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. ++ * @hw: pointer to the HW structure ++ * ++ * This is a function pointer entry point called by the api module. ++ **/ ++static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (hw->media_type != e1000_media_type_copper) { ++ phy->type = e1000_phy_none; ++ goto out; ++ } ++ ++ phy->addr = 1; ++ phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; ++ phy->reset_delay_us = 100; ++ phy->type = e1000_phy_gg82563; ++ ++ /* This can only be done after all function pointers are setup. */ ++ ret_val = e1000_get_phy_id(hw); ++ ++ /* Verify phy id */ ++ if (phy->id != GG82563_E_PHY_ID) { ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs. ++ * @hw: pointer to the HW structure ++ * ++ * This is a function pointer entry point called by the api module. ++ **/ ++static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ u32 eecd = er32(EECD); ++ u16 size; ++ ++ nvm->opcode_bits = 8; ++ nvm->delay_usec = 1; ++ switch (nvm->override) { ++ case e1000_nvm_override_spi_large: ++ nvm->page_size = 32; ++ nvm->address_bits = 16; ++ break; ++ case e1000_nvm_override_spi_small: ++ nvm->page_size = 8; ++ nvm->address_bits = 8; ++ break; ++ default: ++ nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; ++ nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; ++ break; ++ } ++ ++ nvm->type = e1000_nvm_eeprom_spi; ++ ++ size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> ++ E1000_EECD_SIZE_EX_SHIFT); ++ ++ /* Added to a constant, "size" becomes the left-shift value ++ * for setting word_size. ++ */ ++ size += NVM_WORD_SIZE_BASE_SHIFT; ++ nvm->word_size = 1 << size; ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. ++ * @hw: pointer to the HW structure ++ * ++ * This is a function pointer entry point called by the api module. ++ **/ ++static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ struct e1000_mac_info *mac = &hw->mac; ++ struct e1000_mac_operations *func = &mac->ops; ++ s32 ret_val = E1000_SUCCESS; ++ ++ /* Set media type */ ++ switch (adapter->pdev->device) { ++ case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: ++ hw->media_type = e1000_media_type_internal_serdes; ++ break; ++ default: ++ hw->media_type = e1000_media_type_copper; ++ break; ++ } ++ ++ /* Set mta register count */ ++ mac->mta_reg_count = 128; ++ /* Set rar entry count */ ++ mac->rar_entry_count = E1000_RAR_ENTRIES; ++ /* Set if manageability features are enabled. */ ++ mac->arc_subsystem_valid = ++ (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0; ++ ++ /* check for link */ ++ switch (hw->media_type) { ++ case e1000_media_type_copper: ++ func->setup_physical_interface = e1000_setup_copper_link_80003es2lan; ++ func->check_for_link = e1000_check_for_copper_link; ++ break; ++ case e1000_media_type_fiber: ++ func->setup_physical_interface = e1000_setup_fiber_serdes_link; ++ func->check_for_link = e1000_check_for_fiber_link; ++ break; ++ case e1000_media_type_internal_serdes: ++ func->setup_physical_interface = e1000_setup_fiber_serdes_link; ++ func->check_for_link = e1000_check_for_serdes_link; ++ break; ++ default: ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ break; ++ } ++ ++out: ++ return ret_val; ++} ++ ++static s32 e1000_get_invariants_80003es2lan(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ s32 rc; ++ ++ rc = e1000_init_mac_params_80003es2lan(adapter); ++ if (rc) ++ return rc; ++ ++ rc = e1000_init_nvm_params_80003es2lan(hw); ++ if (rc) ++ return rc; ++ ++ rc = e1000_init_phy_params_80003es2lan(hw); ++ if (rc) ++ return rc; ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY ++ * @hw: pointer to the HW structure ++ * ++ * A wrapper to acquire access rights to the correct PHY. This is a ++ * function pointer entry point called by the api module. ++ **/ ++static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) ++{ ++ u16 mask; ++ ++ mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; ++ ++ return e1000_acquire_swfw_sync_80003es2lan(hw, mask); ++} ++ ++/** ++ * e1000_release_phy_80003es2lan - Release rights to access PHY ++ * @hw: pointer to the HW structure ++ * ++ * A wrapper to release access rights to the correct PHY. This is a ++ * function pointer entry point called by the api module. ++ **/ ++static void e1000_release_phy_80003es2lan(struct e1000_hw *hw) ++{ ++ u16 mask; ++ ++ mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; ++ e1000_release_swfw_sync_80003es2lan(hw, mask); ++} ++ ++/** ++ * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM ++ * @hw: pointer to the HW structure ++ * ++ * Acquire the semaphore to access the EEPROM. This is a function ++ * pointer entry point called by the api module. ++ **/ ++static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) ++{ ++ s32 ret_val; ++ ++ ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000_acquire_nvm(hw); ++ ++ if (ret_val) ++ e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM ++ * @hw: pointer to the HW structure ++ * ++ * Release the semaphore used to access the EEPROM. This is a ++ * function pointer entry point called by the api module. ++ **/ ++static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw) ++{ ++ e1000_release_nvm(hw); ++ e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); ++} ++ ++/** ++ * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore ++ * @hw: pointer to the HW structure ++ * @mask: specifies which semaphore to acquire ++ * ++ * Acquire the SW/FW semaphore to access the PHY or NVM. The mask ++ * will also specify which port we're acquiring the lock for. ++ **/ ++static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) ++{ ++ u32 swfw_sync; ++ u32 swmask = mask; ++ u32 fwmask = mask << 16; ++ s32 ret_val = E1000_SUCCESS; ++ s32 i = 0; ++ s32 timeout = 200; ++ ++ while (i < timeout) { ++ if (e1000_get_hw_semaphore(hw)) { ++ ret_val = -E1000_ERR_SWFW_SYNC; ++ goto out; ++ } ++ ++ swfw_sync = er32(SW_FW_SYNC); ++ if (!(swfw_sync & (fwmask | swmask))) ++ break; ++ ++ /* Firmware currently using resource (fwmask) ++ * or other software thread using resource (swmask) */ ++ e1000_put_hw_semaphore(hw); ++ mdelay(5); ++ i++; ++ } ++ ++ if (i == timeout) { ++ hw_dbg(hw, ++ "Driver can't access resource, SW_FW_SYNC timeout.\n"); ++ ret_val = -E1000_ERR_SWFW_SYNC; ++ goto out; ++ } ++ ++ swfw_sync |= swmask; ++ ew32(SW_FW_SYNC, swfw_sync); ++ ++ e1000_put_hw_semaphore(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore ++ * @hw: pointer to the HW structure ++ * @mask: specifies which semaphore to acquire ++ * ++ * Release the SW/FW semaphore used to access the PHY or NVM. The mask ++ * will also specify which port we're releasing the lock for. ++ **/ ++static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) ++{ ++ u32 swfw_sync; ++ ++ while (e1000_get_hw_semaphore(hw) != E1000_SUCCESS); ++ /* Empty */ ++ ++ swfw_sync = er32(SW_FW_SYNC); ++ swfw_sync &= ~mask; ++ ew32(SW_FW_SYNC, swfw_sync); ++ ++ e1000_put_hw_semaphore(hw); ++} ++ ++/** ++ * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register ++ * @hw: pointer to the HW structure ++ * @offset: offset of the register to read ++ * @data: pointer to the data returned from the operation ++ * ++ * Read the GG82563 PHY register. This is a function pointer entry ++ * point called by the api module. ++ **/ ++static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, ++ u32 offset, u16 *data) ++{ ++ s32 ret_val; ++ u32 page_select; ++ u16 temp; ++ ++ /* Select Configuration Page */ ++ if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) ++ page_select = GG82563_PHY_PAGE_SELECT; ++ else ++ /* Use Alternative Page Select register to access ++ * registers 30 and 31 ++ */ ++ page_select = GG82563_PHY_PAGE_SELECT_ALT; ++ ++ temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); ++ ret_val = e1000_write_phy_reg_m88(hw, page_select, temp); ++ if (ret_val) ++ goto out; ++ ++ /* The "ready" bit in the MDIC register may be incorrectly set ++ * before the device has completed the "Page Select" MDI ++ * transaction. So we wait 200us after each MDI command... ++ */ ++ udelay(200); ++ ++ /* ...and verify the command was successful. */ ++ ret_val = e1000_read_phy_reg_m88(hw, page_select, &temp); ++ ++ if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ ++ udelay(200); ++ ++ ret_val = e1000_read_phy_reg_m88(hw, ++ MAX_PHY_REG_ADDRESS & offset, ++ data); ++ ++ udelay(200); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register ++ * @hw: pointer to the HW structure ++ * @offset: offset of the register to read ++ * @data: value to write to the register ++ * ++ * Write to the GG82563 PHY register. This is a function pointer entry ++ * point called by the api module. ++ **/ ++static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, ++ u32 offset, u16 data) ++{ ++ s32 ret_val; ++ u32 page_select; ++ u16 temp; ++ ++ /* Select Configuration Page */ ++ if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) ++ page_select = GG82563_PHY_PAGE_SELECT; ++ else ++ /* Use Alternative Page Select register to access ++ * registers 30 and 31 ++ */ ++ page_select = GG82563_PHY_PAGE_SELECT_ALT; ++ ++ temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); ++ ret_val = e1000_write_phy_reg_m88(hw, page_select, temp); ++ if (ret_val) ++ goto out; ++ ++ ++ /* The "ready" bit in the MDIC register may be incorrectly set ++ * before the device has completed the "Page Select" MDI ++ * transaction. So we wait 200us after each MDI command... ++ */ ++ udelay(200); ++ ++ /* ...and verify the command was successful. */ ++ ret_val = e1000_read_phy_reg_m88(hw, page_select, &temp); ++ ++ if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ ++ udelay(200); ++ ++ ret_val = e1000_write_phy_reg_m88(hw, ++ MAX_PHY_REG_ADDRESS & offset, ++ data); ++ ++ udelay(200); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_write_nvm_80003es2lan - Write to ESB2 NVM ++ * @hw: pointer to the HW structure ++ * @offset: offset of the register to read ++ * @words: number of words to write ++ * @data: buffer of data to write to the NVM ++ * ++ * Write "words" of data to the ESB2 NVM. This is a function ++ * pointer entry point called by the api module. ++ **/ ++static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, ++ u16 words, u16 *data) ++{ ++ return e1000_write_nvm_spi(hw, offset, words, data); ++} ++ ++/** ++ * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete ++ * @hw: pointer to the HW structure ++ * ++ * Wait a specific amount of time for manageability processes to complete. ++ * This is a function pointer entry point called by the phy module. ++ **/ ++static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) ++{ ++ s32 timeout = PHY_CFG_TIMEOUT; ++ s32 ret_val = E1000_SUCCESS; ++ u32 mask = E1000_NVM_CFG_DONE_PORT_0; ++ ++ if (hw->bus.func == 1) ++ mask = E1000_NVM_CFG_DONE_PORT_1; ++ ++ while (timeout) { ++ if (er32(EEMNGCTL) & mask) ++ break; ++ msleep(1); ++ timeout--; ++ } ++ if (!timeout) { ++ hw_dbg(hw, "MNG configuration cycle has not completed.\n"); ++ ret_val = -E1000_ERR_RESET; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex ++ * @hw: pointer to the HW structure ++ * ++ * Force the speed and duplex settings onto the PHY. This is a ++ * function pointer entry point called by the phy module. ++ **/ ++static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) ++{ ++ s32 ret_val; ++ u16 phy_data; ++ bool link; ++ ++ /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI ++ * forced whenever speed and duplex are forced. ++ */ ++ ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; ++ ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data); ++ if (ret_val) ++ goto out; ++ ++ hw_dbg(hw, "GG82563 PSCR: %X\n", phy_data); ++ ++ ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ e1000_phy_force_speed_duplex_setup(hw, &phy_data); ++ ++ /* Reset the phy to commit changes. */ ++ phy_data |= MII_CR_RESET; ++ ++ ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); ++ if (ret_val) ++ goto out; ++ ++ udelay(1); ++ ++ if (hw->phy.wait_for_link) { ++ hw_dbg(hw, "Waiting for forced speed/duplex link " ++ "on GG82563 phy.\n"); ++ ++ ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, ++ 100000, &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) { ++ /* We didn't get link. ++ * Reset the DSP and cross our fingers. ++ */ ++ ret_val = e1000_phy_reset_dsp(hw); ++ if (ret_val) ++ goto out; ++ } ++ ++ /* Try once more */ ++ ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, ++ 100000, &link); ++ if (ret_val) ++ goto out; ++ } ++ ++ ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ /* Resetting the phy means we need to verify the TX_CLK corresponds ++ * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. ++ */ ++ phy_data &= ~GG82563_MSCR_TX_CLK_MASK; ++ if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) ++ phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5; ++ else ++ phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; ++ ++ /* In addition, we must re-enable CRS on Tx for both half and full ++ * duplex. ++ */ ++ phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; ++ ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_cable_length_80003es2lan - Set approximate cable length ++ * @hw: pointer to the HW structure ++ * ++ * Find the approximate cable length as measured by the GG82563 PHY. ++ * This is a function pointer entry point called by the phy module. ++ **/ ++static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_data; ++ u16 index; ++ ++ ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ index = phy_data & GG82563_DSPD_CABLE_LENGTH; ++ phy->min_cable_length = e1000_gg82563_cable_length_table[index]; ++ phy->max_cable_length = e1000_gg82563_cable_length_table[index+5]; ++ ++ phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_link_up_info_80003es2lan - Report speed and duplex ++ * @hw: pointer to the HW structure ++ * @speed: pointer to speed buffer ++ * @duplex: pointer to duplex buffer ++ * ++ * Retrieve the current speed and duplex configuration. ++ * This is a function pointer entry point called by the api module. ++ **/ ++static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, ++ u16 *duplex) ++{ ++ s32 ret_val; ++ ++ if (hw->media_type == e1000_media_type_copper) { ++ ret_val = e1000_get_speed_and_duplex_copper(hw, ++ speed, ++ duplex); ++ if (ret_val) ++ goto out; ++ if (*speed == SPEED_1000) ++ ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); ++ else ++ ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, ++ *duplex); ++ } else { ++ ret_val = e1000_get_speed_and_duplex_fiber_serdes(hw, ++ speed, ++ duplex); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_reset_hw_80003es2lan - Reset the ESB2 controller ++ * @hw: pointer to the HW structure ++ * ++ * Perform a global reset to the ESB2 controller. ++ * This is a function pointer entry point called by the api module. ++ **/ ++static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ u32 icr; ++ s32 ret_val; ++ ++ /* Prevent the PCI-E bus from sticking if there is no TLP connection ++ * on the last TLP read/write transaction when MAC is reset. ++ */ ++ ret_val = e1000_disable_pcie_master(hw); ++ if (ret_val) ++ hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); ++ ++ hw_dbg(hw, "Masking off all interrupts\n"); ++ ew32(IMC, 0xffffffff); ++ ++ ew32(RCTL, 0); ++ ew32(TCTL, E1000_TCTL_PSP); ++ e1e_flush(); ++ ++ msleep(10); ++ ++ ctrl = er32(CTRL); ++ ++ hw_dbg(hw, "Issuing a global reset to MAC\n"); ++ ew32(CTRL, ctrl | E1000_CTRL_RST); ++ ++ ret_val = e1000_get_auto_rd_done(hw); ++ if (ret_val) ++ /* We don't want to continue accessing MAC registers. */ ++ goto out; ++ ++ /* Clear any pending interrupt events. */ ++ ew32(IMC, 0xffffffff); ++ icr = er32(ICR); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_init_hw_80003es2lan - Initialize the ESB2 controller ++ * @hw: pointer to the HW structure ++ * ++ * Initialize the hw bits, LED, VFTA, MTA, link and hw counters. ++ * This is a function pointer entry point called by the api module. ++ **/ ++static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 reg_data; ++ s32 ret_val; ++ u16 i; ++ ++ e1000_initialize_hw_bits_80003es2lan(hw); ++ ++ /* Initialize identification LED */ ++ ret_val = e1000_id_led_init(hw); ++ if (ret_val) { ++ hw_dbg(hw, "Error initializing identification LED\n"); ++ goto out; ++ } ++ ++ /* Disabling VLAN filtering */ ++ hw_dbg(hw, "Initializing the IEEE VLAN\n"); ++ e1000_clear_vfta(hw); ++ ++ /* Setup the receive address. */ ++ e1000_init_rx_addrs(hw, mac->rar_entry_count); ++ ++ /* Zero out the Multicast HASH table */ ++ hw_dbg(hw, "Zeroing the MTA\n"); ++ for (i = 0; i < mac->mta_reg_count; i++) ++ E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); ++ ++ /* Setup link and flow control */ ++ ret_val = e1000_setup_link(hw); ++ ++ /* Set the transmit descriptor write-back policy */ ++ reg_data = er32(TXDCTL); ++ reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | ++ E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; ++ ew32(TXDCTL, reg_data); ++ ++ /* ...for both queues. */ ++ reg_data = er32(TXDCTL1); ++ reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | ++ E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; ++ ew32(TXDCTL1, reg_data); ++ ++ /* Enable retransmit on late collisions */ ++ reg_data = er32(TCTL); ++ reg_data |= E1000_TCTL_RTLC; ++ ew32(TCTL, reg_data); ++ ++ /* Configure Gigabit Carry Extend Padding */ ++ reg_data = er32(TCTL_EXT); ++ reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; ++ reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; ++ ew32(TCTL_EXT, reg_data); ++ ++ /* Configure Transmit Inter-Packet Gap */ ++ reg_data = er32(TIPG); ++ reg_data &= ~E1000_TIPG_IPGT_MASK; ++ reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; ++ ew32(TIPG, reg_data); ++ ++ reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); ++ reg_data &= ~0x00100000; ++ E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); ++ ++ /* Clear all of the statistics registers (clear on read). It is ++ * important that we do this after we have tried to establish link ++ * because the symbol error count will increment wildly if there ++ * is no link. ++ */ ++ e1000_clear_hw_cntrs_80003es2lan(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 ++ * @hw: pointer to the HW structure ++ * ++ * Initializes required hardware-dependent bits needed for normal operation. ++ **/ ++static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) ++{ ++ u32 reg; ++ ++ /* Transmit Descriptor Control 0 */ ++ reg = er32(TXDCTL); ++ reg |= (1 << 22); ++ ew32(TXDCTL, reg); ++ ++ /* Transmit Descriptor Control 1 */ ++ reg = er32(TXDCTL1); ++ reg |= (1 << 22); ++ ew32(TXDCTL1, reg); ++ ++ /* Transmit Arbitration Control 0 */ ++ reg = er32(TARC0); ++ reg &= ~(0xF << 27); /* 30:27 */ ++ if (hw->media_type != e1000_media_type_copper) ++ reg &= ~(1 << 20); ++ ew32(TARC0, reg); ++ ++ /* Transmit Arbitration Control 1 */ ++ reg = er32(TARC1); ++ if (er32(TCTL) & E1000_TCTL_MULR) ++ reg &= ~(1 << 28); ++ else ++ reg |= (1 << 28); ++ ew32(TARC1, reg); ++} ++ ++/** ++ * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link ++ * @hw: pointer to the HW structure ++ * ++ * Setup some GG82563 PHY registers for obtaining link ++ **/ ++static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u32 ctrl_ext; ++ u16 data; ++ ++ ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data |= GG82563_MSCR_ASSERT_CRS_ON_TX; ++ /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ ++ data |= GG82563_MSCR_TX_CLK_1000MBPS_25; ++ ++ ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, ++ data); ++ if (ret_val) ++ goto out; ++ ++ /* Options: ++ * MDI/MDI-X = 0 (default) ++ * 0 - Auto for all speeds ++ * 1 - MDI mode ++ * 2 - MDI-X mode ++ * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) ++ */ ++ ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; ++ ++ switch (phy->mdix) { ++ case 1: ++ data |= GG82563_PSCR_CROSSOVER_MODE_MDI; ++ break; ++ case 2: ++ data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; ++ break; ++ case 0: ++ default: ++ data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; ++ break; ++ } ++ ++ /* Options: ++ * disable_polarity_correction = 0 (default) ++ * Automatic Correction for Reversed Cable Polarity ++ * 0 - Disabled ++ * 1 - Enabled ++ */ ++ data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; ++ if (phy->disable_polarity_correction) ++ data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; ++ ++ ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data); ++ if (ret_val) ++ goto out; ++ ++ /* SW Reset the PHY so all changes take effect */ ++ ret_val = e1000_commit_phy(hw); ++ if (ret_val) { ++ hw_dbg(hw, "Error Resetting the PHY\n"); ++ goto out; ++ } ++ ++ /* Bypass RX and TX FIFO's */ ++ ret_val = e1000_write_kmrn_reg(hw, ++ E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL, ++ E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | ++ E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; ++ ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data); ++ if (ret_val) ++ goto out; ++ ++ ctrl_ext = er32(CTRL_EXT); ++ ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); ++ ew32(CTRL_EXT, ctrl_ext); ++ ++ ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); ++ if (ret_val) ++ goto out; ++ ++ /* Do not init these registers when the HW is in IAMT mode, since the ++ * firmware will have already initialized them. We only initialize ++ * them if the HW is not in IAMT mode. ++ */ ++ if (!e1000_check_mng_mode(hw)) { ++ /* Enable Electrical Idle on the PHY */ ++ data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; ++ ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; ++ ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data); ++ if (ret_val) ++ goto out; ++ } ++ ++ /* Workaround: Disable padding in Kumeran interface in the MAC ++ * and in the PHY to avoid CRC errors. ++ */ ++ ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data); ++ if (ret_val) ++ goto out; ++ ++ data |= GG82563_ICR_DIS_PADDING; ++ ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data); ++ if (ret_val) ++ goto out; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 ++ * @hw: pointer to the HW structure ++ * ++ * Essentially a wrapper for setting up all things "copper" related. ++ * This is a function pointer entry point called by the mac module. ++ **/ ++static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ s32 ret_val; ++ u16 reg_data; ++ ++ ctrl = er32(CTRL); ++ ctrl |= E1000_CTRL_SLU; ++ ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); ++ ew32(CTRL, ctrl); ++ ++ /* Set the mac to wait the maximum time between each ++ * iteration and increase the max iterations when ++ * polling the phy; this fixes erroneous timeouts at 10Mbps. */ ++ ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); ++ if (ret_val) ++ goto out; ++ ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); ++ if (ret_val) ++ goto out; ++ reg_data |= 0x3F; ++ ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); ++ if (ret_val) ++ goto out; ++ ret_val = e1000_read_kmrn_reg(hw, ++ E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, ++ ®_data); ++ if (ret_val) ++ goto out; ++ reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; ++ ret_val = e1000_write_kmrn_reg(hw, ++ E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, ++ reg_data); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000_setup_copper_link(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation ++ * @hw: pointer to the HW structure ++ * @duplex: current duplex setting ++ * ++ * Configure the KMRN interface by applying last minute quirks for ++ * 10/100 operation. ++ **/ ++static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u32 tipg; ++ u16 reg_data; ++ ++ reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; ++ ret_val = e1000_write_kmrn_reg(hw, ++ E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, ++ reg_data); ++ if (ret_val) ++ goto out; ++ ++ /* Configure Transmit Inter-Packet Gap */ ++ tipg = er32(TIPG); ++ tipg &= ~E1000_TIPG_IPGT_MASK; ++ tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; ++ ew32(TIPG, tipg); ++ ++ ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); ++ if (ret_val) ++ goto out; ++ ++ if (duplex == HALF_DUPLEX) ++ reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; ++ else ++ reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; ++ ++ ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation ++ * @hw: pointer to the HW structure ++ * ++ * Configure the KMRN interface by applying last minute quirks for ++ * gigabit operation. ++ **/ ++static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 reg_data; ++ u32 tipg; ++ ++ reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; ++ ret_val = e1000_write_kmrn_reg(hw, ++ E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, ++ reg_data); ++ if (ret_val) ++ goto out; ++ ++ /* Configure Transmit Inter-Packet Gap */ ++ tipg = er32(TIPG); ++ tipg &= ~E1000_TIPG_IPGT_MASK; ++ tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; ++ ew32(TIPG, tipg); ++ ++ ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); ++ if (ret_val) ++ goto out; ++ ++ reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; ++ ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters ++ * @hw: pointer to the HW structure ++ * ++ * Clears the hardware counters by reading the counter registers. ++ **/ ++static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) ++{ ++ u32 temp; ++ ++ e1000_clear_hw_cntrs_base(hw); ++ ++ temp = er32(PRC64); ++ temp = er32(PRC127); ++ temp = er32(PRC255); ++ temp = er32(PRC511); ++ temp = er32(PRC1023); ++ temp = er32(PRC1522); ++ temp = er32(PTC64); ++ temp = er32(PTC127); ++ temp = er32(PTC255); ++ temp = er32(PTC511); ++ temp = er32(PTC1023); ++ temp = er32(PTC1522); ++ ++ temp = er32(ALGNERRC); ++ temp = er32(RXERRC); ++ temp = er32(TNCRS); ++ temp = er32(CEXTERR); ++ temp = er32(TSCTC); ++ temp = er32(TSCTFC); ++ ++ temp = er32(MGTPRC); ++ temp = er32(MGTPDC); ++ temp = er32(MGTPTC); ++ ++ temp = er32(IAC); ++ temp = er32(ICRXOC); ++ ++ temp = er32(ICRXPTC); ++ temp = er32(ICRXATC); ++ temp = er32(ICTXPTC); ++ temp = er32(ICTXATC); ++ temp = er32(ICTXQEC); ++ temp = er32(ICTXQMTC); ++ temp = er32(ICRXDMTC); ++} ++ ++static struct e1000_mac_operations es2_mac_ops = { ++ .mng_mode_enab = E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT, ++ /* check_for_link dependent on media type */ ++ .cleanup_led = e1000_cleanup_led_generic, ++ .clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan, ++ .get_bus_info = e1000_get_bus_info_pcie, ++ .get_link_up_info = e1000_get_link_up_info_80003es2lan, ++ .led_on = e1000_led_on_generic, ++ .led_off = e1000_led_off_generic, ++ .mc_addr_list_update = e1000_mc_addr_list_update_generic, ++ .reset_hw = e1000_reset_hw_80003es2lan, ++ .init_hw = e1000_init_hw_80003es2lan, ++ .setup_link = e1000_setup_link, ++ /* setup_physical_interface dependent on media type */ ++}; ++ ++static struct e1000_phy_operations es2_phy_ops = { ++ .acquire_phy = e1000_acquire_phy_80003es2lan, ++ .check_reset_block = e1000_check_reset_block_generic, ++ .commit_phy = e1000_phy_sw_reset, ++ .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan, ++ .get_cfg_done = e1000_get_cfg_done_80003es2lan, ++ .get_cable_length = e1000_get_cable_length_80003es2lan, ++ .get_phy_info = e1000_get_phy_info_m88, ++ .read_phy_reg = e1000_read_phy_reg_gg82563_80003es2lan, ++ .release_phy = e1000_release_phy_80003es2lan, ++ .reset_phy = e1000_phy_hw_reset_generic, ++ .set_d0_lplu_state = NULL, ++ .set_d3_lplu_state = e1000_set_d3_lplu_state, ++ .write_phy_reg = e1000_write_phy_reg_gg82563_80003es2lan, ++}; ++ ++static struct e1000_nvm_operations es2_nvm_ops = { ++ .acquire_nvm = e1000_acquire_nvm_80003es2lan, ++ .read_nvm = e1000_read_nvm_eerd, ++ .release_nvm = e1000_release_nvm_80003es2lan, ++ .update_nvm = e1000_update_nvm_checksum_generic, ++ .valid_led_default = e1000_valid_led_default, ++ .validate_nvm = e1000_validate_nvm_checksum_generic, ++ .write_nvm = e1000_write_nvm_80003es2lan, ++}; ++ ++struct e1000_info e1000_es2_info = { ++ .mac = e1000_80003es2lan, ++ .flags = FLAG_HAS_HW_VLAN_FILTER ++ | FLAG_HAS_JUMBO_FRAMES ++ | FLAG_HAS_STATS_PTC_PRC ++ | FLAG_HAS_WOL ++ | FLAG_APME_IN_CTRL3 ++ | FLAG_RX_CSUM_ENABLED ++ | FLAG_HAS_CTRLEXT_ON_LOAD ++ | FLAG_HAS_STATS_ICR_ICT ++ | FLAG_RX_NEEDS_RESTART /* errata */ ++ | FLAG_TARC_SET_BIT_ZERO /* errata */ ++ | FLAG_APME_CHECK_PORT_B ++ | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ ++ | FLAG_TIPG_MEDIUM_FOR_80003ESLAN, ++ .pba = 38, ++ .get_invariants = e1000_get_invariants_80003es2lan, ++ .mac_ops = &es2_mac_ops, ++ .phy_ops = &es2_phy_ops, ++ .nvm_ops = &es2_nvm_ops, ++}; ++ +diff --git a/drivers/net/e1000e/ethtool.c b/drivers/net/e1000e/ethtool.c +new file mode 100644 +index 0000000..6c417ea +--- /dev/null ++++ b/drivers/net/e1000e/ethtool.c +@@ -0,0 +1,1763 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2007 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS <linux.nics@intel.com> ++ e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++/* ethtool support for e1000 */ ++ ++#include <linux/netdevice.h> ++ ++#include <linux/ethtool.h> ++ ++#include "e1000.h" ++ ++struct e1000_stats { ++ char stat_string[ETH_GSTRING_LEN]; ++ int sizeof_stat; ++ int stat_offset; ++}; ++ ++#define E1000_STAT(m) sizeof(((struct e1000_adapter *)0)->m), \ ++ offsetof(struct e1000_adapter, m) ++static const struct e1000_stats e1000_gstrings_stats[] = { ++ { "rx_packets", E1000_STAT(stats.gprc) }, ++ { "tx_packets", E1000_STAT(stats.gptc) }, ++ { "rx_bytes", E1000_STAT(stats.gorcl) }, ++ { "tx_bytes", E1000_STAT(stats.gotcl) }, ++ { "rx_broadcast", E1000_STAT(stats.bprc) }, ++ { "tx_broadcast", E1000_STAT(stats.bptc) }, ++ { "rx_multicast", E1000_STAT(stats.mprc) }, ++ { "tx_multicast", E1000_STAT(stats.mptc) }, ++ { "rx_errors", E1000_STAT(net_stats.rx_errors) }, ++ { "tx_errors", E1000_STAT(net_stats.tx_errors) }, ++ { "tx_dropped", E1000_STAT(net_stats.tx_dropped) }, ++ { "multicast", E1000_STAT(stats.mprc) }, ++ { "collisions", E1000_STAT(stats.colc) }, ++ { "rx_length_errors", E1000_STAT(net_stats.rx_length_errors) }, ++ { "rx_over_errors", E1000_STAT(net_stats.rx_over_errors) }, ++ { "rx_crc_errors", E1000_STAT(stats.crcerrs) }, ++ { "rx_frame_errors", E1000_STAT(net_stats.rx_frame_errors) }, ++ { "rx_no_buffer_count", E1000_STAT(stats.rnbc) }, ++ { "rx_missed_errors", E1000_STAT(stats.mpc) }, ++ { "tx_aborted_errors", E1000_STAT(stats.ecol) }, ++ { "tx_carrier_errors", E1000_STAT(stats.tncrs) }, ++ { "tx_fifo_errors", E1000_STAT(net_stats.tx_fifo_errors) }, ++ { "tx_heartbeat_errors", E1000_STAT(net_stats.tx_heartbeat_errors) }, ++ { "tx_window_errors", E1000_STAT(stats.latecol) }, ++ { "tx_abort_late_coll", E1000_STAT(stats.latecol) }, ++ { "tx_deferred_ok", E1000_STAT(stats.dc) }, ++ { "tx_single_coll_ok", E1000_STAT(stats.scc) }, ++ { "tx_multi_coll_ok", E1000_STAT(stats.mcc) }, ++ { "tx_timeout_count", E1000_STAT(tx_timeout_count) }, ++ { "tx_restart_queue", E1000_STAT(restart_queue) }, ++ { "rx_long_length_errors", E1000_STAT(stats.roc) }, ++ { "rx_short_length_errors", E1000_STAT(stats.ruc) }, ++ { "rx_align_errors", E1000_STAT(stats.algnerrc) }, ++ { "tx_tcp_seg_good", E1000_STAT(stats.tsctc) }, ++ { "tx_tcp_seg_failed", E1000_STAT(stats.tsctfc) }, ++ { "rx_flow_control_xon", E1000_STAT(stats.xonrxc) }, ++ { "rx_flow_control_xoff", E1000_STAT(stats.xoffrxc) }, ++ { "tx_flow_control_xon", E1000_STAT(stats.xontxc) }, ++ { "tx_flow_control_xoff", E1000_STAT(stats.xofftxc) }, ++ { "rx_long_byte_count", E1000_STAT(stats.gorcl) }, ++ { "rx_csum_offload_good", E1000_STAT(hw_csum_good) }, ++ { "rx_csum_offload_errors", E1000_STAT(hw_csum_err) }, ++ { "rx_header_split", E1000_STAT(rx_hdr_split) }, ++ { "alloc_rx_buff_failed", E1000_STAT(alloc_rx_buff_failed) }, ++ { "tx_smbus", E1000_STAT(stats.mgptc) }, ++ { "rx_smbus", E1000_STAT(stats.mgprc) }, ++ { "dropped_smbus", E1000_STAT(stats.mgpdc) }, ++}; ++ ++#define E1000_GLOBAL_STATS_LEN \ ++ sizeof(e1000_gstrings_stats) / sizeof(struct e1000_stats) ++#define E1000_STATS_LEN (E1000_GLOBAL_STATS_LEN) ++static const char e1000_gstrings_test[][ETH_GSTRING_LEN] = { ++ "Register test (offline)", "Eeprom test (offline)", ++ "Interrupt test (offline)", "Loopback test (offline)", ++ "Link test (on/offline)" ++}; ++#define E1000_TEST_LEN sizeof(e1000_gstrings_test) / ETH_GSTRING_LEN ++ ++static int e1000_get_settings(struct net_device *netdev, ++ struct ethtool_cmd *ecmd) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ struct e1000_hw *hw = &adapter->hw; ++ ++ if (hw->media_type == e1000_media_type_copper) { ++ ++ ecmd->supported = (SUPPORTED_10baseT_Half | ++ SUPPORTED_10baseT_Full | ++ SUPPORTED_100baseT_Half | ++ SUPPORTED_100baseT_Full | ++ SUPPORTED_1000baseT_Full | ++ SUPPORTED_Autoneg | ++ SUPPORTED_TP); ++ if (hw->phy.type == e1000_phy_ife) ++ ecmd->supported &= ~SUPPORTED_1000baseT_Full; ++ ecmd->advertising = ADVERTISED_TP; ++ ++ if (hw->mac.autoneg == 1) { ++ ecmd->advertising |= ADVERTISED_Autoneg; ++ /* the e1000 autoneg seems to match ethtool nicely */ ++ ecmd->advertising |= hw->phy.autoneg_advertised; ++ } ++ ++ ecmd->port = PORT_TP; ++ ecmd->phy_address = hw->phy.addr; ++ ecmd->transceiver = XCVR_INTERNAL; ++ ++ } else { ++ ecmd->supported = (SUPPORTED_1000baseT_Full | ++ SUPPORTED_FIBRE | ++ SUPPORTED_Autoneg); ++ ++ ecmd->advertising = (ADVERTISED_1000baseT_Full | ++ ADVERTISED_FIBRE | ++ ADVERTISED_Autoneg); ++ ++ ecmd->port = PORT_FIBRE; ++ ecmd->transceiver = XCVR_EXTERNAL; ++ } ++ ++ if (er32(STATUS) & E1000_STATUS_LU) { ++ ++ adapter->hw.mac.ops.get_link_up_info(hw, &adapter->link_speed, ++ &adapter->link_duplex); ++ ecmd->speed = adapter->link_speed; ++ ++ /* unfortunately FULL_DUPLEX != DUPLEX_FULL ++ * and HALF_DUPLEX != DUPLEX_HALF */ ++ ++ if (adapter->link_duplex == FULL_DUPLEX) ++ ecmd->duplex = DUPLEX_FULL; ++ else ++ ecmd->duplex = DUPLEX_HALF; ++ } else { ++ ecmd->speed = -1; ++ ecmd->duplex = -1; ++ } ++ ++ ecmd->autoneg = ((hw->media_type == e1000_media_type_fiber) || ++ hw->mac.autoneg) ? AUTONEG_ENABLE : AUTONEG_DISABLE; ++ return 0; ++} ++ ++static int e1000_set_spd_dplx(struct e1000_adapter *adapter, u16 spddplx) ++{ ++ struct e1000_mac_info *mac = &adapter->hw.mac; ++ ++ mac->autoneg = 0; ++ ++ /* Fiber NICs only allow 1000 gbps Full duplex */ ++ if ((adapter->hw.media_type == e1000_media_type_fiber) && ++ spddplx != (SPEED_1000 + DUPLEX_FULL)) { ++ ndev_err(adapter->netdev, "Unsupported Speed/Duplex " ++ "configuration\n"); ++ return -EINVAL; ++ } ++ ++ switch (spddplx) { ++ case SPEED_10 + DUPLEX_HALF: ++ mac->forced_speed_duplex = ADVERTISE_10_HALF; ++ break; ++ case SPEED_10 + DUPLEX_FULL: ++ mac->forced_speed_duplex = ADVERTISE_10_FULL; ++ break; ++ case SPEED_100 + DUPLEX_HALF: ++ mac->forced_speed_duplex = ADVERTISE_100_HALF; ++ break; ++ case SPEED_100 + DUPLEX_FULL: ++ mac->forced_speed_duplex = ADVERTISE_100_FULL; ++ break; ++ case SPEED_1000 + DUPLEX_FULL: ++ mac->autoneg = 1; ++ adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; ++ break; ++ case SPEED_1000 + DUPLEX_HALF: /* not supported */ ++ default: ++ ndev_err(adapter->netdev, "Unsupported Speed/Duplex " ++ "configuration\n"); ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++static int e1000_set_settings(struct net_device *netdev, ++ struct ethtool_cmd *ecmd) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ struct e1000_hw *hw = &adapter->hw; ++ ++ /* When SoL/IDER sessions are active, autoneg/speed/duplex ++ * cannot be changed */ ++ if (e1000_check_reset_block(hw)) { ++ ndev_err(netdev, "Cannot change link " ++ "characteristics when SoL/IDER is active.\n"); ++ return -EINVAL; ++ } ++ ++ while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) ++ msleep(1); ++ ++ if (ecmd->autoneg == AUTONEG_ENABLE) { ++ hw->mac.autoneg = 1; ++ if (hw->media_type == e1000_media_type_fiber) ++ hw->phy.autoneg_advertised = ADVERTISED_1000baseT_Full | ++ ADVERTISED_FIBRE | ++ ADVERTISED_Autoneg; ++ else ++ hw->phy.autoneg_advertised = ecmd->advertising | ++ ADVERTISED_TP | ++ ADVERTISED_Autoneg; ++ ecmd->advertising = hw->phy.autoneg_advertised; ++ } else { ++ if (e1000_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) { ++ clear_bit(__E1000_RESETTING, &adapter->state); ++ return -EINVAL; ++ } ++ } ++ ++ /* reset the link */ ++ ++ if (netif_running(adapter->netdev)) { ++ e1000_down(adapter); ++ e1000_up(adapter); ++ } else { ++ e1000_reset(adapter); ++ } ++ ++ clear_bit(__E1000_RESETTING, &adapter->state); ++ return 0; ++} ++ ++static void e1000_get_pauseparam(struct net_device *netdev, ++ struct ethtool_pauseparam *pause) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ struct e1000_hw *hw = &adapter->hw; ++ ++ pause->autoneg = ++ (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE); ++ ++ if (hw->mac.fc == e1000_fc_rx_pause) { ++ pause->rx_pause = 1; ++ } else if (hw->mac.fc == e1000_fc_tx_pause) { ++ pause->tx_pause = 1; ++ } else if (hw->mac.fc == e1000_fc_full) { ++ pause->rx_pause = 1; ++ pause->tx_pause = 1; ++ } ++} ++ ++static int e1000_set_pauseparam(struct net_device *netdev, ++ struct ethtool_pauseparam *pause) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ struct e1000_hw *hw = &adapter->hw; ++ int retval = 0; ++ ++ adapter->fc_autoneg = pause->autoneg; ++ ++ while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) ++ msleep(1); ++ ++ if (pause->rx_pause && pause->tx_pause) ++ hw->mac.fc = e1000_fc_full; ++ else if (pause->rx_pause && !pause->tx_pause) ++ hw->mac.fc = e1000_fc_rx_pause; ++ else if (!pause->rx_pause && pause->tx_pause) ++ hw->mac.fc = e1000_fc_tx_pause; ++ else if (!pause->rx_pause && !pause->tx_pause) ++ hw->mac.fc = e1000_fc_none; ++ ++ hw->mac.original_fc = hw->mac.fc; ++ ++ if (adapter->fc_autoneg == AUTONEG_ENABLE) { ++ if (netif_running(adapter->netdev)) { ++ e1000_down(adapter); ++ e1000_up(adapter); ++ } else { ++ e1000_reset(adapter); ++ } ++ } else { ++ retval = ((hw->media_type == e1000_media_type_fiber) ? ++ hw->mac.ops.setup_link(hw) : e1000_force_mac_fc(hw)); ++ } ++ ++ clear_bit(__E1000_RESETTING, &adapter->state); ++ return retval; ++} ++ ++static u32 e1000_get_rx_csum(struct net_device *netdev) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ return (adapter->flags & FLAG_RX_CSUM_ENABLED); ++} ++ ++static int e1000_set_rx_csum(struct net_device *netdev, u32 data) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ ++ if (data) ++ adapter->flags |= FLAG_RX_CSUM_ENABLED; ++ else ++ adapter->flags &= ~FLAG_RX_CSUM_ENABLED; ++ ++ if (netif_running(netdev)) ++ e1000_reinit_locked(adapter); ++ else ++ e1000_reset(adapter); ++ return 0; ++} ++ ++static u32 e1000_get_tx_csum(struct net_device *netdev) ++{ ++ return ((netdev->features & NETIF_F_HW_CSUM) != 0); ++} ++ ++static int e1000_set_tx_csum(struct net_device *netdev, u32 data) ++{ ++ if (data) ++ netdev->features |= NETIF_F_HW_CSUM; ++ else ++ netdev->features &= ~NETIF_F_HW_CSUM; ++ ++ return 0; ++} ++ ++static int e1000_set_tso(struct net_device *netdev, u32 data) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ ++ if (data) { ++ netdev->features |= NETIF_F_TSO; ++ netdev->features |= NETIF_F_TSO6; ++ } else { ++ netdev->features &= ~NETIF_F_TSO; ++ netdev->features &= ~NETIF_F_TSO6; ++ } ++ ++ ndev_info(netdev, "TSO is %s\n", ++ data ? "Enabled" : "Disabled"); ++ adapter->flags |= FLAG_TSO_FORCE; ++ return 0; ++} ++ ++static u32 e1000_get_msglevel(struct net_device *netdev) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ return adapter->msg_enable; ++} ++ ++static void e1000_set_msglevel(struct net_device *netdev, u32 data) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ adapter->msg_enable = data; ++} ++ ++static int e1000_get_regs_len(struct net_device *netdev) ++{ ++#define E1000_REGS_LEN 32 /* overestimate */ ++ return E1000_REGS_LEN * sizeof(u32); ++} ++ ++static void e1000_get_regs(struct net_device *netdev, ++ struct ethtool_regs *regs, void *p) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ struct e1000_hw *hw = &adapter->hw; ++ u32 *regs_buff = p; ++ u16 phy_data; ++ u8 revision_id; ++ ++ memset(p, 0, E1000_REGS_LEN * sizeof(u32)); ++ ++ pci_read_config_byte(adapter->pdev, PCI_REVISION_ID, &revision_id); ++ ++ regs->version = (1 << 24) | (revision_id << 16) | adapter->pdev->device; ++ ++ regs_buff[0] = er32(CTRL); ++ regs_buff[1] = er32(STATUS); ++ ++ regs_buff[2] = er32(RCTL); ++ regs_buff[3] = er32(RDLEN); ++ regs_buff[4] = er32(RDH); ++ regs_buff[5] = er32(RDT); ++ regs_buff[6] = er32(RDTR); ++ ++ regs_buff[7] = er32(TCTL); ++ regs_buff[8] = er32(TDLEN); ++ regs_buff[9] = er32(TDH); ++ regs_buff[10] = er32(TDT); ++ regs_buff[11] = er32(TIDV); ++ ++ regs_buff[12] = adapter->hw.phy.type; /* PHY type (IGP=1, M88=0) */ ++ if (hw->phy.type == e1000_phy_m88) { ++ e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); ++ regs_buff[13] = (u32)phy_data; /* cable length */ ++ regs_buff[14] = 0; /* Dummy (to align w/ IGP phy reg dump) */ ++ regs_buff[15] = 0; /* Dummy (to align w/ IGP phy reg dump) */ ++ regs_buff[16] = 0; /* Dummy (to align w/ IGP phy reg dump) */ ++ e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); ++ regs_buff[17] = (u32)phy_data; /* extended 10bt distance */ ++ regs_buff[18] = regs_buff[13]; /* cable polarity */ ++ regs_buff[19] = 0; /* Dummy (to align w/ IGP phy reg dump) */ ++ regs_buff[20] = regs_buff[17]; /* polarity correction */ ++ /* phy receive errors */ ++ regs_buff[22] = adapter->phy_stats.receive_errors; ++ regs_buff[23] = regs_buff[13]; /* mdix mode */ ++ } ++ regs_buff[21] = adapter->phy_stats.idle_errors; /* phy idle errors */ ++ e1e_rphy(hw, PHY_1000T_STATUS, &phy_data); ++ regs_buff[24] = (u32)phy_data; /* phy local receiver status */ ++ regs_buff[25] = regs_buff[24]; /* phy remote receiver status */ ++} ++ ++static int e1000_get_eeprom_len(struct net_device *netdev) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ return adapter->hw.nvm.word_size * 2; ++} ++ ++static int e1000_get_eeprom(struct net_device *netdev, ++ struct ethtool_eeprom *eeprom, u8 *bytes) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ struct e1000_hw *hw = &adapter->hw; ++ u16 *eeprom_buff; ++ int first_word; ++ int last_word; ++ int ret_val = 0; ++ u16 i; ++ ++ if (eeprom->len == 0) ++ return -EINVAL; ++ ++ eeprom->magic = adapter->pdev->vendor | (adapter->pdev->device << 16); ++ ++ first_word = eeprom->offset >> 1; ++ last_word = (eeprom->offset + eeprom->len - 1) >> 1; ++ ++ eeprom_buff = kmalloc(sizeof(u16) * ++ (last_word - first_word + 1), GFP_KERNEL); ++ if (!eeprom_buff) ++ return -ENOMEM; ++ ++ if (hw->nvm.type == e1000_nvm_eeprom_spi) { ++ ret_val = e1000_read_nvm(hw, first_word, ++ last_word - first_word + 1, ++ eeprom_buff); ++ } else { ++ for (i = 0; i < last_word - first_word + 1; i++) { ++ ret_val = e1000_read_nvm(hw, first_word + i, 1, ++ &eeprom_buff[i]); ++ if (ret_val) ++ break; ++ } ++ } ++ ++ /* Device's eeprom is always little-endian, word addressable */ ++ for (i = 0; i < last_word - first_word + 1; i++) ++ le16_to_cpus(&eeprom_buff[i]); ++ ++ memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len); ++ kfree(eeprom_buff); ++ ++ return ret_val; ++} ++ ++static int e1000_set_eeprom(struct net_device *netdev, ++ struct ethtool_eeprom *eeprom, u8 *bytes) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ struct e1000_hw *hw = &adapter->hw; ++ u16 *eeprom_buff; ++ void *ptr; ++ int max_len; ++ int first_word; ++ int last_word; ++ int ret_val = 0; ++ u16 i; ++ ++ if (eeprom->len == 0) ++ return -EOPNOTSUPP; ++ ++ if (eeprom->magic != (adapter->pdev->vendor | (adapter->pdev->device << 16))) ++ return -EFAULT; ++ ++ max_len = hw->nvm.word_size * 2; ++ ++ first_word = eeprom->offset >> 1; ++ last_word = (eeprom->offset + eeprom->len - 1) >> 1; ++ eeprom_buff = kmalloc(max_len, GFP_KERNEL); ++ if (!eeprom_buff) ++ return -ENOMEM; ++ ++ ptr = (void *)eeprom_buff; ++ ++ if (eeprom->offset & 1) { ++ /* need read/modify/write of first changed EEPROM word */ ++ /* only the second byte of the word is being modified */ ++ ret_val = e1000_read_nvm(hw, first_word, 1, &eeprom_buff[0]); ++ ptr++; ++ } ++ if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) ++ /* need read/modify/write of last changed EEPROM word */ ++ /* only the first byte of the word is being modified */ ++ ret_val = e1000_read_nvm(hw, last_word, 1, ++ &eeprom_buff[last_word - first_word]); ++ ++ /* Device's eeprom is always little-endian, word addressable */ ++ for (i = 0; i < last_word - first_word + 1; i++) ++ le16_to_cpus(&eeprom_buff[i]); ++ ++ memcpy(ptr, bytes, eeprom->len); ++ ++ for (i = 0; i < last_word - first_word + 1; i++) ++ eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]); ++ ++ ret_val = e1000_write_nvm(hw, first_word, ++ last_word - first_word + 1, eeprom_buff); ++ ++ /* Update the checksum over the first part of the EEPROM if needed ++ * and flush shadow RAM for 82573 controllers */ ++ if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG) || ++ (hw->mac.type == e1000_82573))) ++ e1000_update_nvm_checksum(hw); ++ ++ kfree(eeprom_buff); ++ return ret_val; ++} ++ ++static void e1000_get_drvinfo(struct net_device *netdev, ++ struct ethtool_drvinfo *drvinfo) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ char firmware_version[32]; ++ u16 eeprom_data; ++ ++ strncpy(drvinfo->driver, e1000_driver_name, 32); ++ strncpy(drvinfo->version, e1000_driver_version, 32); ++ ++ /* EEPROM image version # is reported as firmware version # for ++ * PCI-E controllers */ ++ e1000_read_nvm(&adapter->hw, 5, 1, &eeprom_data); ++ sprintf(firmware_version, "%d.%d-%d", ++ (eeprom_data & 0xF000) >> 12, ++ (eeprom_data & 0x0FF0) >> 4, ++ eeprom_data & 0x000F); ++ ++ strncpy(drvinfo->fw_version, firmware_version, 32); ++ strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32); ++ drvinfo->n_stats = E1000_STATS_LEN; ++ drvinfo->testinfo_len = E1000_TEST_LEN; ++ drvinfo->regdump_len = e1000_get_regs_len(netdev); ++ drvinfo->eedump_len = e1000_get_eeprom_len(netdev); ++} ++ ++static void e1000_get_ringparam(struct net_device *netdev, ++ struct ethtool_ringparam *ring) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ struct e1000_ring *tx_ring = adapter->tx_ring; ++ struct e1000_ring *rx_ring = adapter->rx_ring; ++ ++ ring->rx_max_pending = E1000_MAX_RXD; ++ ring->tx_max_pending = E1000_MAX_TXD; ++ ring->rx_mini_max_pending = 0; ++ ring->rx_jumbo_max_pending = 0; ++ ring->rx_pending = rx_ring->count; ++ ring->tx_pending = tx_ring->count; ++ ring->rx_mini_pending = 0; ++ ring->rx_jumbo_pending = 0; ++} ++ ++static int e1000_set_ringparam(struct net_device *netdev, ++ struct ethtool_ringparam *ring) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ struct e1000_ring *tx_ring, *tx_old; ++ struct e1000_ring *rx_ring, *rx_old; ++ int err; ++ ++ if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) ++ return -EINVAL; ++ ++ while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) ++ msleep(1); ++ ++ if (netif_running(adapter->netdev)) ++ e1000_down(adapter); ++ ++ tx_old = adapter->tx_ring; ++ rx_old = adapter->rx_ring; ++ ++ err = -ENOMEM; ++ tx_ring = kzalloc(sizeof(struct e1000_ring), GFP_KERNEL); ++ if (!tx_ring) ++ goto err_alloc_tx; ++ ++ rx_ring = kzalloc(sizeof(struct e1000_ring), GFP_KERNEL); ++ if (!rx_ring) ++ goto err_alloc_rx; ++ ++ adapter->tx_ring = tx_ring; ++ adapter->rx_ring = rx_ring; ++ ++ rx_ring->count = max(ring->rx_pending, (u32)E1000_MIN_RXD); ++ rx_ring->count = min(rx_ring->count, (u32)(E1000_MAX_RXD)); ++ rx_ring->count = ALIGN(rx_ring->count, REQ_RX_DESCRIPTOR_MULTIPLE); ++ ++ tx_ring->count = max(ring->tx_pending, (u32)E1000_MIN_TXD); ++ tx_ring->count = min(tx_ring->count, (u32)(E1000_MAX_TXD)); ++ tx_ring->count = ALIGN(tx_ring->count, REQ_TX_DESCRIPTOR_MULTIPLE); ++ ++ if (netif_running(adapter->netdev)) { ++ /* Try to get new resources before deleting old */ ++ err = e1000_setup_rx_resources(adapter); ++ if (err) ++ goto err_setup_rx; ++ err = e1000_setup_tx_resources(adapter); ++ if (err) ++ goto err_setup_tx; ++ ++ /* save the new, restore the old in order to free it, ++ * then restore the new back again */ ++ adapter->rx_ring = rx_old; ++ adapter->tx_ring = tx_old; ++ e1000_free_rx_resources(adapter); ++ e1000_free_tx_resources(adapter); ++ kfree(tx_old); ++ kfree(rx_old); ++ adapter->rx_ring = rx_ring; ++ adapter->tx_ring = tx_ring; ++ err = e1000_up(adapter); ++ if (err) ++ goto err_setup; ++ } ++ ++ clear_bit(__E1000_RESETTING, &adapter->state); ++ return 0; ++err_setup_tx: ++ e1000_free_rx_resources(adapter); ++err_setup_rx: ++ adapter->rx_ring = rx_old; ++ adapter->tx_ring = tx_old; ++ kfree(rx_ring); ++err_alloc_rx: ++ kfree(tx_ring); ++err_alloc_tx: ++ e1000_up(adapter); ++err_setup: ++ clear_bit(__E1000_RESETTING, &adapter->state); ++ return err; ++} ++ ++#define REG_PATTERN_TEST(R, M, W) REG_PATTERN_TEST_ARRAY(R, 0, M, W) ++#define REG_PATTERN_TEST_ARRAY(reg, offset, mask, writeable) \ ++{ \ ++ u32 _pat; \ ++ u32 _value; \ ++ u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \ ++ for (_pat = 0; _pat < ARRAY_SIZE(_test); _pat++) { \ ++ E1000_WRITE_REG_ARRAY(hw, reg, offset, \ ++ (_test[_pat] & writeable)); \ ++ _value = E1000_READ_REG_ARRAY(hw, reg, offset); \ ++ if (_value != (_test[_pat] & writeable & mask)) { \ ++ ndev_err(netdev, "pattern test reg %04X " \ ++ "failed: got 0x%08X expected 0x%08X\n", \ ++ reg + offset, \ ++ value, (_test[_pat] & writeable & mask)); \ ++ *data = reg; \ ++ return 1; \ ++ } \ ++ } \ ++} ++ ++#define REG_SET_AND_CHECK(R, M, W) \ ++{ \ ++ u32 _value; \ ++ __ew32(hw, R, W & M); \ ++ _value = __er32(hw, R); \ ++ if ((W & M) != (_value & M)) { \ ++ ndev_err(netdev, "set/check reg %04X test failed: " \ ++ "got 0x%08X expected 0x%08X\n", R, (_value & M), \ ++ (W & M)); \ ++ *data = R; \ ++ return 1; \ ++ } \ ++} ++ ++static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ struct e1000_mac_info *mac = &adapter->hw.mac; ++ struct net_device *netdev = adapter->netdev; ++ u32 value; ++ u32 before; ++ u32 after; ++ u32 i; ++ u32 toggle; ++ ++ /* The status register is Read Only, so a write should fail. ++ * Some bits that get toggled are ignored. ++ */ ++ switch (mac->type) { ++ /* there are several bits on newer hardware that are r/w */ ++ case e1000_82571: ++ case e1000_82572: ++ case e1000_80003es2lan: ++ toggle = 0x7FFFF3FF; ++ break; ++ case e1000_82573: ++ case e1000_ich8lan: ++ case e1000_ich9lan: ++ toggle = 0x7FFFF033; ++ break; ++ default: ++ toggle = 0xFFFFF833; ++ break; ++ } ++ ++ before = er32(STATUS); ++ value = (er32(STATUS) & toggle); ++ ew32(STATUS, toggle); ++ after = er32(STATUS) & toggle; ++ if (value != after) { ++ ndev_err(netdev, "failed STATUS register test got: " ++ "0x%08X expected: 0x%08X\n", after, value); ++ *data = 1; ++ return 1; ++ } ++ /* restore previous status */ ++ ew32(STATUS, before); ++ ++ if ((mac->type != e1000_ich8lan) && ++ (mac->type != e1000_ich9lan)) { ++ REG_PATTERN_TEST(E1000_FCAL, 0xFFFFFFFF, 0xFFFFFFFF); ++ REG_PATTERN_TEST(E1000_FCAH, 0x0000FFFF, 0xFFFFFFFF); ++ REG_PATTERN_TEST(E1000_FCT, 0x0000FFFF, 0xFFFFFFFF); ++ REG_PATTERN_TEST(E1000_VET, 0x0000FFFF, 0xFFFFFFFF); ++ } ++ ++ REG_PATTERN_TEST(E1000_RDTR, 0x0000FFFF, 0xFFFFFFFF); ++ REG_PATTERN_TEST(E1000_RDBAH, 0xFFFFFFFF, 0xFFFFFFFF); ++ REG_PATTERN_TEST(E1000_RDLEN, 0x000FFF80, 0x000FFFFF); ++ REG_PATTERN_TEST(E1000_RDH, 0x0000FFFF, 0x0000FFFF); ++ REG_PATTERN_TEST(E1000_RDT, 0x0000FFFF, 0x0000FFFF); ++ REG_PATTERN_TEST(E1000_FCRTH, 0x0000FFF8, 0x0000FFF8); ++ REG_PATTERN_TEST(E1000_FCTTV, 0x0000FFFF, 0x0000FFFF); ++ REG_PATTERN_TEST(E1000_TIPG, 0x3FFFFFFF, 0x3FFFFFFF); ++ REG_PATTERN_TEST(E1000_TDBAH, 0xFFFFFFFF, 0xFFFFFFFF); ++ REG_PATTERN_TEST(E1000_TDLEN, 0x000FFF80, 0x000FFFFF); ++ ++ REG_SET_AND_CHECK(E1000_RCTL, 0xFFFFFFFF, 0x00000000); ++ ++ before = (((mac->type == e1000_ich8lan) || ++ (mac->type == e1000_ich9lan)) ? 0x06C3B33E : 0x06DFB3FE); ++ REG_SET_AND_CHECK(E1000_RCTL, before, 0x003FFFFB); ++ REG_SET_AND_CHECK(E1000_TCTL, 0xFFFFFFFF, 0x00000000); ++ ++ REG_SET_AND_CHECK(E1000_RCTL, 0xFFFFFFFF, 0x01FFFFFF); ++ REG_PATTERN_TEST(E1000_RDBAL, 0xFFFFF000, 0xFFFFFFFF); ++ REG_PATTERN_TEST(E1000_TXCW, 0x0000FFFF, 0x0000FFFF); ++ REG_PATTERN_TEST(E1000_TDBAL, 0xFFFFF000, 0xFFFFFFFF); ++ ++ for (i = 0; i < mac->mta_reg_count; i++) ++ REG_PATTERN_TEST_ARRAY(E1000_MTA, i, 0xFFFFFFFF, 0xFFFFFFFF); ++ ++ *data = 0; ++ return 0; ++} ++ ++static int e1000_eeprom_test(struct e1000_adapter *adapter, u64 *data) ++{ ++ u16 temp; ++ u16 checksum = 0; ++ u16 i; ++ ++ *data = 0; ++ /* Read and add up the contents of the EEPROM */ ++ for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { ++ if ((e1000_read_nvm(&adapter->hw, i, 1, &temp)) < 0) { ++ *data = 1; ++ break; ++ } ++ checksum += temp; ++ } ++ ++ /* If Checksum is not Correct return error else test passed */ ++ if ((checksum != (u16) NVM_SUM) && !(*data)) ++ *data = 2; ++ ++ return *data; ++} ++ ++static irqreturn_t e1000_test_intr(int irq, void *data) ++{ ++ struct net_device *netdev = (struct net_device *) data; ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ struct e1000_hw *hw = &adapter->hw; ++ ++ adapter->test_icr |= er32(ICR); ++ ++ return IRQ_HANDLED; ++} ++ ++static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data) ++{ ++ struct net_device *netdev = adapter->netdev; ++ struct e1000_hw *hw = &adapter->hw; ++ u32 mask; ++ u32 shared_int = 1; ++ u32 irq = adapter->pdev->irq; ++ int i; ++ ++ *data = 0; ++ ++ /* NOTE: we don't test MSI interrupts here, yet */ ++ /* Hook up test interrupt handler just for this test */ ++ if (!request_irq(irq, &e1000_test_intr, IRQF_PROBE_SHARED, netdev->name, ++ netdev)) { ++ shared_int = 0; ++ } else if (request_irq(irq, &e1000_test_intr, IRQF_SHARED, ++ netdev->name, netdev)) { ++ *data = 1; ++ return -1; ++ } ++ ndev_info(netdev, "testing %s interrupt\n", ++ (shared_int ? "shared" : "unshared")); ++ ++ /* Disable all the interrupts */ ++ ew32(IMC, 0xFFFFFFFF); ++ msleep(10); ++ ++ /* Test each interrupt */ ++ for (i = 0; i < 10; i++) { ++ ++ if (((adapter->hw.mac.type == e1000_ich8lan) || ++ (adapter->hw.mac.type == e1000_ich9lan)) && i == 8) ++ continue; ++ ++ /* Interrupt to test */ ++ mask = 1 << i; ++ ++ if (!shared_int) { ++ /* Disable the interrupt to be reported in ++ * the cause register and then force the same ++ * interrupt and see if one gets posted. If ++ * an interrupt was posted to the bus, the ++ * test failed. ++ */ ++ adapter->test_icr = 0; ++ ew32(IMC, mask); ++ ew32(ICS, mask); ++ msleep(10); ++ ++ if (adapter->test_icr & mask) { ++ *data = 3; ++ break; ++ } ++ } ++ ++ /* Enable the interrupt to be reported in ++ * the cause register and then force the same ++ * interrupt and see if one gets posted. If ++ * an interrupt was not posted to the bus, the ++ * test failed. ++ */ ++ adapter->test_icr = 0; ++ ew32(IMS, mask); ++ ew32(ICS, mask); ++ msleep(10); ++ ++ if (!(adapter->test_icr & mask)) { ++ *data = 4; ++ break; ++ } ++ ++ if (!shared_int) { ++ /* Disable the other interrupts to be reported in ++ * the cause register and then force the other ++ * interrupts and see if any get posted. If ++ * an interrupt was posted to the bus, the ++ * test failed. ++ */ ++ adapter->test_icr = 0; ++ ew32(IMC, ~mask & 0x00007FFF); ++ ew32(ICS, ~mask & 0x00007FFF); ++ msleep(10); ++ ++ if (adapter->test_icr) { ++ *data = 5; ++ break; ++ } ++ } ++ } ++ ++ /* Disable all the interrupts */ ++ ew32(IMC, 0xFFFFFFFF); ++ msleep(10); ++ ++ /* Unhook test interrupt handler */ ++ free_irq(irq, netdev); ++ ++ return *data; ++} ++ ++static void e1000_free_desc_rings(struct e1000_adapter *adapter) ++{ ++ struct e1000_ring *tx_ring = &adapter->test_tx_ring; ++ struct e1000_ring *rx_ring = &adapter->test_rx_ring; ++ struct pci_dev *pdev = adapter->pdev; ++ int i; ++ ++ if (tx_ring->desc && tx_ring->buffer_info) { ++ for (i = 0; i < tx_ring->count; i++) { ++ if (tx_ring->buffer_info[i].dma) ++ pci_unmap_single(pdev, ++ tx_ring->buffer_info[i].dma, ++ tx_ring->buffer_info[i].length, ++ PCI_DMA_TODEVICE); ++ if (tx_ring->buffer_info[i].skb) ++ dev_kfree_skb(tx_ring->buffer_info[i].skb); ++ } ++ } ++ ++ if (rx_ring->desc && rx_ring->buffer_info) { ++ for (i = 0; i < rx_ring->count; i++) { ++ if (rx_ring->buffer_info[i].dma) ++ pci_unmap_single(pdev, ++ rx_ring->buffer_info[i].dma, ++ 2048, PCI_DMA_FROMDEVICE); ++ if (rx_ring->buffer_info[i].skb) ++ dev_kfree_skb(rx_ring->buffer_info[i].skb); ++ } ++ } ++ ++ if (tx_ring->desc) { ++ pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, ++ tx_ring->dma); ++ tx_ring->desc = NULL; ++ } ++ if (rx_ring->desc) { ++ pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, ++ rx_ring->dma); ++ rx_ring->desc = NULL; ++ } ++ ++ kfree(tx_ring->buffer_info); ++ tx_ring->buffer_info = NULL; ++ kfree(rx_ring->buffer_info); ++ rx_ring->buffer_info = NULL; ++} ++ ++static int e1000_setup_desc_rings(struct e1000_adapter *adapter) ++{ ++ struct e1000_ring *tx_ring = &adapter->test_tx_ring; ++ struct e1000_ring *rx_ring = &adapter->test_rx_ring; ++ struct pci_dev *pdev = adapter->pdev; ++ struct e1000_hw *hw = &adapter->hw; ++ u32 rctl; ++ int size; ++ int i; ++ int ret_val; ++ ++ /* Setup Tx descriptor ring and Tx buffers */ ++ ++ if (!tx_ring->count) ++ tx_ring->count = E1000_DEFAULT_TXD; ++ ++ size = tx_ring->count * sizeof(struct e1000_buffer); ++ tx_ring->buffer_info = kmalloc(size, GFP_KERNEL); ++ if (!tx_ring->buffer_info) { ++ ret_val = 1; ++ goto err_nomem; ++ } ++ memset(tx_ring->buffer_info, 0, size); ++ ++ tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); ++ tx_ring->size = ALIGN(tx_ring->size, 4096); ++ tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, ++ &tx_ring->dma); ++ if (!tx_ring->desc) { ++ ret_val = 2; ++ goto err_nomem; ++ } ++ memset(tx_ring->desc, 0, tx_ring->size); ++ tx_ring->next_to_use = 0; ++ tx_ring->next_to_clean = 0; ++ ++ ew32(TDBAL, ++ ((u64) tx_ring->dma & 0x00000000FFFFFFFF)); ++ ew32(TDBAH, ((u64) tx_ring->dma >> 32)); ++ ew32(TDLEN, ++ tx_ring->count * sizeof(struct e1000_tx_desc)); ++ ew32(TDH, 0); ++ ew32(TDT, 0); ++ ew32(TCTL, ++ E1000_TCTL_PSP | E1000_TCTL_EN | ++ E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT | ++ E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT); ++ ++ for (i = 0; i < tx_ring->count; i++) { ++ struct e1000_tx_desc *tx_desc = E1000_TX_DESC(*tx_ring, i); ++ struct sk_buff *skb; ++ unsigned int skb_size = 1024; ++ ++ skb = alloc_skb(skb_size, GFP_KERNEL); ++ if (!skb) { ++ ret_val = 3; ++ goto err_nomem; ++ } ++ skb_put(skb, skb_size); ++ tx_ring->buffer_info[i].skb = skb; ++ tx_ring->buffer_info[i].length = skb->len; ++ tx_ring->buffer_info[i].dma = ++ pci_map_single(pdev, skb->data, skb->len, ++ PCI_DMA_TODEVICE); ++ tx_desc->buffer_addr = cpu_to_le64( ++ tx_ring->buffer_info[i].dma); ++ tx_desc->lower.data = cpu_to_le32(skb->len); ++ tx_desc->lower.data |= cpu_to_le32(E1000_TXD_CMD_EOP | ++ E1000_TXD_CMD_IFCS | ++ E1000_TXD_CMD_RPS); ++ tx_desc->upper.data = 0; ++ } ++ ++ /* Setup Rx descriptor ring and Rx buffers */ ++ ++ if (!rx_ring->count) ++ rx_ring->count = E1000_DEFAULT_RXD; ++ ++ size = rx_ring->count * sizeof(struct e1000_buffer); ++ rx_ring->buffer_info = kmalloc(size, GFP_KERNEL); ++ if (!rx_ring->buffer_info) { ++ ret_val = 4; ++ goto err_nomem; ++ } ++ memset(rx_ring->buffer_info, 0, size); ++ ++ rx_ring->size = rx_ring->count * sizeof(struct e1000_rx_desc); ++ rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, ++ &rx_ring->dma); ++ if (!rx_ring->desc) { ++ ret_val = 5; ++ goto err_nomem; ++ } ++ memset(rx_ring->desc, 0, rx_ring->size); ++ rx_ring->next_to_use = 0; ++ rx_ring->next_to_clean = 0; ++ ++ rctl = er32(RCTL); ++ ew32(RCTL, rctl & ~E1000_RCTL_EN); ++ ew32(RDBAL, ((u64) rx_ring->dma & 0xFFFFFFFF)); ++ ew32(RDBAH, ((u64) rx_ring->dma >> 32)); ++ ew32(RDLEN, rx_ring->size); ++ ew32(RDH, 0); ++ ew32(RDT, 0); ++ rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 | ++ E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | ++ (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); ++ ew32(RCTL, rctl); ++ ++ for (i = 0; i < rx_ring->count; i++) { ++ struct e1000_rx_desc *rx_desc = E1000_RX_DESC(*rx_ring, i); ++ struct sk_buff *skb; ++ ++ skb = alloc_skb(2048 + NET_IP_ALIGN, GFP_KERNEL); ++ if (!skb) { ++ ret_val = 6; ++ goto err_nomem; ++ } ++ skb_reserve(skb, NET_IP_ALIGN); ++ rx_ring->buffer_info[i].skb = skb; ++ rx_ring->buffer_info[i].dma = ++ pci_map_single(pdev, skb->data, 2048, ++ PCI_DMA_FROMDEVICE); ++ rx_desc->buffer_addr = ++ cpu_to_le64(rx_ring->buffer_info[i].dma); ++ memset(skb->data, 0x00, skb->len); ++ } ++ ++ return 0; ++ ++err_nomem: ++ e1000_free_desc_rings(adapter); ++ return ret_val; ++} ++ ++static void e1000_phy_disable_receiver(struct e1000_adapter *adapter) ++{ ++ /* Write out to PHY registers 29 and 30 to disable the Receiver. */ ++ e1e_wphy(&adapter->hw, 29, 0x001F); ++ e1e_wphy(&adapter->hw, 30, 0x8FFC); ++ e1e_wphy(&adapter->hw, 29, 0x001A); ++ e1e_wphy(&adapter->hw, 30, 0x8FF0); ++} ++ ++static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ u32 ctrl_reg = 0; ++ u32 stat_reg = 0; ++ ++ adapter->hw.mac.autoneg = 0; ++ ++ if (adapter->hw.phy.type == e1000_phy_m88) { ++ /* Auto-MDI/MDIX Off */ ++ e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); ++ /* reset to update Auto-MDI/MDIX */ ++ e1e_wphy(hw, PHY_CONTROL, 0x9140); ++ /* autoneg off */ ++ e1e_wphy(hw, PHY_CONTROL, 0x8140); ++ } else if (adapter->hw.phy.type == e1000_phy_gg82563) ++ e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, 0x1CC); ++ ++ ctrl_reg = er32(CTRL); ++ ++ if (adapter->hw.phy.type == e1000_phy_ife) { ++ /* force 100, set loopback */ ++ e1e_wphy(hw, PHY_CONTROL, 0x6100); ++ ++ /* Now set up the MAC to the same speed/duplex as the PHY. */ ++ ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ ++ ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ ++ E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ ++ E1000_CTRL_SPD_100 |/* Force Speed to 100 */ ++ E1000_CTRL_FD); /* Force Duplex to FULL */ ++ } else { ++ /* force 1000, set loopback */ ++ e1e_wphy(hw, PHY_CONTROL, 0x4140); ++ ++ /* Now set up the MAC to the same speed/duplex as the PHY. */ ++ ctrl_reg = er32(CTRL); ++ ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ ++ ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ ++ E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ ++ E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */ ++ E1000_CTRL_FD); /* Force Duplex to FULL */ ++ } ++ ++ if (adapter->hw.media_type == e1000_media_type_copper && ++ adapter->hw.phy.type == e1000_phy_m88) { ++ ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */ ++ } else { ++ /* Set the ILOS bit on the fiber Nic if half duplex link is ++ * detected. */ ++ stat_reg = er32(STATUS); ++ if ((stat_reg & E1000_STATUS_FD) == 0) ++ ctrl_reg |= (E1000_CTRL_ILOS | E1000_CTRL_SLU); ++ } ++ ++ ew32(CTRL, ctrl_reg); ++ ++ /* Disable the receiver on the PHY so when a cable is plugged in, the ++ * PHY does not begin to autoneg when a cable is reconnected to the NIC. ++ */ ++ if (adapter->hw.phy.type == e1000_phy_m88) ++ e1000_phy_disable_receiver(adapter); ++ ++ udelay(500); ++ ++ return 0; ++} ++ ++static int e1000_set_82571_fiber_loopback(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ u32 ctrl = er32(CTRL); ++ int link = 0; ++ ++ /* special requirements for 82571/82572 fiber adapters */ ++ ++ /* jump through hoops to make sure link is up because serdes ++ * link is hardwired up */ ++ ctrl |= E1000_CTRL_SLU; ++ ew32(CTRL, ctrl); ++ ++ /* disable autoneg */ ++ ctrl = er32(TXCW); ++ ctrl &= ~(1 << 31); ++ ew32(TXCW, ctrl); ++ ++ link = (er32(STATUS) & E1000_STATUS_LU); ++ ++ if (!link) { ++ /* set invert loss of signal */ ++ ctrl = er32(CTRL); ++ ctrl |= E1000_CTRL_ILOS; ++ ew32(CTRL, ctrl); ++ } ++ ++ /* special write to serdes control register to enable SerDes analog ++ * loopback */ ++#define E1000_SERDES_LB_ON 0x410 ++ ew32(SCTL, E1000_SERDES_LB_ON); ++ msleep(10); ++ ++ return 0; ++} ++ ++/* only call this for fiber/serdes connections to es2lan */ ++static int e1000_set_es2lan_mac_loopback(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ u32 ctrlext = er32(CTRL_EXT); ++ u32 ctrl = er32(CTRL); ++ ++ /* save CTRL_EXT to restore later, reuse an empty variable (unused ++ on mac_type 80003es2lan) */ ++ adapter->tx_fifo_head = ctrlext; ++ ++ /* clear the serdes mode bits, putting the device into mac loopback */ ++ ctrlext &= ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; ++ ew32(CTRL_EXT, ctrlext); ++ ++ /* force speed to 1000/FD, link up */ ++ ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); ++ ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | ++ E1000_CTRL_SPD_1000 | E1000_CTRL_FD); ++ ew32(CTRL, ctrl); ++ ++ /* set mac loopback */ ++ ctrl = er32(RCTL); ++ ctrl |= E1000_RCTL_LBM_MAC; ++ ew32(RCTL, ctrl); ++ ++ /* set testing mode parameters (no need to reset later) */ ++#define KMRNCTRLSTA_OPMODE (0x1F << 16) ++#define KMRNCTRLSTA_OPMODE_1GB_FD_GMII 0x0582 ++ ew32(KMRNCTRLSTA, ++ (KMRNCTRLSTA_OPMODE | KMRNCTRLSTA_OPMODE_1GB_FD_GMII)); ++ ++ return 0; ++} ++ ++static int e1000_setup_loopback_test(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ u32 rctl; ++ ++ if (hw->media_type == e1000_media_type_fiber || ++ hw->media_type == e1000_media_type_internal_serdes) { ++ switch (hw->mac.type) { ++ case e1000_80003es2lan: ++ return e1000_set_es2lan_mac_loopback(adapter); ++ break; ++ case e1000_82571: ++ case e1000_82572: ++ return e1000_set_82571_fiber_loopback(adapter); ++ break; ++ default: ++ rctl = er32(RCTL); ++ rctl |= E1000_RCTL_LBM_TCVR; ++ ew32(RCTL, rctl); ++ return 0; ++ } ++ } else if (hw->media_type == e1000_media_type_copper) { ++ return e1000_integrated_phy_loopback(adapter); ++ } ++ ++ return 7; ++} ++ ++static void e1000_loopback_cleanup(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ u32 rctl; ++ u16 phy_reg; ++ ++ rctl = er32(RCTL); ++ rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); ++ ew32(RCTL, rctl); ++ ++ switch (hw->mac.type) { ++ case e1000_80003es2lan: ++ if (hw->media_type == e1000_media_type_fiber || ++ hw->media_type == e1000_media_type_internal_serdes) { ++ /* restore CTRL_EXT, stealing space from tx_fifo_head */ ++ ew32(CTRL_EXT, ++ adapter->tx_fifo_head); ++ adapter->tx_fifo_head = 0; ++ } ++ /* fall through */ ++ case e1000_82571: ++ case e1000_82572: ++ if (hw->media_type == e1000_media_type_fiber || ++ hw->media_type == e1000_media_type_internal_serdes) { ++#define E1000_SERDES_LB_OFF 0x400 ++ ew32(SCTL, E1000_SERDES_LB_OFF); ++ msleep(10); ++ break; ++ } ++ /* Fall Through */ ++ default: ++ hw->mac.autoneg = 1; ++ if (hw->phy.type == e1000_phy_gg82563) ++ e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, 0x180); ++ e1e_rphy(hw, PHY_CONTROL, &phy_reg); ++ if (phy_reg & MII_CR_LOOPBACK) { ++ phy_reg &= ~MII_CR_LOOPBACK; ++ e1e_wphy(hw, PHY_CONTROL, phy_reg); ++ e1000_commit_phy(hw); ++ } ++ break; ++ } ++} ++ ++static void e1000_create_lbtest_frame(struct sk_buff *skb, ++ unsigned int frame_size) ++{ ++ memset(skb->data, 0xFF, frame_size); ++ frame_size &= ~1; ++ memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1); ++ memset(&skb->data[frame_size / 2 + 10], 0xBE, 1); ++ memset(&skb->data[frame_size / 2 + 12], 0xAF, 1); ++} ++ ++static int e1000_check_lbtest_frame(struct sk_buff *skb, ++ unsigned int frame_size) ++{ ++ frame_size &= ~1; ++ if (*(skb->data + 3) == 0xFF) ++ if ((*(skb->data + frame_size / 2 + 10) == 0xBE) && ++ (*(skb->data + frame_size / 2 + 12) == 0xAF)) ++ return 0; ++ return 13; ++} ++ ++static int e1000_run_loopback_test(struct e1000_adapter *adapter) ++{ ++ struct e1000_ring *tx_ring = &adapter->test_tx_ring; ++ struct e1000_ring *rx_ring = &adapter->test_rx_ring; ++ struct pci_dev *pdev = adapter->pdev; ++ struct e1000_hw *hw = &adapter->hw; ++ int i, j, k, l; ++ int lc; ++ int good_cnt; ++ int ret_val = 0; ++ unsigned long time; ++ ++ ew32(RDT, rx_ring->count - 1); ++ ++ /* Calculate the loop count based on the largest descriptor ring ++ * The idea is to wrap the largest ring a number of times using 64 ++ * send/receive pairs during each loop ++ */ ++ ++ if (rx_ring->count <= tx_ring->count) ++ lc = ((tx_ring->count / 64) * 2) + 1; ++ else ++ lc = ((rx_ring->count / 64) * 2) + 1; ++ ++ k = 0; ++ l = 0; ++ for (j = 0; j <= lc; j++) { /* loop count loop */ ++ for (i = 0; i < 64; i++) { /* send the packets */ ++ e1000_create_lbtest_frame( ++ tx_ring->buffer_info[i].skb, 1024); ++ pci_dma_sync_single_for_device(pdev, ++ tx_ring->buffer_info[k].dma, ++ tx_ring->buffer_info[k].length, ++ PCI_DMA_TODEVICE); ++ k++; ++ if (k == tx_ring->count) ++ k = 0; ++ } ++ ew32(TDT, k); ++ msleep(200); ++ time = jiffies; /* set the start time for the receive */ ++ good_cnt = 0; ++ do { /* receive the sent packets */ ++ pci_dma_sync_single_for_cpu(pdev, ++ rx_ring->buffer_info[l].dma, 2048, ++ PCI_DMA_FROMDEVICE); ++ ++ ret_val = e1000_check_lbtest_frame( ++ rx_ring->buffer_info[l].skb, 1024); ++ if (!ret_val) ++ good_cnt++; ++ l++; ++ if (l == rx_ring->count) ++ l = 0; ++ /* time + 20 msecs (200 msecs on 2.4) is more than ++ * enough time to complete the receives, if it's ++ * exceeded, break and error off ++ */ ++ } while (good_cnt < 64 && jiffies < (time + 20)); ++ if (good_cnt != 64) { ++ ret_val = 13; /* ret_val is the same as mis-compare */ ++ break; ++ } ++ if (jiffies >= (time + 2)) { ++ ret_val = 14; /* error code for time out error */ ++ break; ++ } ++ } /* end loop count loop */ ++ return ret_val; ++} ++ ++static int e1000_loopback_test(struct e1000_adapter *adapter, u64 *data) ++{ ++ /* PHY loopback cannot be performed if SoL/IDER ++ * sessions are active */ ++ if (e1000_check_reset_block(&adapter->hw)) { ++ ndev_err(adapter->netdev, "Cannot do PHY loopback test " ++ "when SoL/IDER is active.\n"); ++ *data = 0; ++ goto out; ++ } ++ ++ *data = e1000_setup_desc_rings(adapter); ++ if (data) ++ goto out; ++ ++ *data = e1000_setup_loopback_test(adapter); ++ if (data) ++ goto err_loopback; ++ ++ *data = e1000_run_loopback_test(adapter); ++ e1000_loopback_cleanup(adapter); ++ ++err_loopback: ++ e1000_free_desc_rings(adapter); ++out: ++ return *data; ++} ++ ++static int e1000_link_test(struct e1000_adapter *adapter, u64 *data) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ ++ *data = 0; ++ if (hw->media_type == e1000_media_type_internal_serdes) { ++ int i = 0; ++ hw->mac.serdes_has_link = 0; ++ ++ /* On some blade server designs, link establishment ++ * could take as long as 2-3 minutes */ ++ do { ++ hw->mac.ops.check_for_link(hw); ++ if (hw->mac.serdes_has_link) ++ return *data; ++ msleep(20); ++ } while (i++ < 3750); ++ ++ *data = 1; ++ } else { ++ hw->mac.ops.check_for_link(hw); ++ if (hw->mac.autoneg) ++ msleep(4000); ++ ++ if (!(er32(STATUS) & ++ E1000_STATUS_LU)) ++ *data = 1; ++ } ++ return *data; ++} ++ ++static int e1000_diag_test_count(struct net_device *netdev) ++{ ++ return E1000_TEST_LEN; ++} ++ ++static void e1000_diag_test(struct net_device *netdev, ++ struct ethtool_test *eth_test, u64 *data) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ u16 autoneg_advertised; ++ u8 forced_speed_duplex; ++ u8 autoneg; ++ bool if_running = netif_running(netdev); ++ ++ set_bit(__E1000_TESTING, &adapter->state); ++ if (eth_test->flags == ETH_TEST_FL_OFFLINE) { ++ /* Offline tests */ ++ ++ /* save speed, duplex, autoneg settings */ ++ autoneg_advertised = adapter->hw.phy.autoneg_advertised; ++ forced_speed_duplex = adapter->hw.mac.forced_speed_duplex; ++ autoneg = adapter->hw.mac.autoneg; ++ ++ ndev_info(netdev, "offline testing starting\n"); ++ ++ /* Link test performed before hardware reset so autoneg doesn't ++ * interfere with test result */ ++ if (e1000_link_test(adapter, &data[4])) ++ eth_test->flags |= ETH_TEST_FL_FAILED; ++ ++ if (if_running) ++ /* indicate we're in test mode */ ++ dev_close(netdev); ++ else ++ e1000_reset(adapter); ++ ++ if (e1000_reg_test(adapter, &data[0])) ++ eth_test->flags |= ETH_TEST_FL_FAILED; ++ ++ e1000_reset(adapter); ++ if (e1000_eeprom_test(adapter, &data[1])) ++ eth_test->flags |= ETH_TEST_FL_FAILED; ++ ++ e1000_reset(adapter); ++ if (e1000_intr_test(adapter, &data[2])) ++ eth_test->flags |= ETH_TEST_FL_FAILED; ++ ++ e1000_reset(adapter); ++ /* make sure the phy is powered up */ ++ e1000_power_up_phy(adapter); ++ if (e1000_loopback_test(adapter, &data[3])) ++ eth_test->flags |= ETH_TEST_FL_FAILED; ++ ++ /* restore speed, duplex, autoneg settings */ ++ adapter->hw.phy.autoneg_advertised = autoneg_advertised; ++ adapter->hw.mac.forced_speed_duplex = forced_speed_duplex; ++ adapter->hw.mac.autoneg = autoneg; ++ ++ /* force this routine to wait until autoneg complete/timeout */ ++ adapter->hw.phy.wait_for_link = 1; ++ e1000_reset(adapter); ++ adapter->hw.phy.wait_for_link = 0; ++ ++ clear_bit(__E1000_TESTING, &adapter->state); ++ if (if_running) ++ dev_open(netdev); ++ } else { ++ ndev_info(netdev, "online testing starting\n"); ++ /* Online tests */ ++ if (e1000_link_test(adapter, &data[4])) ++ eth_test->flags |= ETH_TEST_FL_FAILED; ++ ++ /* Online tests aren't run; pass by default */ ++ data[0] = 0; ++ data[1] = 0; ++ data[2] = 0; ++ data[3] = 0; ++ ++ clear_bit(__E1000_TESTING, &adapter->state); ++ } ++ msleep_interruptible(4 * 1000); ++} ++ ++static void e1000_get_wol(struct net_device *netdev, ++ struct ethtool_wolinfo *wol) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ ++ wol->supported = 0; ++ wol->wolopts = 0; ++ ++ if (!(adapter->flags & FLAG_HAS_WOL)) ++ return; ++ ++ wol->supported = WAKE_UCAST | WAKE_MCAST | ++ WAKE_BCAST | WAKE_MAGIC; ++ ++ /* apply any specific unsupported masks here */ ++ if (adapter->flags & FLAG_NO_WAKE_UCAST) { ++ wol->supported &= ~WAKE_UCAST; ++ ++ if (adapter->wol & E1000_WUFC_EX) ++ ndev_err(netdev, "Interface does not support " ++ "directed (unicast) frame wake-up packets\n"); ++ } ++ ++ if (adapter->wol & E1000_WUFC_EX) ++ wol->wolopts |= WAKE_UCAST; ++ if (adapter->wol & E1000_WUFC_MC) ++ wol->wolopts |= WAKE_MCAST; ++ if (adapter->wol & E1000_WUFC_BC) ++ wol->wolopts |= WAKE_BCAST; ++ if (adapter->wol & E1000_WUFC_MAG) ++ wol->wolopts |= WAKE_MAGIC; ++} ++ ++static int e1000_set_wol(struct net_device *netdev, ++ struct ethtool_wolinfo *wol) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ ++ if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE)) ++ return -EOPNOTSUPP; ++ ++ if (!(adapter->flags & FLAG_HAS_WOL)) ++ return wol->wolopts ? -EOPNOTSUPP : 0; ++ ++ /* these settings will always override what we currently have */ ++ adapter->wol = 0; ++ ++ if (wol->wolopts & WAKE_UCAST) ++ adapter->wol |= E1000_WUFC_EX; ++ if (wol->wolopts & WAKE_MCAST) ++ adapter->wol |= E1000_WUFC_MC; ++ if (wol->wolopts & WAKE_BCAST) ++ adapter->wol |= E1000_WUFC_BC; ++ if (wol->wolopts & WAKE_MAGIC) ++ adapter->wol |= E1000_WUFC_MAG; ++ ++ return 0; ++} ++ ++/* toggle LED 4 times per second = 2 "blinks" per second */ ++#define E1000_ID_INTERVAL (HZ/4) ++ ++/* bit defines for adapter->led_status */ ++#define E1000_LED_ON 0 ++ ++static void e1000_led_blink_callback(unsigned long data) ++{ ++ struct e1000_adapter *adapter = (struct e1000_adapter *) data; ++ ++ if (test_and_change_bit(E1000_LED_ON, &adapter->led_status)) ++ adapter->hw.mac.ops.led_off(&adapter->hw); ++ else ++ adapter->hw.mac.ops.led_on(&adapter->hw); ++ ++ mod_timer(&adapter->blink_timer, jiffies + E1000_ID_INTERVAL); ++} ++ ++static int e1000_phys_id(struct net_device *netdev, u32 data) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ ++ if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ)) ++ data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ); ++ ++ if (adapter->hw.phy.type == e1000_phy_ife) { ++ if (!adapter->blink_timer.function) { ++ init_timer(&adapter->blink_timer); ++ adapter->blink_timer.function = ++ e1000_led_blink_callback; ++ adapter->blink_timer.data = (unsigned long) adapter; ++ } ++ mod_timer(&adapter->blink_timer, jiffies); ++ msleep_interruptible(data * 1000); ++ del_timer_sync(&adapter->blink_timer); ++ e1e_wphy(&adapter->hw, ++ IFE_PHY_SPECIAL_CONTROL_LED, 0); ++ } else { ++ e1000_blink_led(&adapter->hw); ++ msleep_interruptible(data * 1000); ++ } ++ ++ adapter->hw.mac.ops.led_off(&adapter->hw); ++ clear_bit(E1000_LED_ON, &adapter->led_status); ++ adapter->hw.mac.ops.cleanup_led(&adapter->hw); ++ ++ return 0; ++} ++ ++static int e1000_nway_reset(struct net_device *netdev) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ if (netif_running(netdev)) ++ e1000_reinit_locked(adapter); ++ return 0; ++} ++ ++static int e1000_get_stats_count(struct net_device *netdev) ++{ ++ return E1000_STATS_LEN; ++} ++ ++static void e1000_get_ethtool_stats(struct net_device *netdev, ++ struct ethtool_stats *stats, ++ u64 *data) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ int i; ++ ++ e1000_update_stats(adapter); ++ for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) { ++ char *p = (char *)adapter+e1000_gstrings_stats[i].stat_offset; ++ data[i] = (e1000_gstrings_stats[i].sizeof_stat == ++ sizeof(u64)) ? *(u64 *)p : *(u32 *)p; ++ } ++} ++ ++static void e1000_get_strings(struct net_device *netdev, u32 stringset, ++ u8 *data) ++{ ++ u8 *p = data; ++ int i; ++ ++ switch (stringset) { ++ case ETH_SS_TEST: ++ memcpy(data, *e1000_gstrings_test, ++ E1000_TEST_LEN*ETH_GSTRING_LEN); ++ break; ++ case ETH_SS_STATS: ++ for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) { ++ memcpy(p, e1000_gstrings_stats[i].stat_string, ++ ETH_GSTRING_LEN); ++ p += ETH_GSTRING_LEN; ++ } ++ break; ++ } ++} ++ ++static const struct ethtool_ops e1000_ethtool_ops = { ++ .get_settings = e1000_get_settings, ++ .set_settings = e1000_set_settings, ++ .get_drvinfo = e1000_get_drvinfo, ++ .get_regs_len = e1000_get_regs_len, ++ .get_regs = e1000_get_regs, ++ .get_wol = e1000_get_wol, ++ .set_wol = e1000_set_wol, ++ .get_msglevel = e1000_get_msglevel, ++ .set_msglevel = e1000_set_msglevel, ++ .nway_reset = e1000_nway_reset, ++ .get_link = ethtool_op_get_link, ++ .get_eeprom_len = e1000_get_eeprom_len, ++ .get_eeprom = e1000_get_eeprom, ++ .set_eeprom = e1000_set_eeprom, ++ .get_ringparam = e1000_get_ringparam, ++ .set_ringparam = e1000_set_ringparam, ++ .get_pauseparam = e1000_get_pauseparam, ++ .set_pauseparam = e1000_set_pauseparam, ++ .get_rx_csum = e1000_get_rx_csum, ++ .set_rx_csum = e1000_set_rx_csum, ++ .get_tx_csum = e1000_get_tx_csum, ++ .set_tx_csum = e1000_set_tx_csum, ++ .get_sg = ethtool_op_get_sg, ++ .set_sg = ethtool_op_set_sg, ++ .get_tso = ethtool_op_get_tso, ++ .set_tso = e1000_set_tso, ++ .self_test_count = e1000_diag_test_count, ++ .self_test = e1000_diag_test, ++ .get_strings = e1000_get_strings, ++ .phys_id = e1000_phys_id, ++ .get_stats_count = e1000_get_stats_count, ++ .get_ethtool_stats = e1000_get_ethtool_stats, ++}; ++ ++void e1000_set_ethtool_ops(struct net_device *netdev) ++{ ++ SET_ETHTOOL_OPS(netdev, &e1000_ethtool_ops); ++} +diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h +new file mode 100644 +index 0000000..4d562c4 +--- /dev/null ++++ b/drivers/net/e1000e/hw.h +@@ -0,0 +1,862 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2007 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS <linux.nics@intel.com> ++ e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#ifndef _E1000_HW_H_ ++#define _E1000_HW_H_ ++ ++struct e1000_hw; ++struct e1000_adapter; ++ ++#include "defines.h" ++ ++#define er32(reg) __er32(hw, E1000_##reg) ++#define ew32(reg,val) __ew32(hw, E1000_##reg, (val)) ++#define e1e_flush() er32(STATUS) ++ ++#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \ ++ (writel((value), ((a)->hw_addr + reg + ((offset) << 2)))) ++ ++#define E1000_READ_REG_ARRAY(a, reg, offset) \ ++ (readl((a)->hw_addr + reg + ((offset) << 2))) ++ ++enum e1e_registers { ++ E1000_CTRL = 0x00000, /* Device Control - RW */ ++ E1000_STATUS = 0x00008, /* Device Status - RO */ ++ E1000_EECD = 0x00010, /* EEPROM/Flash Control - RW */ ++ E1000_EERD = 0x00014, /* EEPROM Read - RW */ ++ E1000_CTRL_EXT = 0x00018, /* Extended Device Control - RW */ ++ E1000_FLA = 0x0001C, /* Flash Access - RW */ ++ E1000_MDIC = 0x00020, /* MDI Control - RW */ ++ E1000_SCTL = 0x00024, /* SerDes Control - RW */ ++ E1000_FCAL = 0x00028, /* Flow Control Address Low - RW */ ++ E1000_FCAH = 0x0002C, /* Flow Control Address High -RW */ ++ E1000_FEXTNVM = 0x00028, /* Future Extended NVM - RW */ ++ E1000_FCT = 0x00030, /* Flow Control Type - RW */ ++ E1000_VET = 0x00038, /* VLAN Ether Type - RW */ ++ E1000_ICR = 0x000C0, /* Interrupt Cause Read - R/clr */ ++ E1000_ITR = 0x000C4, /* Interrupt Throttling Rate - RW */ ++ E1000_ICS = 0x000C8, /* Interrupt Cause Set - WO */ ++ E1000_IMS = 0x000D0, /* Interrupt Mask Set - RW */ ++ E1000_IMC = 0x000D8, /* Interrupt Mask Clear - WO */ ++ E1000_IAM = 0x000E0, /* Interrupt Acknowledge Auto Mask */ ++ E1000_RCTL = 0x00100, /* RX Control - RW */ ++ E1000_FCTTV = 0x00170, /* Flow Control Transmit Timer Value - RW */ ++ E1000_TXCW = 0x00178, /* TX Configuration Word - RW */ ++ E1000_RXCW = 0x00180, /* RX Configuration Word - RO */ ++ E1000_TCTL = 0x00400, /* TX Control - RW */ ++ E1000_TCTL_EXT = 0x00404, /* Extended TX Control - RW */ ++ E1000_TIPG = 0x00410, /* TX Inter-packet gap -RW */ ++ E1000_AIT = 0x00458, /* Adaptive Interframe Spacing Throttle - RW */ ++ E1000_LEDCTL = 0x00E00, /* LED Control - RW */ ++ E1000_EXTCNF_CTRL = 0x00F00, /* Extended Configuration Control */ ++ E1000_EXTCNF_SIZE = 0x00F08, /* Extended Configuration Size */ ++ E1000_PHY_CTRL = 0x00F10, /* PHY Control Register in CSR */ ++ E1000_PBA = 0x01000, /* Packet Buffer Allocation - RW */ ++ E1000_PBS = 0x01008, /* Packet Buffer Size */ ++ E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */ ++ E1000_EEWR = 0x0102C, /* EEPROM Write Register - RW */ ++ E1000_FLOP = 0x0103C, /* FLASH Opcode Register */ ++ E1000_ERT = 0x02008, /* Early Rx Threshold - RW */ ++ E1000_FCRTL = 0x02160, /* Flow Control Receive Threshold Low - RW */ ++ E1000_FCRTH = 0x02168, /* Flow Control Receive Threshold High - RW */ ++ E1000_PSRCTL = 0x02170, /* Packet Split Receive Control - RW */ ++ E1000_RDBAL = 0x02800, /* RX Descriptor Base Address Low - RW */ ++ E1000_RDBAH = 0x02804, /* RX Descriptor Base Address High - RW */ ++ E1000_RDLEN = 0x02808, /* RX Descriptor Length - RW */ ++ E1000_RDH = 0x02810, /* RX Descriptor Head - RW */ ++ E1000_RDT = 0x02818, /* RX Descriptor Tail - RW */ ++ E1000_RDTR = 0x02820, /* RX Delay Timer - RW */ ++ E1000_RADV = 0x0282C, /* RX Interrupt Absolute Delay Timer - RW */ ++ ++/* Convenience macros ++ * ++ * Note: "_n" is the queue number of the register to be written to. ++ * ++ * Example usage: ++ * E1000_RDBAL_REG(current_rx_queue) ++ * ++ */ ++#define E1000_RDBAL_REG(_n) (E1000_RDBAL + (_n << 8)) ++ E1000_KABGTXD = 0x03004, /* AFE Band Gap Transmit Ref Data */ ++ E1000_TDBAL = 0x03800, /* TX Descriptor Base Address Low - RW */ ++ E1000_TDBAH = 0x03804, /* TX Descriptor Base Address High - RW */ ++ E1000_TDLEN = 0x03808, /* TX Descriptor Length - RW */ ++ E1000_TDH = 0x03810, /* TX Descriptor Head - RW */ ++ E1000_TDT = 0x03818, /* TX Descriptor Tail - RW */ ++ E1000_TIDV = 0x03820, /* TX Interrupt Delay Value - RW */ ++ E1000_TXDCTL = 0x03828, /* TX Descriptor Control - RW */ ++ E1000_TADV = 0x0382C, /* TX Interrupt Absolute Delay Val - RW */ ++ E1000_TARC0 = 0x03840, /* TX Arbitration Count (0) */ ++ E1000_TXDCTL1 = 0x03928, /* TX Descriptor Control (1) - RW */ ++ E1000_TARC1 = 0x03940, /* TX Arbitration Count (1) */ ++ E1000_CRCERRS = 0x04000, /* CRC Error Count - R/clr */ ++ E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */ ++ E1000_SYMERRS = 0x04008, /* Symbol Error Count - R/clr */ ++ E1000_RXERRC = 0x0400C, /* Receive Error Count - R/clr */ ++ E1000_MPC = 0x04010, /* Missed Packet Count - R/clr */ ++ E1000_SCC = 0x04014, /* Single Collision Count - R/clr */ ++ E1000_ECOL = 0x04018, /* Excessive Collision Count - R/clr */ ++ E1000_MCC = 0x0401C, /* Multiple Collision Count - R/clr */ ++ E1000_LATECOL = 0x04020, /* Late Collision Count - R/clr */ ++ E1000_COLC = 0x04028, /* Collision Count - R/clr */ ++ E1000_DC = 0x04030, /* Defer Count - R/clr */ ++ E1000_TNCRS = 0x04034, /* TX-No CRS - R/clr */ ++ E1000_SEC = 0x04038, /* Sequence Error Count - R/clr */ ++ E1000_CEXTERR = 0x0403C, /* Carrier Extension Error Count - R/clr */ ++ E1000_RLEC = 0x04040, /* Receive Length Error Count - R/clr */ ++ E1000_XONRXC = 0x04048, /* XON RX Count - R/clr */ ++ E1000_XONTXC = 0x0404C, /* XON TX Count - R/clr */ ++ E1000_XOFFRXC = 0x04050, /* XOFF RX Count - R/clr */ ++ E1000_XOFFTXC = 0x04054, /* XOFF TX Count - R/clr */ ++ E1000_FCRUC = 0x04058, /* Flow Control RX Unsupported Count- R/clr */ ++ E1000_PRC64 = 0x0405C, /* Packets RX (64 bytes) - R/clr */ ++ E1000_PRC127 = 0x04060, /* Packets RX (65-127 bytes) - R/clr */ ++ E1000_PRC255 = 0x04064, /* Packets RX (128-255 bytes) - R/clr */ ++ E1000_PRC511 = 0x04068, /* Packets RX (255-511 bytes) - R/clr */ ++ E1000_PRC1023 = 0x0406C, /* Packets RX (512-1023 bytes) - R/clr */ ++ E1000_PRC1522 = 0x04070, /* Packets RX (1024-1522 bytes) - R/clr */ ++ E1000_GPRC = 0x04074, /* Good Packets RX Count - R/clr */ ++ E1000_BPRC = 0x04078, /* Broadcast Packets RX Count - R/clr */ ++ E1000_MPRC = 0x0407C, /* Multicast Packets RX Count - R/clr */ ++ E1000_GPTC = 0x04080, /* Good Packets TX Count - R/clr */ ++ E1000_GORCL = 0x04088, /* Good Octets RX Count Low - R/clr */ ++ E1000_GORCH = 0x0408C, /* Good Octets RX Count High - R/clr */ ++ E1000_GOTCL = 0x04090, /* Good Octets TX Count Low - R/clr */ ++ E1000_GOTCH = 0x04094, /* Good Octets TX Count High - R/clr */ ++ E1000_RNBC = 0x040A0, /* RX No Buffers Count - R/clr */ ++ E1000_RUC = 0x040A4, /* RX Undersize Count - R/clr */ ++ E1000_RFC = 0x040A8, /* RX Fragment Count - R/clr */ ++ E1000_ROC = 0x040AC, /* RX Oversize Count - R/clr */ ++ E1000_RJC = 0x040B0, /* RX Jabber Count - R/clr */ ++ E1000_MGTPRC = 0x040B4, /* Management Packets RX Count - R/clr */ ++ E1000_MGTPDC = 0x040B8, /* Management Packets Dropped Count - R/clr */ ++ E1000_MGTPTC = 0x040BC, /* Management Packets TX Count - R/clr */ ++ E1000_TORL = 0x040C0, /* Total Octets RX Low - R/clr */ ++ E1000_TORH = 0x040C4, /* Total Octets RX High - R/clr */ ++ E1000_TOTL = 0x040C8, /* Total Octets TX Low - R/clr */ ++ E1000_TOTH = 0x040CC, /* Total Octets TX High - R/clr */ ++ E1000_TPR = 0x040D0, /* Total Packets RX - R/clr */ ++ E1000_TPT = 0x040D4, /* Total Packets TX - R/clr */ ++ E1000_PTC64 = 0x040D8, /* Packets TX (64 bytes) - R/clr */ ++ E1000_PTC127 = 0x040DC, /* Packets TX (65-127 bytes) - R/clr */ ++ E1000_PTC255 = 0x040E0, /* Packets TX (128-255 bytes) - R/clr */ ++ E1000_PTC511 = 0x040E4, /* Packets TX (256-511 bytes) - R/clr */ ++ E1000_PTC1023 = 0x040E8, /* Packets TX (512-1023 bytes) - R/clr */ ++ E1000_PTC1522 = 0x040EC, /* Packets TX (1024-1522 Bytes) - R/clr */ ++ E1000_MPTC = 0x040F0, /* Multicast Packets TX Count - R/clr */ ++ E1000_BPTC = 0x040F4, /* Broadcast Packets TX Count - R/clr */ ++ E1000_TSCTC = 0x040F8, /* TCP Segmentation Context TX - R/clr */ ++ E1000_TSCTFC = 0x040FC, /* TCP Segmentation Context TX Fail - R/clr */ ++ E1000_IAC = 0x04100, /* Interrupt Assertion Count */ ++ E1000_ICRXPTC = 0x04104, /* Irq Cause Rx Packet Timer Expire Count */ ++ E1000_ICRXATC = 0x04108, /* Irq Cause Rx Abs Timer Expire Count */ ++ E1000_ICTXPTC = 0x0410C, /* Irq Cause Tx Packet Timer Expire Count */ ++ E1000_ICTXATC = 0x04110, /* Irq Cause Tx Abs Timer Expire Count */ ++ E1000_ICTXQEC = 0x04118, /* Irq Cause Tx Queue Empty Count */ ++ E1000_ICTXQMTC = 0x0411C, /* Irq Cause Tx Queue MinThreshold Count */ ++ E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */ ++ E1000_ICRXOC = 0x04124, /* Irq Cause Receiver Overrun Count */ ++ E1000_RXCSUM = 0x05000, /* RX Checksum Control - RW */ ++ E1000_RFCTL = 0x05008, /* Receive Filter Control*/ ++ E1000_MTA = 0x05200, /* Multicast Table Array - RW Array */ ++ E1000_RA = 0x05400, /* Receive Address - RW Array */ ++ E1000_VFTA = 0x05600, /* VLAN Filter Table Array - RW Array */ ++ E1000_WUC = 0x05800, /* Wakeup Control - RW */ ++ E1000_WUFC = 0x05808, /* Wakeup Filter Control - RW */ ++ E1000_WUS = 0x05810, /* Wakeup Status - RO */ ++ E1000_MANC = 0x05820, /* Management Control - RW */ ++ E1000_FFLT = 0x05F00, /* Flexible Filter Length Table - RW Array */ ++ E1000_HOST_IF = 0x08800, /* Host Interface */ ++ ++ E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */ ++ E1000_MANC2H = 0x05860, /* Management Control To Host - RW */ ++ E1000_SW_FW_SYNC = 0x05B5C, /* Software-Firmware Synchronization - RW */ ++ E1000_GCR = 0x05B00, /* PCI-Ex Control */ ++ E1000_FACTPS = 0x05B30, /* Function Active and Power State to MNG */ ++ E1000_SWSM = 0x05B50, /* SW Semaphore */ ++ E1000_FWSM = 0x05B54, /* FW Semaphore */ ++ E1000_HICR = 0x08F00, /* Host Inteface Control */ ++}; ++ ++/* RSS registers */ ++ ++/* IGP01E1000 Specific Registers */ ++#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ ++#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ ++#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ ++#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ ++#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ ++#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ ++ ++#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 ++#define IGP01E1000_PHY_POLARITY_MASK 0x0078 ++ ++#define IGP01E1000_PSCR_AUTO_MDIX 0x1000 ++#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ ++ ++#define IGP01E1000_PSCFR_SMART_SPEED 0x0080 ++ ++#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ ++#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */ ++#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ ++ ++#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 ++ ++#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 ++#define IGP01E1000_PSSR_MDIX 0x0008 ++#define IGP01E1000_PSSR_SPEED_MASK 0xC000 ++#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 ++ ++#define IGP02E1000_PHY_CHANNEL_NUM 4 ++#define IGP02E1000_PHY_AGC_A 0x11B1 ++#define IGP02E1000_PHY_AGC_B 0x12B1 ++#define IGP02E1000_PHY_AGC_C 0x14B1 ++#define IGP02E1000_PHY_AGC_D 0x18B1 ++ ++#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */ ++#define IGP02E1000_AGC_LENGTH_MASK 0x7F ++#define IGP02E1000_AGC_RANGE 15 ++ ++/* manage.c */ ++#define E1000_VFTA_ENTRY_SHIFT 5 ++#define E1000_VFTA_ENTRY_MASK 0x7F ++#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F ++ ++#define E1000_HICR_EN 0x01 /* Enable bit - RO */ ++#define E1000_HICR_C 0x02 /* Driver sets this bit when done ++ * to put command in RAM */ ++#define E1000_HICR_FW_RESET_ENABLE 0x40 ++#define E1000_HICR_FW_RESET 0x80 ++ ++#define E1000_FWSM_MODE_MASK 0xE ++#define E1000_FWSM_MODE_SHIFT 1 ++ ++#define E1000_MNG_IAMT_MODE 0x3 ++#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 ++#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 ++#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 ++#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 ++#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1 ++#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2 ++ ++/* nvm.c */ ++#define E1000_STM_OPCODE 0xDB00 ++ ++#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000 ++#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16 ++#define E1000_KMRNCTRLSTA_REN 0x00200000 ++#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */ ++#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */ ++ ++#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 ++#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */ ++#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */ ++#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */ ++ ++/* IFE PHY Extended Status Control */ ++#define IFE_PESC_POLARITY_REVERSED 0x0100 ++ ++/* IFE PHY Special Control */ ++#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 ++#define IFE_PSC_FORCE_POLARITY 0x0020 ++ ++/* IFE PHY Special Control and LED Control */ ++#define IFE_PSCL_PROBE_MODE 0x0020 ++#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ ++#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ ++ ++/* IFE PHY MDIX Control */ ++#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ ++#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */ ++#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */ ++ ++#define E1000_CABLE_LENGTH_UNDEFINED 0xFF ++ ++#define E1000_DEV_ID_82571EB_COPPER 0x105E ++#define E1000_DEV_ID_82571EB_FIBER 0x105F ++#define E1000_DEV_ID_82571EB_SERDES 0x1060 ++#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 ++#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 ++#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC ++#define E1000_DEV_ID_82572EI_COPPER 0x107D ++#define E1000_DEV_ID_82572EI_FIBER 0x107E ++#define E1000_DEV_ID_82572EI_SERDES 0x107F ++#define E1000_DEV_ID_82572EI 0x10B9 ++#define E1000_DEV_ID_82573E 0x108B ++#define E1000_DEV_ID_82573E_IAMT 0x108C ++#define E1000_DEV_ID_82573L 0x109A ++ ++#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 ++#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 ++#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA ++#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB ++ ++#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 ++#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A ++#define E1000_DEV_ID_ICH8_IGP_C 0x104B ++#define E1000_DEV_ID_ICH8_IFE 0x104C ++#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 ++#define E1000_DEV_ID_ICH8_IFE_G 0x10C5 ++#define E1000_DEV_ID_ICH8_IGP_M 0x104D ++#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD ++#define E1000_DEV_ID_ICH9_IGP_C 0x294C ++#define E1000_DEV_ID_ICH9_IFE 0x10C0 ++#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 ++#define E1000_DEV_ID_ICH9_IFE_G 0x10C2 ++ ++#define E1000_FUNC_1 1 ++ ++enum e1000_mac_type { ++ e1000_82571, ++ e1000_82572, ++ e1000_82573, ++ e1000_80003es2lan, ++ e1000_ich8lan, ++ e1000_ich9lan, ++}; ++ ++enum e1000_media_type { ++ e1000_media_type_unknown = 0, ++ e1000_media_type_copper = 1, ++ e1000_media_type_fiber = 2, ++ e1000_media_type_internal_serdes = 3, ++ e1000_num_media_types ++}; ++ ++enum e1000_nvm_type { ++ e1000_nvm_unknown = 0, ++ e1000_nvm_none, ++ e1000_nvm_eeprom_spi, ++ e1000_nvm_flash_hw, ++ e1000_nvm_flash_sw ++}; ++ ++enum e1000_nvm_override { ++ e1000_nvm_override_none = 0, ++ e1000_nvm_override_spi_small, ++ e1000_nvm_override_spi_large ++}; ++ ++enum e1000_phy_type { ++ e1000_phy_unknown = 0, ++ e1000_phy_none, ++ e1000_phy_m88, ++ e1000_phy_igp, ++ e1000_phy_igp_2, ++ e1000_phy_gg82563, ++ e1000_phy_igp_3, ++ e1000_phy_ife, ++}; ++ ++enum e1000_bus_width { ++ e1000_bus_width_unknown = 0, ++ e1000_bus_width_pcie_x1, ++ e1000_bus_width_pcie_x2, ++ e1000_bus_width_pcie_x4 = 4, ++ e1000_bus_width_32, ++ e1000_bus_width_64, ++ e1000_bus_width_reserved ++}; ++ ++enum e1000_1000t_rx_status { ++ e1000_1000t_rx_status_not_ok = 0, ++ e1000_1000t_rx_status_ok, ++ e1000_1000t_rx_status_undefined = 0xFF ++}; ++ ++enum e1000_rev_polarity{ ++ e1000_rev_polarity_normal = 0, ++ e1000_rev_polarity_reversed, ++ e1000_rev_polarity_undefined = 0xFF ++}; ++ ++enum e1000_fc_mode { ++ e1000_fc_none = 0, ++ e1000_fc_rx_pause, ++ e1000_fc_tx_pause, ++ e1000_fc_full, ++ e1000_fc_default = 0xFF ++}; ++ ++enum e1000_ms_type { ++ e1000_ms_hw_default = 0, ++ e1000_ms_force_master, ++ e1000_ms_force_slave, ++ e1000_ms_auto ++}; ++ ++enum e1000_smart_speed { ++ e1000_smart_speed_default = 0, ++ e1000_smart_speed_on, ++ e1000_smart_speed_off ++}; ++ ++/* Receive Descriptor */ ++struct e1000_rx_desc { ++ u64 buffer_addr; /* Address of the descriptor's data buffer */ ++ u16 length; /* Length of data DMAed into data buffer */ ++ u16 csum; /* Packet checksum */ ++ u8 status; /* Descriptor status */ ++ u8 errors; /* Descriptor Errors */ ++ u16 special; ++}; ++ ++/* Receive Descriptor - Extended */ ++union e1000_rx_desc_extended { ++ struct { ++ u64 buffer_addr; ++ u64 reserved; ++ } read; ++ struct { ++ struct { ++ u32 mrq; /* Multiple Rx Queues */ ++ union { ++ u32 rss; /* RSS Hash */ ++ struct { ++ u16 ip_id; /* IP id */ ++ u16 csum; /* Packet Checksum */ ++ } csum_ip; ++ } hi_dword; ++ } lower; ++ struct { ++ u32 status_error; /* ext status/error */ ++ u16 length; ++ u16 vlan; /* VLAN tag */ ++ } upper; ++ } wb; /* writeback */ ++}; ++ ++#define MAX_PS_BUFFERS 4 ++/* Receive Descriptor - Packet Split */ ++union e1000_rx_desc_packet_split { ++ struct { ++ /* one buffer for protocol header(s), three data buffers */ ++ u64 buffer_addr[MAX_PS_BUFFERS]; ++ } read; ++ struct { ++ struct { ++ u32 mrq; /* Multiple Rx Queues */ ++ union { ++ u32 rss; /* RSS Hash */ ++ struct { ++ u16 ip_id; /* IP id */ ++ u16 csum; /* Packet Checksum */ ++ } csum_ip; ++ } hi_dword; ++ } lower; ++ struct { ++ u32 status_error; /* ext status/error */ ++ u16 length0; /* length of buffer 0 */ ++ u16 vlan; /* VLAN tag */ ++ } middle; ++ struct { ++ u16 header_status; ++ u16 length[3]; /* length of buffers 1-3 */ ++ } upper; ++ u64 reserved; ++ } wb; /* writeback */ ++}; ++ ++/* Transmit Descriptor */ ++struct e1000_tx_desc { ++ u64 buffer_addr; /* Address of the descriptor's data buffer */ ++ union { ++ u32 data; ++ struct { ++ u16 length; /* Data buffer length */ ++ u8 cso; /* Checksum offset */ ++ u8 cmd; /* Descriptor control */ ++ } flags; ++ } lower; ++ union { ++ u32 data; ++ struct { ++ u8 status; /* Descriptor status */ ++ u8 css; /* Checksum start */ ++ u16 special; ++ } fields; ++ } upper; ++}; ++ ++/* Offload Context Descriptor */ ++struct e1000_context_desc { ++ union { ++ u32 ip_config; ++ struct { ++ u8 ipcss; /* IP checksum start */ ++ u8 ipcso; /* IP checksum offset */ ++ u16 ipcse; /* IP checksum end */ ++ } ip_fields; ++ } lower_setup; ++ union { ++ u32 tcp_config; ++ struct { ++ u8 tucss; /* TCP checksum start */ ++ u8 tucso; /* TCP checksum offset */ ++ u16 tucse; /* TCP checksum end */ ++ } tcp_fields; ++ } upper_setup; ++ u32 cmd_and_length; ++ union { ++ u32 data; ++ struct { ++ u8 status; /* Descriptor status */ ++ u8 hdr_len; /* Header length */ ++ u16 mss; /* Maximum segment size */ ++ } fields; ++ } tcp_seg_setup; ++}; ++ ++/* Offload data descriptor */ ++struct e1000_data_desc { ++ u64 buffer_addr; /* Address of the descriptor's buffer address */ ++ union { ++ u32 data; ++ struct { ++ u16 length; /* Data buffer length */ ++ u8 typ_len_ext; ++ u8 cmd; ++ } flags; ++ } lower; ++ union { ++ u32 data; ++ struct { ++ u8 status; /* Descriptor status */ ++ u8 popts; /* Packet Options */ ++ u16 special; /* */ ++ } fields; ++ } upper; ++}; ++ ++/* Statistics counters collected by the MAC */ ++struct e1000_hw_stats { ++ u64 crcerrs; ++ u64 algnerrc; ++ u64 symerrs; ++ u64 rxerrc; ++ u64 mpc; ++ u64 scc; ++ u64 ecol; ++ u64 mcc; ++ u64 latecol; ++ u64 colc; ++ u64 dc; ++ u64 tncrs; ++ u64 sec; ++ u64 cexterr; ++ u64 rlec; ++ u64 xonrxc; ++ u64 xontxc; ++ u64 xoffrxc; ++ u64 xofftxc; ++ u64 fcruc; ++ u64 prc64; ++ u64 prc127; ++ u64 prc255; ++ u64 prc511; ++ u64 prc1023; ++ u64 prc1522; ++ u64 gprc; ++ u64 bprc; ++ u64 mprc; ++ u64 gptc; ++ u64 gorcl; ++ u64 gorch; ++ u64 gotcl; ++ u64 gotch; ++ u64 rnbc; ++ u64 ruc; ++ u64 rfc; ++ u64 roc; ++ u64 rjc; ++ u64 mgprc; ++ u64 mgpdc; ++ u64 mgptc; ++ u64 torl; ++ u64 torh; ++ u64 totl; ++ u64 toth; ++ u64 tpr; ++ u64 tpt; ++ u64 ptc64; ++ u64 ptc127; ++ u64 ptc255; ++ u64 ptc511; ++ u64 ptc1023; ++ u64 ptc1522; ++ u64 mptc; ++ u64 bptc; ++ u64 tsctc; ++ u64 tsctfc; ++ u64 iac; ++ u64 icrxptc; ++ u64 icrxatc; ++ u64 ictxptc; ++ u64 ictxatc; ++ u64 ictxqec; ++ u64 ictxqmtc; ++ u64 icrxdmtc; ++ u64 icrxoc; ++}; ++ ++struct e1000_phy_stats { ++ u32 idle_errors; ++ u32 receive_errors; ++}; ++ ++struct e1000_host_mng_dhcp_cookie { ++ u32 signature; ++ u8 status; ++ u8 reserved0; ++ u16 vlan_id; ++ u32 reserved1; ++ u16 reserved2; ++ u8 reserved3; ++ u8 checksum; ++}; ++ ++/* Host Interface "Rev 1" */ ++struct e1000_host_command_header { ++ u8 command_id; ++ u8 command_length; ++ u8 command_options; ++ u8 checksum; ++}; ++ ++#define E1000_HI_MAX_DATA_LENGTH 252 ++struct e1000_host_command_info { ++ struct e1000_host_command_header command_header; ++ u8 command_data[E1000_HI_MAX_DATA_LENGTH]; ++}; ++ ++/* Host Interface "Rev 2" */ ++struct e1000_host_mng_command_header { ++ u8 command_id; ++ u8 checksum; ++ u16 reserved1; ++ u16 reserved2; ++ u16 command_length; ++}; ++ ++#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 ++struct e1000_host_mng_command_info { ++ struct e1000_host_mng_command_header command_header; ++ u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; ++}; ++ ++/* Function pointers and static data for the MAC. */ ++struct e1000_mac_operations { ++ u32 mng_mode_enab; ++ ++ s32 (*check_for_link)(struct e1000_hw *); ++ s32 (*cleanup_led)(struct e1000_hw *); ++ void (*clear_hw_cntrs)(struct e1000_hw *); ++ s32 (*get_bus_info)(struct e1000_hw *); ++ s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); ++ s32 (*led_on)(struct e1000_hw *); ++ s32 (*led_off)(struct e1000_hw *); ++ void (*mc_addr_list_update)(struct e1000_hw *, u8 *, u32, u32, ++ u32); ++ s32 (*reset_hw)(struct e1000_hw *); ++ s32 (*init_hw)(struct e1000_hw *); ++ s32 (*setup_link)(struct e1000_hw *); ++ s32 (*setup_physical_interface)(struct e1000_hw *); ++}; ++ ++/* Function pointers for the PHY. */ ++struct e1000_phy_operations { ++ s32 (*acquire_phy)(struct e1000_hw *); ++ s32 (*check_reset_block)(struct e1000_hw *); ++ s32 (*commit_phy)(struct e1000_hw *); ++ s32 (*force_speed_duplex)(struct e1000_hw *); ++ s32 (*get_cfg_done)(struct e1000_hw *hw); ++ s32 (*get_cable_length)(struct e1000_hw *); ++ s32 (*get_phy_info)(struct e1000_hw *); ++ s32 (*read_phy_reg)(struct e1000_hw *, u32, u16 *); ++ void (*release_phy)(struct e1000_hw *); ++ s32 (*reset_phy)(struct e1000_hw *); ++ s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); ++ s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); ++ s32 (*write_phy_reg)(struct e1000_hw *, u32, u16); ++}; ++ ++/* Function pointers for the NVM. */ ++struct e1000_nvm_operations { ++ s32 (*acquire_nvm)(struct e1000_hw *); ++ s32 (*read_nvm)(struct e1000_hw *, u16, u16, u16 *); ++ void (*release_nvm)(struct e1000_hw *); ++ s32 (*update_nvm)(struct e1000_hw *); ++ s32 (*valid_led_default)(struct e1000_hw *, u16 *); ++ s32 (*validate_nvm)(struct e1000_hw *); ++ s32 (*write_nvm)(struct e1000_hw *, u16, u16, u16 *); ++}; ++ ++struct e1000_mac_info { ++ struct e1000_mac_operations ops; ++ ++ u8 addr[6]; ++ u8 perm_addr[6]; ++ ++ enum e1000_mac_type type; ++ enum e1000_fc_mode fc; ++ enum e1000_fc_mode original_fc; ++ ++ u32 collision_delta; ++ u32 ledctl_default; ++ u32 ledctl_mode1; ++ u32 ledctl_mode2; ++ u32 max_frame_size; ++ u32 mc_filter_type; ++ u32 min_frame_size; ++ u32 tx_packet_delta; ++ u32 txcw; ++ ++ u16 current_ifs_val; ++ u16 ifs_max_val; ++ u16 ifs_min_val; ++ u16 ifs_ratio; ++ u16 ifs_step_size; ++ u16 mta_reg_count; ++ u16 rar_entry_count; ++ u16 fc_high_water; ++ u16 fc_low_water; ++ u16 fc_pause_time; ++ ++ u8 forced_speed_duplex; ++ ++ bool arc_subsystem_valid; ++ bool autoneg; ++ bool autoneg_failed; ++ bool get_link_status; ++ bool in_ifs_mode; ++ bool serdes_has_link; ++ bool tx_pkt_filtering; ++}; ++ ++struct e1000_phy_info { ++ struct e1000_phy_operations ops; ++ ++ enum e1000_phy_type type; ++ ++ enum e1000_1000t_rx_status local_rx; ++ enum e1000_1000t_rx_status remote_rx; ++ enum e1000_ms_type ms_type; ++ enum e1000_ms_type original_ms_type; ++ enum e1000_rev_polarity cable_polarity; ++ enum e1000_smart_speed smart_speed; ++ ++ u32 addr; ++ u32 id; ++ u32 reset_delay_us; /* in usec */ ++ u32 revision; ++ ++ u16 autoneg_advertised; ++ u16 autoneg_mask; ++ u16 cable_length; ++ u16 max_cable_length; ++ u16 min_cable_length; ++ ++ u8 mdix; ++ ++ bool disable_polarity_correction; ++ bool is_mdix; ++ bool polarity_correction; ++ bool speed_downgraded; ++ bool wait_for_link; ++}; ++ ++struct e1000_nvm_info { ++ struct e1000_nvm_operations ops; ++ ++ enum e1000_nvm_type type; ++ enum e1000_nvm_override override; ++ ++ u32 flash_bank_size; ++ u32 flash_base_addr; ++ ++ u16 word_size; ++ u16 delay_usec; ++ u16 address_bits; ++ u16 opcode_bits; ++ u16 page_size; ++}; ++ ++struct e1000_bus_info { ++ enum e1000_bus_width width; ++ ++ u16 func; ++}; ++ ++struct e1000_dev_spec_82571 { ++ bool laa_is_present; ++}; ++ ++struct e1000_shadow_ram { ++ u16 value; ++ bool modified; ++}; ++ ++#define E1000_ICH8_SHADOW_RAM_WORDS 2048 ++ ++struct e1000_dev_spec_ich8lan { ++ bool kmrn_lock_loss_workaround_enabled; ++ struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS]; ++}; ++ ++struct e1000_hw { ++ struct e1000_adapter *adapter; ++ ++ u8 __iomem *hw_addr; ++ u8 __iomem *flash_address; ++ ++ struct e1000_mac_info mac; ++ struct e1000_phy_info phy; ++ struct e1000_nvm_info nvm; ++ struct e1000_bus_info bus; ++ struct e1000_host_mng_dhcp_cookie mng_cookie; ++ ++ union { ++ struct e1000_dev_spec_82571 e82571; ++ struct e1000_dev_spec_ich8lan ich8lan; ++ } dev_spec; ++ ++ enum e1000_media_type media_type; ++}; ++ ++#ifdef DEBUG ++#define hw_dbg(hw, format, arg...) \ ++ printk(KERN_DEBUG, "%s: " format, e1000_get_hw_dev_name(hw), ##arg); ++#else ++static inline int __attribute__ ((format (printf, 2, 3))) ++hw_dbg(struct e1000_hw *hw, const char *format, ...) ++{ ++ return 0; ++} ++#endif ++ ++#endif +diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c +new file mode 100644 +index 0000000..5967139 +--- /dev/null ++++ b/drivers/net/e1000e/ich8lan.c +@@ -0,0 +1,2297 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2007 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS <linux.nics@intel.com> ++ e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++/* ++ * 82562G-2 10/100 Network Connection ++ * 82562GT 10/100 Network Connection ++ * 82562GT-2 10/100 Network Connection ++ * 82562V 10/100 Network Connection ++ * 82562V-2 10/100 Network Connection ++ * 82566DC-2 Gigabit Network Connection ++ * 82566DC Gigabit Network Connection ++ * 82566DM-2 Gigabit Network Connection ++ * 82566DM Gigabit Network Connection ++ * 82566MC Gigabit Network Connection ++ * 82566MM Gigabit Network Connection ++ */ ++ ++#include "e1000.h" ++ ++#define ICH_FLASH_GFPREG 0x0000 ++#define ICH_FLASH_HSFSTS 0x0004 ++#define ICH_FLASH_HSFCTL 0x0006 ++#define ICH_FLASH_FADDR 0x0008 ++#define ICH_FLASH_FDATA0 0x0010 ++ ++#define ICH_FLASH_READ_COMMAND_TIMEOUT 500 ++#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500 ++#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000 ++#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF ++#define ICH_FLASH_CYCLE_REPEAT_COUNT 10 ++ ++#define ICH_CYCLE_READ 0 ++#define ICH_CYCLE_WRITE 2 ++#define ICH_CYCLE_ERASE 3 ++ ++#define FLASH_GFPREG_BASE_MASK 0x1FFF ++#define FLASH_SECTOR_ADDR_SHIFT 12 ++ ++#define ICH_FLASH_SEG_SIZE_256 256 ++#define ICH_FLASH_SEG_SIZE_4K 4096 ++#define ICH_FLASH_SEG_SIZE_8K 8192 ++#define ICH_FLASH_SEG_SIZE_64K 65536 ++ ++ ++#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ ++ ++#define E1000_ICH_MNG_IAMT_MODE 0x2 ++ ++#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ ++ (ID_LED_DEF1_OFF2 << 8) | \ ++ (ID_LED_DEF1_ON2 << 4) | \ ++ (ID_LED_DEF1_DEF2)) ++ ++#define E1000_ICH_NVM_SIG_WORD 0x13 ++#define E1000_ICH_NVM_SIG_MASK 0xC000 ++ ++#define E1000_ICH8_LAN_INIT_TIMEOUT 1500 ++ ++#define E1000_FEXTNVM_SW_CONFIG 1 ++#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */ ++ ++#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL ++ ++#define E1000_ICH_RAR_ENTRIES 7 ++ ++#define PHY_PAGE_SHIFT 5 ++#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ ++ ((reg) & MAX_PHY_REG_ADDRESS)) ++#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ ++#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ ++ ++#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 ++#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 ++#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 ++ ++/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ ++/* Offset 04h HSFSTS */ ++union ich8_hws_flash_status { ++ struct ich8_hsfsts { ++ u16 flcdone :1; /* bit 0 Flash Cycle Done */ ++ u16 flcerr :1; /* bit 1 Flash Cycle Error */ ++ u16 dael :1; /* bit 2 Direct Access error Log */ ++ u16 berasesz :2; /* bit 4:3 Sector Erase Size */ ++ u16 flcinprog :1; /* bit 5 flash cycle in Progress */ ++ u16 reserved1 :2; /* bit 13:6 Reserved */ ++ u16 reserved2 :6; /* bit 13:6 Reserved */ ++ u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */ ++ u16 flockdn :1; /* bit 15 Flash Config Lock-Down */ ++ } hsf_status; ++ u16 regval; ++}; ++ ++/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ ++/* Offset 06h FLCTL */ ++union ich8_hws_flash_ctrl { ++ struct ich8_hsflctl { ++ u16 flcgo :1; /* 0 Flash Cycle Go */ ++ u16 flcycle :2; /* 2:1 Flash Cycle */ ++ u16 reserved :5; /* 7:3 Reserved */ ++ u16 fldbcount :2; /* 9:8 Flash Data Byte Count */ ++ u16 flockdn :6; /* 15:10 Reserved */ ++ } hsf_ctrl; ++ u16 regval; ++}; ++ ++/* ICH Flash Region Access Permissions */ ++union ich8_hws_flash_regacc { ++ struct ich8_flracc { ++ u32 grra :8; /* 0:7 GbE region Read Access */ ++ u32 grwa :8; /* 8:15 GbE region Write Access */ ++ u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */ ++ u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */ ++ } hsf_flregacc; ++ u16 regval; ++}; ++ ++static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); ++static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); ++static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); ++static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw); ++static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); ++static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, ++ u32 offset, u8 byte); ++static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, ++ u16 *data); ++static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, ++ u8 size, u16 *data); ++static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); ++static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); ++ ++static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) ++{ ++ return readw(hw->flash_address + reg); ++} ++ ++static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) ++{ ++ return readl(hw->flash_address + reg); ++} ++ ++static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) ++{ ++ writew(val, hw->flash_address + reg); ++} ++ ++static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) ++{ ++ writel(val, hw->flash_address + reg); ++} ++ ++#define er16flash(reg) __er16flash(hw, (reg)) ++#define er32flash(reg) __er32flash(hw, (reg)) ++#define ew16flash(reg,val) __ew16flash(hw, (reg), (val)) ++#define ew32flash(reg,val) __ew32flash(hw, (reg), (val)) ++ ++/** ++ * e1000_init_phy_params_ich8lan - Initialize PHY function pointers ++ * @hw: pointer to the HW structure ++ * ++ * Initialize family-specific PHY parameters and function pointers. ++ **/ ++static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val = E1000_SUCCESS; ++ u16 i = 0; ++ ++ phy->addr = 1; ++ phy->reset_delay_us = 100; ++ ++ phy->id = 0; ++ while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) && ++ (i++ < 100)) { ++ msleep(1); ++ ret_val = e1000_get_phy_id(hw); ++ if (ret_val) ++ goto out; ++ } ++ ++ /* Verify phy id */ ++ switch (phy->id) { ++ case IGP03E1000_E_PHY_ID: ++ phy->type = e1000_phy_igp_3; ++ phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; ++ break; ++ case IFE_E_PHY_ID: ++ case IFE_PLUS_E_PHY_ID: ++ case IFE_C_E_PHY_ID: ++ phy->type = e1000_phy_ife; ++ phy->autoneg_mask = E1000_ALL_NOT_GIG; ++ break; ++ default: ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers ++ * @hw: pointer to the HW structure ++ * ++ * Initialize family-specific NVM parameters and function ++ * pointers. ++ **/ ++static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; ++ u32 gfpreg; ++ u32 sector_base_addr; ++ u32 sector_end_addr; ++ s32 ret_val = E1000_SUCCESS; ++ u16 i; ++ ++ /* Can't read flash registers if the register set isn't mapped. ++ */ ++ if (!hw->flash_address) { ++ hw_dbg(hw, "ERROR: Flash registers not mapped\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ nvm->type = e1000_nvm_flash_sw; ++ ++ gfpreg = er32flash(ICH_FLASH_GFPREG); ++ ++ /* sector_X_addr is a "sector"-aligned address (4096 bytes) ++ * Add 1 to sector_end_addr since this sector is included in ++ * the overall size. */ ++ sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; ++ sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; ++ ++ /* flash_base_addr is byte-aligned */ ++ nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; ++ ++ /* find total size of the NVM, then cut in half since the total ++ * size represents two separate NVM banks. */ ++ nvm->flash_bank_size = (sector_end_addr - sector_base_addr) ++ << FLASH_SECTOR_ADDR_SHIFT; ++ nvm->flash_bank_size /= 2; ++ /* Adjust to word count */ ++ nvm->flash_bank_size /= sizeof(u16); ++ ++ nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; ++ ++ /* Clear shadow ram */ ++ for (i = 0; i < nvm->word_size; i++) { ++ dev_spec->shadow_ram[i].modified = 0; ++ dev_spec->shadow_ram[i].value = 0xFFFF; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_init_mac_params_ich8lan - Initialize MAC function pointers ++ * @hw: pointer to the HW structure ++ * ++ * Initialize family-specific MAC parameters and function ++ * pointers. ++ **/ ++static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ struct e1000_mac_info *mac = &hw->mac; ++ ++ /* Set media type function pointer */ ++ hw->media_type = e1000_media_type_copper; ++ ++ /* Set mta register count */ ++ mac->mta_reg_count = 32; ++ /* Set rar entry count */ ++ mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; ++ if (mac->type == e1000_ich8lan) ++ mac->rar_entry_count--; ++ /* Set if manageability features are enabled. */ ++ mac->arc_subsystem_valid = 1; ++ ++ /* Enable PCS Lock-loss workaround for ICH8 */ ++ if (mac->type == e1000_ich8lan) ++ e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, 1); ++ ++ return E1000_SUCCESS; ++} ++ ++static s32 e1000_get_invariants_ich8lan(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ s32 rc; ++ ++ rc = e1000_init_mac_params_ich8lan(adapter); ++ if (rc) ++ return rc; ++ ++ rc = e1000_init_nvm_params_ich8lan(hw); ++ if (rc) ++ return rc; ++ ++ rc = e1000_init_phy_params_ich8lan(hw); ++ if (rc) ++ return rc; ++ ++ if ((adapter->hw.mac.type == e1000_ich8lan) && ++ (adapter->hw.phy.type == e1000_phy_igp_3)) ++ adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_acquire_swflag_ich8lan - Acquire software control flag ++ * @hw: pointer to the HW structure ++ * ++ * Acquires the software control flag for performing NVM and PHY ++ * operations. This is a function pointer entry point only called by ++ * read/write routines for the PHY and NVM parts. ++ **/ ++static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) ++{ ++ u32 extcnf_ctrl; ++ u32 timeout = PHY_CFG_TIMEOUT; ++ s32 ret_val = E1000_SUCCESS; ++ ++ while (timeout) { ++ extcnf_ctrl = er32(EXTCNF_CTRL); ++ extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; ++ ew32(EXTCNF_CTRL, extcnf_ctrl); ++ ++ extcnf_ctrl = er32(EXTCNF_CTRL); ++ if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) ++ break; ++ mdelay(1); ++ timeout--; ++ } ++ ++ if (!timeout) { ++ hw_dbg(hw, "FW or HW has locked the resource for too long.\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_release_swflag_ich8lan - Release software control flag ++ * @hw: pointer to the HW structure ++ * ++ * Releases the software control flag for performing NVM and PHY operations. ++ * This is a function pointer entry point only called by read/write ++ * routines for the PHY and NVM parts. ++ **/ ++static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) ++{ ++ u32 extcnf_ctrl; ++ ++ extcnf_ctrl = er32(EXTCNF_CTRL); ++ extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; ++ ew32(EXTCNF_CTRL, extcnf_ctrl); ++} ++ ++/** ++ * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked ++ * @hw: pointer to the HW structure ++ * ++ * Checks if firmware is blocking the reset of the PHY. ++ * This is a function pointer entry point only called by ++ * reset routines. ++ **/ ++static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) ++{ ++ u32 fwsm; ++ ++ fwsm = er32(FWSM); ++ ++ return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS ++ : E1000_BLK_PHY_RESET; ++} ++ ++/** ++ * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex ++ * @hw: pointer to the HW structure ++ * ++ * Forces the speed and duplex settings of the PHY. ++ * This is a function pointer entry point only called by ++ * PHY setup routines. ++ **/ ++static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 data; ++ bool link; ++ ++ if (phy->type != e1000_phy_ife) { ++ ret_val = e1000_phy_force_speed_duplex_igp(hw); ++ goto out; ++ } ++ ++ ret_val = e1e_rphy(hw, PHY_CONTROL, &data); ++ if (ret_val) ++ goto out; ++ ++ e1000_phy_force_speed_duplex_setup(hw, &data); ++ ++ ret_val = e1e_wphy(hw, PHY_CONTROL, data); ++ if (ret_val) ++ goto out; ++ ++ /* Disable MDI-X support for 10/100 */ ++ ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~IFE_PMC_AUTO_MDIX; ++ data &= ~IFE_PMC_FORCE_MDIX; ++ ++ ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data); ++ if (ret_val) ++ goto out; ++ ++ hw_dbg(hw, "IFE PMC: %X\n", data); ++ ++ udelay(1); ++ ++ if (phy->wait_for_link) { ++ hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n"); ++ ++ ret_val = e1000_phy_has_link_generic(hw, ++ PHY_FORCE_LIMIT, ++ 100000, ++ &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) ++ hw_dbg(hw, "Link taking longer than expected.\n"); ++ ++ /* Try once more */ ++ ret_val = e1000_phy_has_link_generic(hw, ++ PHY_FORCE_LIMIT, ++ 100000, ++ &link); ++ if (ret_val) ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_hw_reset_ich8lan - Performs a PHY reset ++ * @hw: pointer to the HW structure ++ * ++ * Resets the PHY ++ * This is a function pointer entry point called by drivers ++ * or other shared routines. ++ **/ ++static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ u32 i; ++ u32 data, cnf_size, cnf_base_addr, sw_cfg_mask; ++ s32 ret_val; ++ u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT; ++ u16 word_addr, reg_data, reg_addr, phy_page = 0; ++ ++ ret_val = e1000_phy_hw_reset_generic(hw); ++ if (ret_val) ++ goto out; ++ ++ /* Initialize the PHY from the NVM on ICH platforms. This ++ * is needed due to an issue where the NVM configuration is ++ * not properly autoloaded after power transitions. ++ * Therefore, after each PHY reset, we will load the ++ * configuration data out of the NVM manually. ++ */ ++ if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) { ++ struct e1000_adapter *adapter = hw->adapter; ++ ++ /* Check if SW needs configure the PHY */ ++ if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) || ++ (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M)) ++ sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; ++ else ++ sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; ++ ++ data = er32(FEXTNVM); ++ if (!(data & sw_cfg_mask)) ++ goto out; ++ ++ /* Wait for basic configuration completes before proceeding*/ ++ do { ++ data = er32(STATUS); ++ data &= E1000_STATUS_LAN_INIT_DONE; ++ udelay(100); ++ } while ((!data) && --loop); ++ ++ /* If basic configuration is incomplete before the above loop ++ * count reaches 0, loading the configuration from NVM will ++ * leave the PHY in a bad state possibly resulting in no link. ++ */ ++ if (loop == 0) { ++ hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n"); ++ } ++ ++ /* Clear the Init Done bit for the next init event */ ++ data = er32(STATUS); ++ data &= ~E1000_STATUS_LAN_INIT_DONE; ++ ew32(STATUS, data); ++ ++ /* Make sure HW does not configure LCD from PHY ++ * extended configuration before SW configuration */ ++ data = er32(EXTCNF_CTRL); ++ if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) ++ goto out; ++ ++ cnf_size = er32(EXTCNF_SIZE); ++ cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; ++ cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; ++ if (!cnf_size) ++ goto out; ++ ++ cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; ++ cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; ++ ++ /* Configure LCD from extended configuration ++ * region. */ ++ ++ /* cnf_base_addr is in DWORD */ ++ word_addr = (u16)(cnf_base_addr << 1); ++ ++ for (i = 0; i < cnf_size; i++) { ++ ret_val = e1000_read_nvm(hw, ++ (word_addr + i * 2), ++ 1, ++ ®_data); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000_read_nvm(hw, ++ (word_addr + i * 2 + 1), ++ 1, ++ ®_addr); ++ if (ret_val) ++ goto out; ++ ++ /* Save off the PHY page for future writes. */ ++ if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { ++ phy_page = reg_data; ++ continue; ++ } ++ ++ reg_addr |= phy_page; ++ ++ ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data); ++ if (ret_val) ++ goto out; ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states ++ * @hw: pointer to the HW structure ++ * ++ * Populates "phy" structure with various feature states. ++ * This function is only called by other family-specific ++ * routines. ++ **/ ++static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 data; ++ bool link; ++ ++ ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) { ++ hw_dbg(hw, "Phy info is only valid if link is up\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data); ++ if (ret_val) ++ goto out; ++ phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE)); ++ ++ if (phy->polarity_correction) { ++ ret_val = e1000_check_polarity_ife_ich8lan(hw); ++ if (ret_val) ++ goto out; ++ } else { ++ /* Polarity is forced */ ++ phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) ++ ? e1000_rev_polarity_reversed ++ : e1000_rev_polarity_normal; ++ } ++ ++ ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); ++ if (ret_val) ++ goto out; ++ ++ phy->is_mdix = (data & IFE_PMC_MDIX_STATUS); ++ ++ /* The following parameters are undefined for 10/100 operation. */ ++ phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; ++ phy->local_rx = e1000_1000t_rx_status_undefined; ++ phy->remote_rx = e1000_1000t_rx_status_undefined; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info ++ * @hw: pointer to the HW structure ++ * ++ * Wrapper for calling the get_phy_info routines for the appropriate phy type. ++ * This is a function pointer entry point called by drivers ++ * or other shared routines. ++ **/ ++static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw) ++{ ++ s32 ret_val = -E1000_ERR_PHY_TYPE; ++ ++ switch (hw->phy.type) { ++ case e1000_phy_ife: ++ ret_val = e1000_get_phy_info_ife_ich8lan(hw); ++ break; ++ case e1000_phy_igp_3: ++ ret_val = e1000_get_phy_info_igp(hw); ++ break; ++ default: ++ break; ++ } ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY ++ * @hw: pointer to the HW structure ++ * ++ * Polarity is determined on the polarity reveral feature being enabled. ++ * This function is only called by other family-specific ++ * routines. ++ **/ ++static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_data, offset, mask; ++ ++ /* Polarity is determined based on the reversal feature ++ * being enabled. ++ */ ++ if (phy->polarity_correction) { ++ offset = IFE_PHY_EXTENDED_STATUS_CONTROL; ++ mask = IFE_PESC_POLARITY_REVERSED; ++ } else { ++ offset = IFE_PHY_SPECIAL_CONTROL; ++ mask = IFE_PSC_FORCE_POLARITY; ++ } ++ ++ ret_val = e1e_rphy(hw, offset, &phy_data); ++ ++ if (!ret_val) ++ phy->cable_polarity = (phy_data & mask) ++ ? e1000_rev_polarity_reversed ++ : e1000_rev_polarity_normal; ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state ++ * @hw: pointer to the HW structure ++ * @active: TRUE to enable LPLU, FALSE to disable ++ * ++ * Sets the LPLU D0 state according to the active flag. When ++ * activating LPLU this function also disables smart speed ++ * and vice versa. LPLU will not be activated unless the ++ * device autonegotiation advertisement meets standards of ++ * either 10 or 10/100 or 10/100/1000 at all duplexes. ++ * This is a function pointer entry point only called by ++ * PHY setup routines. ++ **/ ++static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ u32 phy_ctrl; ++ s32 ret_val = E1000_SUCCESS; ++ u16 data; ++ ++ if (phy->type != e1000_phy_igp_3) ++ goto out; ++ ++ phy_ctrl = er32(PHY_CTRL); ++ ++ if (active) { ++ phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; ++ ew32(PHY_CTRL, phy_ctrl); ++ ++ /* Call gig speed drop workaround on LPLU before accessing ++ * any PHY registers */ ++ if ((hw->mac.type == e1000_ich8lan) && ++ (hw->phy.type == e1000_phy_igp_3)) ++ e1000_gig_downshift_workaround_ich8lan(hw); ++ ++ /* When LPLU is enabled, we should disable SmartSpeed */ ++ ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); ++ data &= ~IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); ++ if (ret_val) ++ goto out; ++ } else { ++ phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; ++ ew32(PHY_CTRL, phy_ctrl); ++ ++ /* LPLU and SmartSpeed are mutually exclusive. LPLU is used ++ * during Dx states where the power conservation is most ++ * important. During driver activity we should enable ++ * SmartSpeed, so performance is maintained. */ ++ if (phy->smart_speed == e1000_smart_speed_on) { ++ ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data |= IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ if (ret_val) ++ goto out; ++ } else if (phy->smart_speed == e1000_smart_speed_off) { ++ ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ if (ret_val) ++ goto out; ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state ++ * @hw: pointer to the HW structure ++ * @active: TRUE to enable LPLU, FALSE to disable ++ * ++ * Sets the LPLU D3 state according to the active flag. When ++ * activating LPLU this function also disables smart speed ++ * and vice versa. LPLU will not be activated unless the ++ * device autonegotiation advertisement meets standards of ++ * either 10 or 10/100 or 10/100/1000 at all duplexes. ++ * This is a function pointer entry point only called by ++ * PHY setup routines. ++ **/ ++static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ u32 phy_ctrl; ++ s32 ret_val = E1000_SUCCESS; ++ u16 data; ++ ++ phy_ctrl = er32(PHY_CTRL); ++ ++ if (!active) { ++ phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; ++ ew32(PHY_CTRL, phy_ctrl); ++ /* LPLU and SmartSpeed are mutually exclusive. LPLU is used ++ * during Dx states where the power conservation is most ++ * important. During driver activity we should enable ++ * SmartSpeed, so performance is maintained. */ ++ if (phy->smart_speed == e1000_smart_speed_on) { ++ ret_val = e1e_rphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data |= IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = e1e_wphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ if (ret_val) ++ goto out; ++ } else if (phy->smart_speed == e1000_smart_speed_off) { ++ ret_val = e1e_rphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = e1e_wphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ if (ret_val) ++ goto out; ++ } ++ } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || ++ (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || ++ (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { ++ phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; ++ ew32(PHY_CTRL, phy_ctrl); ++ ++ /* Call gig speed drop workaround on LPLU before accessing ++ * any PHY registers */ ++ if ((hw->mac.type == e1000_ich8lan) && ++ (hw->phy.type == e1000_phy_igp_3)) ++ e1000_gig_downshift_workaround_ich8lan(hw); ++ ++ /* When LPLU is enabled, we should disable SmartSpeed */ ++ ret_val = e1e_rphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = e1e_wphy(hw, ++ IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_read_nvm_ich8lan - Read word(s) from the NVM ++ * @hw: pointer to the HW structure ++ * @offset: The offset (in bytes) of the word(s) to read. ++ * @words: Size of data to read in words ++ * @data: Pointer to the word(s) to read at offset. ++ * ++ * Reads a word(s) from the NVM using the flash access registers. ++ **/ ++static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, ++ u16 *data) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; ++ u32 act_offset; ++ s32 ret_val = E1000_SUCCESS; ++ u16 i, word; ++ ++ if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || ++ (words == 0)) { ++ hw_dbg(hw, "nvm parameter(s) out of bounds\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++ ret_val = e1000_acquire_swflag_ich8lan(hw); ++ if (ret_val) ++ goto out; ++ ++ /* Start with the bank offset, then add the relative offset. */ ++ act_offset = (er32(EECD) & E1000_EECD_SEC1VAL) ++ ? nvm->flash_bank_size ++ : 0; ++ act_offset += offset; ++ ++ for (i = 0; i < words; i++) { ++ if ((dev_spec->shadow_ram) && ++ (dev_spec->shadow_ram[offset+i].modified)) { ++ data[i] = dev_spec->shadow_ram[offset+i].value; ++ } else { ++ ret_val = e1000_read_flash_word_ich8lan(hw, ++ act_offset + i, ++ &word); ++ if (ret_val) ++ break; ++ data[i] = word; ++ } ++ } ++ ++ e1000_release_swflag_ich8lan(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_flash_cycle_init_ich8lan - Initialize flash ++ * @hw: pointer to the HW structure ++ * ++ * This function does initial flash setup so that a new read/write/erase cycle ++ * can be started. ++ **/ ++static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) ++{ ++ union ich8_hws_flash_status hsfsts; ++ s32 ret_val = -E1000_ERR_NVM; ++ s32 i = 0; ++ ++ hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); ++ ++ /* Check if the flash descriptor is valid */ ++ if (hsfsts.hsf_status.fldesvalid == 0) { ++ hw_dbg(hw, "Flash descriptor invalid. " ++ "SW Sequencing must be used."); ++ goto out; ++ } ++ ++ /* Clear FCERR and DAEL in hw status by writing 1 */ ++ hsfsts.hsf_status.flcerr = 1; ++ hsfsts.hsf_status.dael = 1; ++ ++ ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); ++ ++ /* Either we should have a hardware SPI cycle in progress ++ * bit to check against, in order to start a new cycle or ++ * FDONE bit should be changed in the hardware so that it ++ * is 1 after harware reset, which can then be used as an ++ * indication whether a cycle is in progress or has been ++ * completed. ++ */ ++ ++ if (hsfsts.hsf_status.flcinprog == 0) { ++ /* There is no cycle running at present, ++ * so we can start a cycle */ ++ /* Begin by setting Flash Cycle Done. */ ++ hsfsts.hsf_status.flcdone = 1; ++ ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); ++ ret_val = E1000_SUCCESS; ++ } else { ++ /* otherwise poll for sometime so the current ++ * cycle has a chance to end before giving up. */ ++ for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { ++ hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS); ++ if (hsfsts.hsf_status.flcinprog == 0) { ++ ret_val = E1000_SUCCESS; ++ break; ++ } ++ udelay(1); ++ } ++ if (ret_val == E1000_SUCCESS) { ++ /* Successful in waiting for previous cycle to timeout, ++ * now set the Flash Cycle Done. */ ++ hsfsts.hsf_status.flcdone = 1; ++ ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); ++ } else { ++ hw_dbg(hw, "Flash controller busy, cannot get access"); ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) ++ * @hw: pointer to the HW structure ++ * @timeout: maximum time to wait for completion ++ * ++ * This function starts a flash cycle and waits for its completion. ++ **/ ++static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) ++{ ++ union ich8_hws_flash_ctrl hsflctl; ++ union ich8_hws_flash_status hsfsts; ++ s32 ret_val = -E1000_ERR_NVM; ++ u32 i = 0; ++ ++ /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ ++ hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); ++ hsflctl.hsf_ctrl.flcgo = 1; ++ ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); ++ ++ /* wait till FDONE bit is set to 1 */ ++ do { ++ hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); ++ if (hsfsts.hsf_status.flcdone == 1) ++ break; ++ udelay(1); ++ } while (i++ < timeout); ++ ++ if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) ++ ret_val = E1000_SUCCESS; ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_read_flash_word_ich8lan - Read word from flash ++ * @hw: pointer to the HW structure ++ * @offset: offset to data location ++ * @data: pointer to the location for storing the data ++ * ++ * Reads the flash word at offset into data. Offset is converted ++ * to bytes before read. ++ **/ ++static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, ++ u16 *data) ++{ ++ s32 ret_val; ++ ++ if (!data) { ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++ /* Must convert offset into bytes. */ ++ offset <<= 1; ++ ++ ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_read_flash_data_ich8lan - Read byte or word from NVM ++ * @hw: pointer to the HW structure ++ * @offset: The offset (in bytes) of the byte or word to read. ++ * @size: Size of data to read, 1=byte 2=word ++ * @data: Pointer to the word to store the value read. ++ * ++ * Reads a byte or word from the NVM using the flash access registers. ++ **/ ++static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, ++ u8 size, u16 *data) ++{ ++ union ich8_hws_flash_status hsfsts; ++ union ich8_hws_flash_ctrl hsflctl; ++ u32 flash_linear_addr; ++ u32 flash_data = 0; ++ s32 ret_val = -E1000_ERR_NVM; ++ u8 count = 0; ++ ++ if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) ++ goto out; ++ ++ flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + ++ hw->nvm.flash_base_addr; ++ ++ do { ++ udelay(1); ++ /* Steps */ ++ ret_val = e1000_flash_cycle_init_ich8lan(hw); ++ if (ret_val != E1000_SUCCESS) ++ break; ++ ++ hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); ++ /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ ++ hsflctl.hsf_ctrl.fldbcount = size - 1; ++ hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; ++ ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); ++ ++ ew32flash(ICH_FLASH_FADDR, flash_linear_addr); ++ ++ ret_val = e1000_flash_cycle_ich8lan(hw, ++ ICH_FLASH_READ_COMMAND_TIMEOUT); ++ ++ /* Check if FCERR is set to 1, if set to 1, clear it ++ * and try the whole sequence a few more times, else ++ * read in (shift in) the Flash Data0, the order is ++ * least significant byte first msb to lsb */ ++ if (ret_val == E1000_SUCCESS) { ++ flash_data = er32flash(ICH_FLASH_FDATA0); ++ if (size == 1) { ++ *data = (u8)(flash_data & 0x000000FF); ++ } else if (size == 2) { ++ *data = (u16)(flash_data & 0x0000FFFF); ++ } ++ break; ++ } else { ++ /* If we've gotten here, then things are probably ++ * completely hosed, but if the error condition is ++ * detected, it won't hurt to give it another try... ++ * ICH_FLASH_CYCLE_REPEAT_COUNT times. ++ */ ++ hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); ++ if (hsfsts.hsf_status.flcerr == 1) { ++ /* Repeat for some time before giving up. */ ++ continue; ++ } else if (hsfsts.hsf_status.flcdone == 0) { ++ hw_dbg(hw, "Timeout error - flash cycle " ++ "did not complete."); ++ break; ++ } ++ } ++ } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_write_nvm_ich8lan - Write word(s) to the NVM ++ * @hw: pointer to the HW structure ++ * @offset: The offset (in bytes) of the word(s) to write. ++ * @words: Size of data to write in words ++ * @data: Pointer to the word(s) to write at offset. ++ * ++ * Writes a byte or word to the NVM using the flash access registers. ++ **/ ++static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, ++ u16 *data) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; ++ s32 ret_val = E1000_SUCCESS; ++ u16 i; ++ ++ if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || ++ (words == 0)) { ++ hw_dbg(hw, "nvm parameter(s) out of bounds\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++ ret_val = e1000_acquire_swflag_ich8lan(hw); ++ if (ret_val) ++ goto out; ++ ++ for (i = 0; i < words; i++) { ++ dev_spec->shadow_ram[offset+i].modified = 1; ++ dev_spec->shadow_ram[offset+i].value = data[i]; ++ } ++ ++ e1000_release_swflag_ich8lan(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM ++ * @hw: pointer to the HW structure ++ * ++ * The NVM checksum is updated by calling the generic update_nvm_checksum, ++ * which writes the checksum to the shadow ram. The changes in the shadow ++ * ram are then committed to the EEPROM by processing each bank at a time ++ * checking for the modified bit and writing only the pending changes. ++ * After a succesful commit, the shadow ram is cleared and is ready for ++ * future writes. ++ **/ ++static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; ++ u32 i, act_offset, new_bank_offset, old_bank_offset; ++ s32 ret_val; ++ u16 data; ++ ++ ret_val = e1000_update_nvm_checksum_generic(hw); ++ if (ret_val) ++ goto out; ++ ++ if (nvm->type != e1000_nvm_flash_sw) ++ goto out; ++ ++ ret_val = e1000_acquire_swflag_ich8lan(hw); ++ if (ret_val) ++ goto out; ++ ++ /* We're writing to the opposite bank so if we're on bank 1, ++ * write to bank 0 etc. We also need to erase the segment that ++ * is going to be written */ ++ if (!(er32(EECD) & E1000_EECD_SEC1VAL)) { ++ new_bank_offset = nvm->flash_bank_size; ++ old_bank_offset = 0; ++ e1000_erase_flash_bank_ich8lan(hw, 1); ++ } else { ++ old_bank_offset = nvm->flash_bank_size; ++ new_bank_offset = 0; ++ e1000_erase_flash_bank_ich8lan(hw, 0); ++ } ++ ++ for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { ++ /* Determine whether to write the value stored ++ * in the other NVM bank or a modified value stored ++ * in the shadow RAM */ ++ if (dev_spec->shadow_ram[i].modified) { ++ data = dev_spec->shadow_ram[i].value; ++ } else { ++ e1000_read_flash_word_ich8lan(hw, ++ i + old_bank_offset, ++ &data); ++ } ++ ++ /* If the word is 0x13, then make sure the signature bits ++ * (15:14) are 11b until the commit has completed. ++ * This will allow us to write 10b which indicates the ++ * signature is valid. We want to do this after the write ++ * has completed so that we don't mark the segment valid ++ * while the write is still in progress */ ++ if (i == E1000_ICH_NVM_SIG_WORD) ++ data |= E1000_ICH_NVM_SIG_MASK; ++ ++ /* Convert offset to bytes. */ ++ act_offset = (i + new_bank_offset) << 1; ++ ++ udelay(100); ++ /* Write the bytes to the new bank. */ ++ ret_val = e1000_retry_write_flash_byte_ich8lan(hw, ++ act_offset, ++ (u8)data); ++ if (ret_val) ++ break; ++ ++ udelay(100); ++ ret_val = e1000_retry_write_flash_byte_ich8lan(hw, ++ act_offset + 1, ++ (u8)(data >> 8)); ++ if (ret_val) ++ break; ++ } ++ ++ /* Don't bother writing the segment valid bits if sector ++ * programming failed. */ ++ if (ret_val) { ++ hw_dbg(hw, "Flash commit failed.\n"); ++ e1000_release_swflag_ich8lan(hw); ++ goto out; ++ } ++ ++ /* Finally validate the new segment by setting bit 15:14 ++ * to 10b in word 0x13 , this can be done without an ++ * erase as well since these bits are 11 to start with ++ * and we need to change bit 14 to 0b */ ++ act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; ++ e1000_read_flash_word_ich8lan(hw, act_offset, &data); ++ data &= 0xBFFF; ++ ret_val = e1000_retry_write_flash_byte_ich8lan(hw, ++ act_offset * 2 + 1, ++ (u8)(data >> 8)); ++ if (ret_val) { ++ e1000_release_swflag_ich8lan(hw); ++ goto out; ++ } ++ ++ /* And invalidate the previously valid segment by setting ++ * its signature word (0x13) high_byte to 0b. This can be ++ * done without an erase because flash erase sets all bits ++ * to 1's. We can write 1's to 0's without an erase */ ++ act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; ++ ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); ++ if (ret_val) { ++ e1000_release_swflag_ich8lan(hw); ++ goto out; ++ } ++ ++ /* Great! Everything worked, we can now clear the cached entries. */ ++ for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { ++ dev_spec->shadow_ram[i].modified = 0; ++ dev_spec->shadow_ram[i].value = 0xFFFF; ++ } ++ ++ e1000_release_swflag_ich8lan(hw); ++ ++ /* Reload the EEPROM, or else modifications will not appear ++ * until after the next adapter reset. ++ */ ++ e1000_reload_nvm(hw); ++ msleep(10); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum ++ * @hw: pointer to the HW structure ++ * ++ * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. ++ * If the bit is 0, that the EEPROM had been modified, but the checksum was not ++ * calculated, in which case we need to calculate the checksum and set bit 6. ++ **/ ++static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 data; ++ ++ /* Read 0x19 and check bit 6. If this bit is 0, the checksum ++ * needs to be fixed. This bit is an indication that the NVM ++ * was prepared by OEM software and did not calculate the ++ * checksum...a likely scenario. ++ */ ++ ret_val = e1000_read_nvm(hw, 0x19, 1, &data); ++ if (ret_val) ++ goto out; ++ ++ if ((data & 0x40) == 0) { ++ data |= 0x40; ++ ret_val = e1000_write_nvm(hw, 0x19, 1, &data); ++ if (ret_val) ++ goto out; ++ ret_val = e1000_update_nvm_checksum(hw); ++ if (ret_val) ++ goto out; ++ } ++ ++ ret_val = e1000_validate_nvm_checksum_generic(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_write_flash_data_ich8lan - Writes bytes to the NVM ++ * @hw: pointer to the HW structure ++ * @offset: The offset (in bytes) of the byte/word to read. ++ * @size: Size of data to read, 1=byte 2=word ++ * @data: The byte(s) to write to the NVM. ++ * ++ * Writes one/two bytes to the NVM using the flash access registers. ++ **/ ++static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, ++ u8 size, u16 data) ++{ ++ union ich8_hws_flash_status hsfsts; ++ union ich8_hws_flash_ctrl hsflctl; ++ u32 flash_linear_addr; ++ u32 flash_data = 0; ++ s32 ret_val = -E1000_ERR_NVM; ++ u8 count = 0; ++ ++ if (size < 1 || size > 2 || data > size * 0xff || ++ offset > ICH_FLASH_LINEAR_ADDR_MASK) ++ goto out; ++ ++ flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + ++ hw->nvm.flash_base_addr; ++ ++ do { ++ udelay(1); ++ /* Steps */ ++ ret_val = e1000_flash_cycle_init_ich8lan(hw); ++ if (ret_val != E1000_SUCCESS) ++ break; ++ ++ hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); ++ /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ ++ hsflctl.hsf_ctrl.fldbcount = size -1; ++ hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; ++ ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); ++ ++ ew32flash(ICH_FLASH_FADDR, flash_linear_addr); ++ ++ if (size == 1) ++ flash_data = (u32)data & 0x00FF; ++ else ++ flash_data = (u32)data; ++ ++ ew32flash(ICH_FLASH_FDATA0, flash_data); ++ ++ /* check if FCERR is set to 1 , if set to 1, clear it ++ * and try the whole sequence a few more times else done */ ++ ret_val = e1000_flash_cycle_ich8lan(hw, ++ ICH_FLASH_WRITE_COMMAND_TIMEOUT); ++ if (ret_val == E1000_SUCCESS) { ++ break; ++ } else { ++ /* If we're here, then things are most likely ++ * completely hosed, but if the error condition ++ * is detected, it won't hurt to give it another ++ * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. ++ */ ++ hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); ++ if (hsfsts.hsf_status.flcerr == 1) { ++ /* Repeat for some time before giving up. */ ++ continue; ++ } else if (hsfsts.hsf_status.flcdone == 0) { ++ hw_dbg(hw, "Timeout error - flash cycle " ++ "did not complete."); ++ break; ++ } ++ } ++ } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_write_flash_byte_ich8lan - Write a single byte to NVM ++ * @hw: pointer to the HW structure ++ * @offset: The index of the byte to read. ++ * @data: The byte to write to the NVM. ++ * ++ * Writes a single byte to the NVM using the flash access registers. ++ **/ ++static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, ++ u8 data) ++{ ++ u16 word = (u16)data; ++ ++ return e1000_write_flash_data_ich8lan(hw, offset, 1, word); ++} ++ ++/** ++ * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM ++ * @hw: pointer to the HW structure ++ * @offset: The offset of the byte to write. ++ * @byte: The byte to write to the NVM. ++ * ++ * Writes a single byte to the NVM using the flash access registers. ++ * Goes through a retry algorithm before giving up. ++ **/ ++static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, ++ u32 offset, u8 byte) ++{ ++ s32 ret_val; ++ u16 program_retries; ++ ++ ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); ++ if (ret_val == E1000_SUCCESS) ++ goto out; ++ ++ for (program_retries = 0; program_retries < 100; program_retries++) { ++ hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset); ++ udelay(100); ++ ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); ++ if (ret_val == E1000_SUCCESS) ++ break; ++ } ++ if (program_retries == 100) { ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM ++ * @hw: pointer to the HW structure ++ * @bank: 0 for first bank, 1 for second bank, etc. ++ * ++ * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. ++ * bank N is 4096 * N + flash_reg_addr. ++ **/ ++static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ union ich8_hws_flash_status hsfsts; ++ union ich8_hws_flash_ctrl hsflctl; ++ u32 flash_linear_addr; ++ /* bank size is in 16bit words - adjust to bytes */ ++ u32 flash_bank_size = nvm->flash_bank_size * 2; ++ s32 ret_val = E1000_SUCCESS; ++ s32 count = 0; ++ s32 j, iteration, sector_size; ++ ++ hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); ++ ++ /* Determine HW Sector size: Read BERASE bits of hw flash status ++ * register */ ++ /* 00: The Hw sector is 256 bytes, hence we need to erase 16 ++ * consecutive sectors. The start index for the nth Hw sector ++ * can be calculated as = bank * 4096 + n * 256 ++ * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. ++ * The start index for the nth Hw sector can be calculated ++ * as = bank * 4096 ++ * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 ++ * (ich9 only, otherwise error condition) ++ * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 ++ */ ++ switch (hsfsts.hsf_status.berasesz) { ++ case 0: ++ /* Hw sector size 256 */ ++ sector_size = ICH_FLASH_SEG_SIZE_256; ++ iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; ++ break; ++ case 1: ++ sector_size = ICH_FLASH_SEG_SIZE_4K; ++ iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K; ++ break; ++ case 2: ++ if (hw->mac.type == e1000_ich9lan) { ++ sector_size = ICH_FLASH_SEG_SIZE_8K; ++ iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K; ++ } else { ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ break; ++ case 3: ++ sector_size = ICH_FLASH_SEG_SIZE_64K; ++ iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K; ++ break; ++ default: ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++ /* Start with the base address, then add the sector offset. */ ++ flash_linear_addr = hw->nvm.flash_base_addr; ++ flash_linear_addr += (bank) ? (sector_size * iteration) : 0; ++ ++ for (j = 0; j < iteration ; j++) { ++ do { ++ /* Steps */ ++ ret_val = e1000_flash_cycle_init_ich8lan(hw); ++ if (ret_val) ++ goto out; ++ ++ /* Write a value 11 (block Erase) in Flash ++ * Cycle field in hw flash control */ ++ hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); ++ hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; ++ ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); ++ ++ /* Write the last 24 bits of an index within the ++ * block into Flash Linear address field in Flash ++ * Address. ++ */ ++ flash_linear_addr += (j * sector_size); ++ ew32flash(ICH_FLASH_FADDR, flash_linear_addr); ++ ++ ret_val = e1000_flash_cycle_ich8lan(hw, ++ ICH_FLASH_ERASE_COMMAND_TIMEOUT); ++ if (ret_val == E1000_SUCCESS) { ++ break; ++ } else { ++ /* Check if FCERR is set to 1. If 1, ++ * clear it and try the whole sequence ++ * a few more times else Done */ ++ hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); ++ if (hsfsts.hsf_status.flcerr == 1) { ++ /* repeat for some time before ++ * giving up */ ++ continue; ++ } else if (hsfsts.hsf_status.flcdone == 0) ++ goto out; ++ } ++ } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_valid_led_default_ich8lan - Set the default LED settings ++ * @hw: pointer to the HW structure ++ * @data: Pointer to the LED settings ++ * ++ * Reads the LED default settings from the NVM to data. If the NVM LED ++ * settings is all 0's or F's, set the LED default to a valid LED default ++ * setting. ++ **/ ++static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) ++{ ++ s32 ret_val; ++ ++ ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); ++ if (ret_val) { ++ hw_dbg(hw, "NVM Read Error\n"); ++ goto out; ++ } ++ ++ if (*data == ID_LED_RESERVED_0000 || ++ *data == ID_LED_RESERVED_FFFF) ++ *data = ID_LED_DEFAULT_ICH8LAN; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_bus_info_ich8lan - Get/Set the bus type and width ++ * @hw: pointer to the HW structure ++ * ++ * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability ++ * register, so the the bus width is hard coded. ++ **/ ++static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) ++{ ++ struct e1000_bus_info *bus = &hw->bus; ++ s32 ret_val; ++ ++ ret_val = e1000_get_bus_info_pcie(hw); ++ ++ /* ICH devices are "PCI Express"-ish. They have ++ * a configuration space, but do not contain ++ * PCI Express Capability registers, so bus width ++ * must be hardcoded. ++ */ ++ if (bus->width == e1000_bus_width_unknown) ++ bus->width = e1000_bus_width_pcie_x1; ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_reset_hw_ich8lan - Reset the hardware ++ * @hw: pointer to the HW structure ++ * ++ * Does a full reset of the hardware which includes a reset of the PHY and ++ * MAC. ++ **/ ++static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) ++{ ++ u32 ctrl, icr, kab; ++ s32 ret_val; ++ ++ /* Prevent the PCI-E bus from sticking if there is no TLP connection ++ * on the last TLP read/write transaction when MAC is reset. ++ */ ++ ret_val = e1000_disable_pcie_master(hw); ++ if (ret_val) { ++ hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); ++ } ++ ++ hw_dbg(hw, "Masking off all interrupts\n"); ++ ew32(IMC, 0xffffffff); ++ ++ /* Disable the Transmit and Receive units. Then delay to allow ++ * any pending transactions to complete before we hit the MAC ++ * with the global reset. ++ */ ++ ew32(RCTL, 0); ++ ew32(TCTL, E1000_TCTL_PSP); ++ e1e_flush(); ++ ++ msleep(10); ++ ++ /* Workaround for ICH8 bit corruption issue in FIFO memory */ ++ if (hw->mac.type == e1000_ich8lan) { ++ /* Set Tx and Rx buffer allocation to 8k apiece. */ ++ ew32(PBA, E1000_PBA_8K); ++ /* Set Packet Buffer Size to 16k. */ ++ ew32(PBS, E1000_PBS_16K); ++ } ++ ++ ctrl = er32(CTRL); ++ ++ if (!e1000_check_reset_block(hw)) { ++ /* PHY HW reset requires MAC CORE reset at the same ++ * time to make sure the interface between MAC and the ++ * external PHY is reset. ++ */ ++ ctrl |= E1000_CTRL_PHY_RST; ++ } ++ ret_val = e1000_acquire_swflag_ich8lan(hw); ++ hw_dbg(hw, "Issuing a global reset to ich8lan"); ++ ew32(CTRL, (ctrl | E1000_CTRL_RST)); ++ msleep(20); ++ ++ ret_val = e1000_get_auto_rd_done(hw); ++ if (ret_val) { ++ /* ++ * When auto config read does not complete, do not ++ * return with an error. This can happen in situations ++ * where there is no eeprom and prevents getting link. ++ */ ++ hw_dbg(hw, "Auto Read Done did not complete\n"); ++ } ++ ++ ew32(IMC, 0xffffffff); ++ icr = er32(ICR); ++ ++ kab = er32(KABGTXD); ++ kab |= E1000_KABGTXD_BGSQLBIAS; ++ ew32(KABGTXD, kab); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_init_hw_ich8lan - Initialize the hardware ++ * @hw: pointer to the HW structure ++ * ++ * Prepares the hardware for transmit and receive by doing the following: ++ * - initialize hardware bits ++ * - initialize LED identification ++ * - setup receive address registers ++ * - setup flow control ++ * - setup transmit discriptors ++ * - clear statistics ++ **/ ++static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 ctrl_ext, txdctl, snoop; ++ s32 ret_val; ++ u16 i; ++ ++ e1000_initialize_hw_bits_ich8lan(hw); ++ ++ /* Initialize identification LED */ ++ ret_val = e1000_id_led_init(hw); ++ if (ret_val) { ++ hw_dbg(hw, "Error initializing identification LED\n"); ++ goto out; ++ } ++ ++ /* Setup the receive address. */ ++ e1000_init_rx_addrs(hw, mac->rar_entry_count); ++ ++ /* Zero out the Multicast HASH table */ ++ hw_dbg(hw, "Zeroing the MTA\n"); ++ for (i = 0; i < mac->mta_reg_count; i++) ++ E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); ++ ++ /* Setup link and flow control */ ++ ret_val = e1000_setup_link_ich8lan(hw); ++ ++ /* Set the transmit descriptor write-back policy for both queues */ ++ txdctl = er32(TXDCTL); ++ txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | ++ E1000_TXDCTL_FULL_TX_DESC_WB; ++ txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | ++ E1000_TXDCTL_MAX_TX_DESC_PREFETCH; ++ ew32(TXDCTL, txdctl); ++ txdctl = er32(TXDCTL1); ++ txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | ++ E1000_TXDCTL_FULL_TX_DESC_WB; ++ txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | ++ E1000_TXDCTL_MAX_TX_DESC_PREFETCH; ++ ew32(TXDCTL1, txdctl); ++ ++ /* ICH8 has opposite polarity of no_snoop bits. ++ * By default, we should use snoop behavior. */ ++ if (mac->type == e1000_ich8lan) ++ snoop = PCIE_ICH8_SNOOP_ALL; ++ else ++ snoop = (u32) ~(PCIE_NO_SNOOP_ALL); ++ e1000_set_pcie_no_snoop(hw, snoop); ++ ++ ctrl_ext = er32(CTRL_EXT); ++ ctrl_ext |= E1000_CTRL_EXT_RO_DIS; ++ ew32(CTRL_EXT, ctrl_ext); ++ ++ /* Clear all of the statistics registers (clear on read). It is ++ * important that we do this after we have tried to establish link ++ * because the symbol error count will increment wildly if there ++ * is no link. ++ */ ++ e1000_clear_hw_cntrs_ich8lan(hw); ++ ++out: ++ return ret_val; ++} ++/** ++ * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits ++ * @hw: pointer to the HW structure ++ * ++ * Sets/Clears required hardware bits necessary for correctly setting up the ++ * hardware for transmit and receive. ++ **/ ++static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) ++{ ++ u32 reg; ++ ++ /* Extended Device Control */ ++ reg = er32(CTRL_EXT); ++ reg |= (1 << 22); ++ ew32(CTRL_EXT, reg); ++ ++ /* Transmit Descriptor Control 0 */ ++ reg = er32(TXDCTL); ++ reg |= (1 << 22); ++ ew32(TXDCTL, reg); ++ ++ /* Transmit Descriptor Control 1 */ ++ reg = er32(TXDCTL1); ++ reg |= (1 << 22); ++ ew32(TXDCTL1, reg); ++ ++ /* Transmit Arbitration Control 0 */ ++ reg = er32(TARC0); ++ if (hw->mac.type == e1000_ich8lan) ++ reg |= (1 << 28) | (1 << 29); ++ reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); ++ ew32(TARC0, reg); ++ ++ /* Transmit Arbitration Control 1 */ ++ reg = er32(TARC1); ++ if (er32(TCTL) & E1000_TCTL_MULR) ++ reg &= ~(1 << 28); ++ else ++ reg |= (1 << 28); ++ reg |= (1 << 24) | (1 << 26) | (1 << 30); ++ ew32(TARC1, reg); ++ ++ /* Device Status */ ++ if (hw->mac.type == e1000_ich8lan) { ++ reg = er32(STATUS); ++ reg &= ~(1 << 31); ++ ew32(STATUS, reg); ++ } ++} ++ ++/** ++ * e1000_setup_link_ich8lan - Setup flow control and link settings ++ * @hw: pointer to the HW structure ++ * ++ * Determines which flow control settings to use, then configures flow ++ * control. Calls the appropriate media-specific link configuration ++ * function. Assuming the adapter has a valid link partner, a valid link ++ * should be established. Assumes the hardware has previously been reset ++ * and the transmitter and receiver are not enabled. ++ **/ ++static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (e1000_check_reset_block(hw)) ++ goto out; ++ ++ /* ICH parts do not have a word in the NVM to determine ++ * the default flow control setting, so we explicitly ++ * set it to full. ++ */ ++ if (mac->fc == e1000_fc_default) ++ mac->fc = e1000_fc_full; ++ ++ mac->original_fc = mac->fc; ++ ++ hw_dbg(hw, "After fix-ups FlowControl is now = %x\n", mac->fc); ++ ++ /* Continue to configure the copper link. */ ++ ret_val = e1000_setup_copper_link_ich8lan(hw); ++ if (ret_val) ++ goto out; ++ ++ ew32(FCTTV, mac->fc_pause_time); ++ ++ ret_val = e1000_set_fc_watermarks(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface ++ * @hw: pointer to the HW structure ++ * ++ * Configures the kumeran interface to the PHY to wait the appropriate time ++ * when polling the PHY, then call the generic setup_copper_link to finish ++ * configuring the copper link. ++ **/ ++static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ s32 ret_val; ++ u16 reg_data; ++ ++ ctrl = er32(CTRL); ++ ctrl |= E1000_CTRL_SLU; ++ ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); ++ ew32(CTRL, ctrl); ++ ++ /* Set the mac to wait the maximum time between each iteration ++ * and increase the max iterations when polling the phy; ++ * this fixes erroneous timeouts at 10Mbps. */ ++ ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); ++ if (ret_val) ++ goto out; ++ ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); ++ if (ret_val) ++ goto out; ++ reg_data |= 0x3F; ++ ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); ++ if (ret_val) ++ goto out; ++ ++ if (hw->phy.type == e1000_phy_igp_3) { ++ ret_val = e1000_copper_link_setup_igp(hw); ++ if (ret_val) ++ goto out; ++ } ++ ++ ret_val = e1000_setup_copper_link(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_link_up_info_ich8lan - Get current link speed and duplex ++ * @hw: pointer to the HW structure ++ * @speed: pointer to store current link speed ++ * @duplex: pointer to store the current link duplex ++ * ++ * Calls the generic get_speed_and_duplex to retreive the current link ++ * information and then calls the Kumeran lock loss workaround for links at ++ * gigabit speeds. ++ **/ ++static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, ++ u16 *duplex) ++{ ++ s32 ret_val; ++ ++ ret_val = e1000_get_speed_and_duplex_copper(hw, speed, duplex); ++ if (ret_val) ++ goto out; ++ ++ if ((hw->mac.type == e1000_ich8lan) && ++ (hw->phy.type == e1000_phy_igp_3) && ++ (*speed == SPEED_1000)) { ++ ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround ++ * @hw: pointer to the HW structure ++ * ++ * Work-around for 82566 Kumeran PCS lock loss: ++ * On link status change (i.e. PCI reset, speed change) and link is up and ++ * speed is gigabit- ++ * 0) if workaround is optionally disabled do nothing ++ * 1) wait 1ms for Kumeran link to come up ++ * 2) check Kumeran Diagnostic register PCS lock loss bit ++ * 3) if not set the link is locked (all is good), otherwise... ++ * 4) reset the PHY ++ * 5) repeat up to 10 times ++ * Note: this is only called for IGP3 copper when speed is 1gb. ++ **/ ++static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) ++{ ++ struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; ++ u32 phy_ctrl; ++ s32 ret_val = E1000_SUCCESS; ++ u16 i, data; ++ bool link; ++ ++ if (!dev_spec->kmrn_lock_loss_workaround_enabled) ++ goto out; ++ ++ /* Make sure link is up before proceeding. If not just return. ++ * Attempting this while link is negotiating fouled up link ++ * stability */ ++ ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); ++ if (!link) { ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ ++ for (i = 0; i < 10; i++) { ++ /* read once to clear */ ++ ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); ++ if (ret_val) ++ goto out; ++ /* and again to get new status */ ++ ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); ++ if (ret_val) ++ goto out; ++ ++ /* check for PCS lock */ ++ if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) { ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ ++ /* Issue PHY reset */ ++ e1000_phy_hw_reset(hw); ++ mdelay(5); ++ } ++ /* Disable GigE link negotiation */ ++ phy_ctrl = er32(PHY_CTRL); ++ phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | ++ E1000_PHY_CTRL_NOND0A_GBE_DISABLE); ++ ew32(PHY_CTRL, phy_ctrl); ++ ++ /* Call gig speed drop workaround on Giga disable before accessing ++ * any PHY registers */ ++ e1000_gig_downshift_workaround_ich8lan(hw); ++ ++ /* unable to acquire PCS lock */ ++ ret_val = -E1000_ERR_PHY; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_set_kmrn_lock_loss_workaound_ich8lan - Set Kumeran workaround state ++ * @hw: pointer to the HW structure ++ * @state: boolean value used to set the current Kumaran workaround state ++ * ++ * If ICH8, set the current Kumeran workaround state (enabled - TRUE ++ * /disabled - FALSE). ++ **/ ++void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, ++ bool state) ++{ ++ struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; ++ ++ if (hw->mac.type != e1000_ich8lan) { ++ hw_dbg(hw, "Workaround applies to ICH8 only.\n"); ++ goto out; ++ } ++ ++ dev_spec->kmrn_lock_loss_workaround_enabled = state; ++ ++out: ++ return; ++} ++ ++/** ++ * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 ++ * @hw: pointer to the HW structure ++ * ++ * Workaround for 82566 power-down on D3 entry: ++ * 1) disable gigabit link ++ * 2) write VR power-down enable ++ * 3) read it back ++ * Continue if successful, else issue LCD reset and repeat ++ **/ ++void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) ++{ ++ u32 reg; ++ u16 data; ++ u8 retry = 0; ++ ++ if (hw->phy.type != e1000_phy_igp_3) ++ goto out; ++ ++ /* Try the workaround twice (if needed) */ ++ do { ++ /* Disable link */ ++ reg = er32(PHY_CTRL); ++ reg |= (E1000_PHY_CTRL_GBE_DISABLE | ++ E1000_PHY_CTRL_NOND0A_GBE_DISABLE); ++ ew32(PHY_CTRL, reg); ++ ++ /* Call gig speed drop workaround on Giga disable before ++ * accessing any PHY registers */ ++ if (hw->mac.type == e1000_ich8lan) ++ e1000_gig_downshift_workaround_ich8lan(hw); ++ ++ /* Write VR power-down enable */ ++ e1e_rphy(hw, IGP3_VR_CTRL, &data); ++ data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; ++ e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); ++ ++ /* Read it back and test */ ++ e1e_rphy(hw, IGP3_VR_CTRL, &data); ++ data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; ++ if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) ++ break; ++ ++ /* Issue PHY reset and repeat at most one more time */ ++ reg = er32(CTRL); ++ ew32(CTRL, reg | E1000_CTRL_PHY_RST); ++ retry++; ++ } while (retry); ++ ++out: ++ return; ++} ++ ++/** ++ * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working ++ * @hw: pointer to the HW structure ++ * ++ * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), ++ * LPLU, Giga disable, MDIC PHY reset): ++ * 1) Set Kumeran Near-end loopback ++ * 2) Clear Kumeran Near-end loopback ++ * Should only be called for ICH8[m] devices with IGP_3 Phy. ++ **/ ++void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 reg_data; ++ ++ if ((hw->mac.type != e1000_ich8lan) || ++ (hw->phy.type != e1000_phy_igp_3)) ++ goto out; ++ ++ ret_val = e1000_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, ++ ®_data); ++ if (ret_val) ++ goto out; ++ reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; ++ ret_val = e1000_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, ++ reg_data); ++ if (ret_val) ++ goto out; ++ reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; ++ ret_val = e1000_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, ++ reg_data); ++out: ++ return; ++} ++ ++/** ++ * e1000_cleanup_led_ich8lan - Restore the default LED operation ++ * @hw: pointer to the HW structure ++ * ++ * Return the LED back to the default configuration. ++ **/ ++static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (hw->phy.type == e1000_phy_ife) ++ ret_val = e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); ++ else ++ ew32(LEDCTL, hw->mac.ledctl_default); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_led_on_ich8lan - Turn LED's on ++ * @hw: pointer to the HW structure ++ * ++ * Turn on the LED's. ++ **/ ++static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (hw->phy.type == e1000_phy_ife) ++ ret_val = e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, ++ (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); ++ else ++ ew32(LEDCTL, hw->mac.ledctl_mode2); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_led_off_ich8lan - Turn LED's off ++ * @hw: pointer to the HW structure ++ * ++ * Turn off the LED's. ++ **/ ++static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (hw->phy.type == e1000_phy_ife) ++ ret_val = e1e_wphy(hw, ++ IFE_PHY_SPECIAL_CONTROL_LED, ++ (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); ++ else ++ ew32(LEDCTL, hw->mac.ledctl_mode1); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters ++ * @hw: pointer to the HW structure ++ * ++ * Clears hardware counters specific to the silicon family and calls ++ * clear_hw_cntrs_generic to clear all general purpose counters. ++ **/ ++static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) ++{ ++ u32 temp; ++ ++ e1000_clear_hw_cntrs_base(hw); ++ ++ temp = er32(ALGNERRC); ++ temp = er32(RXERRC); ++ temp = er32(TNCRS); ++ temp = er32(CEXTERR); ++ temp = er32(TSCTC); ++ temp = er32(TSCTFC); ++ ++ temp = er32(MGTPRC); ++ temp = er32(MGTPDC); ++ temp = er32(MGTPTC); ++ ++ temp = er32(IAC); ++ temp = er32(ICRXOC); ++ ++} ++ ++static struct e1000_mac_operations ich8_mac_ops = { ++ .mng_mode_enab = E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT, ++ .check_for_link = e1000_check_for_copper_link, ++ .cleanup_led = e1000_cleanup_led_ich8lan, ++ .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, ++ .get_bus_info = e1000_get_bus_info_ich8lan, ++ .get_link_up_info = e1000_get_link_up_info_ich8lan, ++ .led_on = e1000_led_on_ich8lan, ++ .led_off = e1000_led_off_ich8lan, ++ .mc_addr_list_update = e1000_mc_addr_list_update_generic, ++ .reset_hw = e1000_reset_hw_ich8lan, ++ .init_hw = e1000_init_hw_ich8lan, ++ .setup_link = e1000_setup_link_ich8lan, ++ .setup_physical_interface= e1000_setup_copper_link_ich8lan, ++}; ++ ++static struct e1000_phy_operations ich8_phy_ops = { ++ .acquire_phy = e1000_acquire_swflag_ich8lan, ++ .check_reset_block = e1000_check_reset_block_ich8lan, ++ .commit_phy = NULL, ++ .force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan, ++ .get_cfg_done = e1000_get_cfg_done, ++ .get_cable_length = e1000_get_cable_length_igp_2, ++ .get_phy_info = e1000_get_phy_info_ich8lan, ++ .read_phy_reg = e1000_read_phy_reg_igp, ++ .release_phy = e1000_release_swflag_ich8lan, ++ .reset_phy = e1000_phy_hw_reset_ich8lan, ++ .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, ++ .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, ++ .write_phy_reg = e1000_write_phy_reg_igp, ++}; ++ ++static struct e1000_nvm_operations ich8_nvm_ops = { ++ .acquire_nvm = e1000_acquire_swflag_ich8lan, ++ .read_nvm = e1000_read_nvm_ich8lan, ++ .release_nvm = e1000_release_swflag_ich8lan, ++ .update_nvm = e1000_update_nvm_checksum_ich8lan, ++ .valid_led_default = e1000_valid_led_default_ich8lan, ++ .validate_nvm = e1000_validate_nvm_checksum_ich8lan, ++ .write_nvm = e1000_write_nvm_ich8lan, ++}; ++ ++struct e1000_info e1000_ich8_info = { ++ .mac = e1000_ich8lan, ++ .flags = FLAG_HAS_WOL ++ | FLAG_RX_CSUM_ENABLED ++ | FLAG_HAS_CTRLEXT_ON_LOAD ++ | FLAG_HAS_AMT ++ | FLAG_HAS_FLASH ++ | FLAG_APME_IN_WUC, ++ .pba = 8, ++ .get_invariants = e1000_get_invariants_ich8lan, ++ .mac_ops = &ich8_mac_ops, ++ .phy_ops = &ich8_phy_ops, ++ .nvm_ops = &ich8_nvm_ops, ++}; ++ ++struct e1000_info e1000_ich9_info = { ++ .mac = e1000_ich9lan, ++ .flags = FLAG_HAS_JUMBO_FRAMES ++ | FLAG_HAS_WOL ++ | FLAG_RX_CSUM_ENABLED ++ | FLAG_HAS_CTRLEXT_ON_LOAD ++ | FLAG_HAS_AMT ++ | FLAG_HAS_ERT ++ | FLAG_HAS_FLASH ++ | FLAG_APME_IN_WUC, ++ .pba = 10, ++ .get_invariants = e1000_get_invariants_ich8lan, ++ .mac_ops = &ich8_mac_ops, ++ .phy_ops = &ich8_phy_ops, ++ .nvm_ops = &ich8_nvm_ops, ++}; ++ +diff --git a/drivers/net/e1000e/lib.c b/drivers/net/e1000e/lib.c +new file mode 100644 +index 0000000..21c16e0 +--- /dev/null ++++ b/drivers/net/e1000e/lib.c +@@ -0,0 +1,2528 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2007 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS <linux.nics@intel.com> ++ e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#include <linux/netdevice.h> ++#include <linux/pci.h> ++ ++#include "e1000.h" ++ ++enum e1000_mng_mode { ++ e1000_mng_mode_none = 0, ++ e1000_mng_mode_asf, ++ e1000_mng_mode_pt, ++ e1000_mng_mode_ipmi, ++ e1000_mng_mode_host_if_only ++}; ++ ++#define E1000_FACTPS_MNGCG 0x20000000 ++ ++#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management ++ * Technology signature */ ++ ++/** ++ * e1000_get_bus_info_pcie - Get PCIe bus information ++ * @hw: pointer to the HW structure ++ * ++ * Determines and stores the system bus information for a particular ++ * network interface. The following bus information is determined and stored: ++ * bus speed, bus width, type (PCIe), and PCIe function. ++ **/ ++s32 e1000_get_bus_info_pcie(struct e1000_hw *hw) ++{ ++ struct e1000_bus_info *bus = &hw->bus; ++ struct e1000_adapter *adapter = hw->adapter; ++ u32 status; ++ u16 pcie_link_status, pci_header_type, cap_offset; ++ ++ cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); ++ if (!cap_offset) { ++ bus->width = e1000_bus_width_unknown; ++ } else { ++ pci_read_config_word(adapter->pdev, ++ cap_offset + PCIE_LINK_STATUS, ++ &pcie_link_status); ++ bus->width = (enum e1000_bus_width)((pcie_link_status & ++ PCIE_LINK_WIDTH_MASK) >> ++ PCIE_LINK_WIDTH_SHIFT); ++ } ++ ++ pci_read_config_word(adapter->pdev, PCI_HEADER_TYPE_REGISTER, ++ &pci_header_type); ++ if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { ++ status = er32(STATUS); ++ bus->func = (status & E1000_STATUS_FUNC_MASK) ++ >> E1000_STATUS_FUNC_SHIFT; ++ } else { ++ bus->func = 0; ++ } ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_write_vfta - Write value to VLAN filter table ++ * @hw: pointer to the HW structure ++ * @offset: register offset in VLAN filter table ++ * @value: register value written to VLAN filter table ++ * ++ * Writes value at the given offset in the register array which stores ++ * the VLAN filter table. ++ **/ ++void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) ++{ ++ E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); ++ e1e_flush(); ++} ++ ++/** ++ * e1000_init_rx_addrs - Initialize receive address's ++ * @hw: pointer to the HW structure ++ * @rar_count: receive address registers ++ * ++ * Setups the receive address registers by setting the base receive address ++ * register to the devices MAC address and clearing all the other receive ++ * address registers to 0. ++ **/ ++void e1000_init_rx_addrs(struct e1000_hw *hw, u16 rar_count) ++{ ++ u32 i; ++ ++ /* Setup the receive address */ ++ hw_dbg(hw, "Programming MAC Address into RAR[0]\n"); ++ ++ e1000_rar_set(hw, hw->mac.addr, 0); ++ ++ /* Zero out the other (rar_entry_count - 1) receive addresses */ ++ hw_dbg(hw, "Clearing RAR[1-%u]\n", rar_count-1); ++ for (i = 1; i < rar_count; i++) { ++ E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0); ++ e1e_flush(); ++ E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0); ++ e1e_flush(); ++ } ++} ++ ++/** ++ * e1000_rar_set - Set receive address register ++ * @hw: pointer to the HW structure ++ * @addr: pointer to the receive address ++ * @index: receive address array register ++ * ++ * Sets the receive address array register at index to the address passed ++ * in by addr. ++ **/ ++void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) ++{ ++ u32 rar_low, rar_high; ++ ++ /* HW expects these in little endian so we reverse the byte order ++ * from network order (big endian) to little endian ++ */ ++ rar_low = ((u32) addr[0] | ++ ((u32) addr[1] << 8) | ++ ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); ++ ++ rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); ++ ++ rar_high |= E1000_RAH_AV; ++ ++ E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low); ++ E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high); ++} ++ ++/** ++ * e1000_mta_set - Set multicast filter table address ++ * @hw: pointer to the HW structure ++ * @hash_value: determines the MTA register and bit to set ++ * ++ * The multicast table address is a register array of 32-bit registers. ++ * The hash_value is used to determine what register the bit is in, the ++ * current value is read, the new bit is OR'd in and the new value is ++ * written back into the register. ++ **/ ++static void e1000_mta_set(struct e1000_hw *hw, u32 hash_value) ++{ ++ u32 hash_bit, hash_reg, mta; ++ ++ /* The MTA is a register array of 32-bit registers. It is ++ * treated like an array of (32*mta_reg_count) bits. We want to ++ * set bit BitArray[hash_value]. So we figure out what register ++ * the bit is in, read it, OR in the new bit, then write ++ * back the new value. The (hw->mac.mta_reg_count - 1) serves as a ++ * mask to bits 31:5 of the hash value which gives us the ++ * register we're modifying. The hash bit within that register ++ * is determined by the lower 5 bits of the hash value. ++ */ ++ hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); ++ hash_bit = hash_value & 0x1F; ++ ++ mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); ++ ++ mta |= (1 << hash_bit); ++ ++ E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); ++ e1e_flush(); ++} ++ ++/** ++ * e1000_hash_mc_addr - Generate a multicast hash value ++ * @hw: pointer to the HW structure ++ * @mc_addr: pointer to a multicast address ++ * ++ * Generates a multicast address hash value which is used to determine ++ * the multicast filter table array address and new table value. See ++ * e1000_mta_set_generic() ++ **/ ++static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) ++{ ++ u32 hash_value, hash_mask; ++ u8 bit_shift = 0; ++ ++ /* Register count multiplied by bits per register */ ++ hash_mask = (hw->mac.mta_reg_count * 32) - 1; ++ ++ /* For a mc_filter_type of 0, bit_shift is the number of left-shifts ++ * where 0xFF would still fall within the hash mask. */ ++ while (hash_mask >> bit_shift != 0xFF) ++ bit_shift++; ++ ++ /* The portion of the address that is used for the hash table ++ * is determined by the mc_filter_type setting. ++ * The algorithm is such that there is a total of 8 bits of shifting. ++ * The bit_shift for a mc_filter_type of 0 represents the number of ++ * left-shifts where the MSB of mc_addr[5] would still fall within ++ * the hash_mask. Case 0 does this exactly. Since there are a total ++ * of 8 bits of shifting, then mc_addr[4] will shift right the ++ * remaining number of bits. Thus 8 - bit_shift. The rest of the ++ * cases are a variation of this algorithm...essentially raising the ++ * number of bits to shift mc_addr[5] left, while still keeping the ++ * 8-bit shifting total. ++ */ ++ /* For example, given the following Destination MAC Address and an ++ * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), ++ * we can see that the bit_shift for case 0 is 4. These are the hash ++ * values resulting from each mc_filter_type... ++ * [0] [1] [2] [3] [4] [5] ++ * 01 AA 00 12 34 56 ++ * LSB MSB ++ * ++ * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 ++ * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 ++ * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 ++ * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 ++ */ ++ switch (hw->mac.mc_filter_type) { ++ default: ++ case 0: ++ break; ++ case 1: ++ bit_shift += 1; ++ break; ++ case 2: ++ bit_shift += 2; ++ break; ++ case 3: ++ bit_shift += 4; ++ break; ++ } ++ ++ hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | ++ (((u16) mc_addr[5]) << bit_shift))); ++ ++ return hash_value; ++} ++ ++/** ++ * e1000_mc_addr_list_update_generic - Update Multicast addresses ++ * @hw: pointer to the HW structure ++ * @mc_addr_list: array of multicast addresses to program ++ * @mc_addr_count: number of multicast addresses to program ++ * @rar_used_count: the first RAR register free to program ++ * @rar_count: total number of supported Receive Address Registers ++ * ++ * Updates the Receive Address Registers and Multicast Table Array. ++ * The caller must have a packed mc_addr_list of multicast addresses. ++ * The parameter rar_count will usually be hw->mac.rar_entry_count ++ * unless there are workarounds that change this. ++ **/ ++void e1000_mc_addr_list_update_generic(struct e1000_hw *hw, ++ u8 *mc_addr_list, u32 mc_addr_count, ++ u32 rar_used_count, u32 rar_count) ++{ ++ u32 hash_value; ++ u32 i; ++ ++ /* Load the first set of multicast addresses into the exact ++ * filters (RAR). If there are not enough to fill the RAR ++ * array, clear the filters. ++ */ ++ for (i = rar_used_count; i < rar_count; i++) { ++ if (mc_addr_count) { ++ e1000_rar_set(hw, mc_addr_list, i); ++ mc_addr_count--; ++ mc_addr_list += ETH_ALEN; ++ } else { ++ E1000_WRITE_REG_ARRAY(hw, E1000_RA, i << 1, 0); ++ e1e_flush(); ++ E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1) + 1, 0); ++ e1e_flush(); ++ } ++ } ++ ++ /* Clear the old settings from the MTA */ ++ hw_dbg(hw, "Clearing MTA\n"); ++ for (i = 0; i < hw->mac.mta_reg_count; i++) { ++ E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); ++ e1e_flush(); ++ } ++ ++ /* Load any remaining multicast addresses into the hash table. */ ++ for (; mc_addr_count > 0; mc_addr_count--) { ++ hash_value = e1000_hash_mc_addr(hw, mc_addr_list); ++ hw_dbg(hw, "Hash value = 0x%03X\n", hash_value); ++ e1000_mta_set(hw, hash_value); ++ mc_addr_list += ETH_ALEN; ++ } ++} ++ ++/** ++ * e1000_clear_hw_cntrs_base - Clear base hardware counters ++ * @hw: pointer to the HW structure ++ * ++ * Clears the base hardware counters by reading the counter registers. ++ **/ ++void e1000_clear_hw_cntrs_base(struct e1000_hw *hw) ++{ ++ u32 temp; ++ ++ temp = er32(CRCERRS); ++ temp = er32(SYMERRS); ++ temp = er32(MPC); ++ temp = er32(SCC); ++ temp = er32(ECOL); ++ temp = er32(MCC); ++ temp = er32(LATECOL); ++ temp = er32(COLC); ++ temp = er32(DC); ++ temp = er32(SEC); ++ temp = er32(RLEC); ++ temp = er32(XONRXC); ++ temp = er32(XONTXC); ++ temp = er32(XOFFRXC); ++ temp = er32(XOFFTXC); ++ temp = er32(FCRUC); ++ temp = er32(GPRC); ++ temp = er32(BPRC); ++ temp = er32(MPRC); ++ temp = er32(GPTC); ++ temp = er32(GORCL); ++ temp = er32(GORCH); ++ temp = er32(GOTCL); ++ temp = er32(GOTCH); ++ temp = er32(RNBC); ++ temp = er32(RUC); ++ temp = er32(RFC); ++ temp = er32(ROC); ++ temp = er32(RJC); ++ temp = er32(TORL); ++ temp = er32(TORH); ++ temp = er32(TOTL); ++ temp = er32(TOTH); ++ temp = er32(TPR); ++ temp = er32(TPT); ++ temp = er32(MPTC); ++ temp = er32(BPTC); ++} ++ ++/** ++ * e1000_check_for_copper_link - Check for link (Copper) ++ * @hw: pointer to the HW structure ++ * ++ * Checks to see of the link status of the hardware has changed. If a ++ * change in link status has been detected, then we read the PHY registers ++ * to get the current speed/duplex if link exists. ++ **/ ++s32 e1000_check_for_copper_link(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ s32 ret_val; ++ bool link; ++ ++ /* We only want to go out to the PHY registers to see if Auto-Neg ++ * has completed and/or if our link status has changed. The ++ * get_link_status flag is set upon receiving a Link Status ++ * Change or Rx Sequence Error interrupt. ++ */ ++ if (!mac->get_link_status) { ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ ++ /* First we want to see if the MII Status Register reports ++ * link. If so, then we want to get the current speed/duplex ++ * of the PHY. ++ */ ++ ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) ++ goto out; /* No link detected */ ++ ++ mac->get_link_status = 0; ++ ++ /* Check if there was DownShift, must be checked ++ * immediately after link-up */ ++ e1000_check_downshift(hw); ++ ++ /* If we are forcing speed/duplex, then we simply return since ++ * we have already determined whether we have link or not. ++ */ ++ if (!mac->autoneg) { ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ /* Auto-Neg is enabled. Auto Speed Detection takes care ++ * of MAC speed/duplex configuration. So we only need to ++ * configure Collision Distance in the MAC. ++ */ ++ e1000_config_collision_dist(hw); ++ ++ /* Configure Flow Control now that Auto-Neg has completed. ++ * First, we need to restore the desired flow control ++ * settings because we may have had to re-autoneg with a ++ * different link partner. ++ */ ++ ret_val = e1000_config_fc_after_link_up(hw); ++ if (ret_val) { ++ hw_dbg(hw, "Error configuring flow control\n"); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_check_for_fiber_link - Check for link (Fiber) ++ * @hw: pointer to the HW structure ++ * ++ * Checks for link up on the hardware. If link is not up and we have ++ * a signal, then we need to force link up. ++ **/ ++s32 e1000_check_for_fiber_link(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 rxcw; ++ u32 ctrl; ++ u32 status; ++ s32 ret_val = E1000_SUCCESS; ++ ++ ctrl = er32(CTRL); ++ status = er32(STATUS); ++ rxcw = er32(RXCW); ++ ++ /* If we don't have link (auto-negotiation failed or link partner ++ * cannot auto-negotiate), the cable is plugged in (we have signal), ++ * and our link partner is not trying to auto-negotiate with us (we ++ * are receiving idles or data), we need to force link up. We also ++ * need to give auto-negotiation time to complete, in case the cable ++ * was just plugged in. The autoneg_failed flag does this. ++ */ ++ /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ ++ if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && ++ (!(rxcw & E1000_RXCW_C))) { ++ if (mac->autoneg_failed == 0) { ++ mac->autoneg_failed = 1; ++ goto out; ++ } ++ hw_dbg(hw, "NOT RXing /C/, disable AutoNeg and force link.\n"); ++ ++ /* Disable auto-negotiation in the TXCW register */ ++ ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); ++ ++ /* Force link-up and also force full-duplex. */ ++ ctrl = er32(CTRL); ++ ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); ++ ew32(CTRL, ctrl); ++ ++ /* Configure Flow Control after forcing link up. */ ++ ret_val = e1000_config_fc_after_link_up(hw); ++ if (ret_val) { ++ hw_dbg(hw, "Error configuring flow control\n"); ++ goto out; ++ } ++ } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { ++ /* If we are forcing link and we are receiving /C/ ordered ++ * sets, re-enable auto-negotiation in the TXCW register ++ * and disable forced link in the Device Control register ++ * in an attempt to auto-negotiate with our link partner. ++ */ ++ hw_dbg(hw, "RXing /C/, enable AutoNeg and stop forcing link.\n"); ++ ew32(TXCW, mac->txcw); ++ ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); ++ ++ mac->serdes_has_link = 1; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_check_for_serdes_link - Check for link (Serdes) ++ * @hw: pointer to the HW structure ++ * ++ * Checks for link up on the hardware. If link is not up and we have ++ * a signal, then we need to force link up. ++ **/ ++s32 e1000_check_for_serdes_link(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 rxcw; ++ u32 ctrl; ++ u32 status; ++ s32 ret_val = E1000_SUCCESS; ++ ++ ctrl = er32(CTRL); ++ status = er32(STATUS); ++ rxcw = er32(RXCW); ++ ++ /* If we don't have link (auto-negotiation failed or link partner ++ * cannot auto-negotiate), and our link partner is not trying to ++ * auto-negotiate with us (we are receiving idles or data), ++ * we need to force link up. We also need to give auto-negotiation ++ * time to complete. ++ */ ++ /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ ++ if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { ++ if (mac->autoneg_failed == 0) { ++ mac->autoneg_failed = 1; ++ goto out; ++ } ++ hw_dbg(hw, "NOT RXing /C/, disable AutoNeg and force link.\n"); ++ ++ /* Disable auto-negotiation in the TXCW register */ ++ ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); ++ ++ /* Force link-up and also force full-duplex. */ ++ ctrl = er32(CTRL); ++ ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); ++ ew32(CTRL, ctrl); ++ ++ /* Configure Flow Control after forcing link up. */ ++ ret_val = e1000_config_fc_after_link_up(hw); ++ if (ret_val) { ++ hw_dbg(hw, "Error configuring flow control\n"); ++ goto out; ++ } ++ } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { ++ /* If we are forcing link and we are receiving /C/ ordered ++ * sets, re-enable auto-negotiation in the TXCW register ++ * and disable forced link in the Device Control register ++ * in an attempt to auto-negotiate with our link partner. ++ */ ++ hw_dbg(hw, "RXing /C/, enable AutoNeg and stop forcing link.\n"); ++ ew32(TXCW, mac->txcw); ++ ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); ++ ++ mac->serdes_has_link = 1; ++ } else if (!(E1000_TXCW_ANE & er32(TXCW))) { ++ /* If we force link for non-auto-negotiation switch, check ++ * link status based on MAC synchronization for internal ++ * serdes media type. ++ */ ++ /* SYNCH bit and IV bit are sticky. */ ++ udelay(10); ++ if (E1000_RXCW_SYNCH & er32(RXCW)) { ++ if (!(rxcw & E1000_RXCW_IV)) { ++ mac->serdes_has_link = 1; ++ hw_dbg(hw, "SERDES: Link is up.\n"); ++ } ++ } else { ++ mac->serdes_has_link = 0; ++ hw_dbg(hw, "SERDES: Link is down.\n"); ++ } ++ } ++ ++ if (E1000_TXCW_ANE & er32(TXCW)) { ++ status = er32(STATUS); ++ mac->serdes_has_link = (status & E1000_STATUS_LU); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_set_default_fc_generic - Set flow control default values ++ * @hw: pointer to the HW structure ++ * ++ * Read the EEPROM for the default values for flow control and store the ++ * values. ++ **/ ++static s32 e1000_set_default_fc_generic(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ s32 ret_val = E1000_SUCCESS; ++ u16 nvm_data; ++ ++ if (mac->fc != e1000_fc_default) ++ goto out; ++ ++ /* Read and store word 0x0F of the EEPROM. This word contains bits ++ * that determine the hardware's default PAUSE (flow control) mode, ++ * a bit that determines whether the HW defaults to enabling or ++ * disabling auto-negotiation, and the direction of the ++ * SW defined pins. If there is no SW over-ride of the flow ++ * control setting, then the variable hw->fc will ++ * be initialized based on a value in the EEPROM. ++ */ ++ ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); ++ ++ if (ret_val) { ++ hw_dbg(hw, "NVM Read Error\n"); ++ goto out; ++ } ++ ++ if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) ++ mac->fc = e1000_fc_none; ++ else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == ++ NVM_WORD0F_ASM_DIR) ++ mac->fc = e1000_fc_tx_pause; ++ else ++ mac->fc = e1000_fc_full; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_setup_link - Setup flow control and link settings ++ * @hw: pointer to the HW structure ++ * ++ * Determines which flow control settings to use, then configures flow ++ * control. Calls the appropriate media-specific link configuration ++ * function. Assuming the adapter has a valid link partner, a valid link ++ * should be established. Assumes the hardware has previously been reset ++ * and the transmitter and receiver are not enabled. ++ **/ ++s32 e1000_setup_link(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ s32 ret_val = E1000_SUCCESS; ++ ++ /* In the case of the phy reset being blocked, we already have a link. ++ * We do not need to set it up again. ++ */ ++ if (e1000_check_reset_block(hw)) ++ goto out; ++ ++ ret_val = e1000_set_default_fc_generic(hw); ++ if (ret_val) ++ goto out; ++ ++ /* We want to save off the original Flow Control configuration just ++ * in case we get disconnected and then reconnected into a different ++ * hub or switch with different Flow Control capabilities. ++ */ ++ mac->original_fc = mac->fc; ++ ++ hw_dbg(hw, "After fix-ups FlowControl is now = %x\n", mac->fc); ++ ++ /* Call the necessary media_type subroutine to configure the link. */ ++ ret_val = mac->ops.setup_physical_interface(hw); ++ if (ret_val) ++ goto out; ++ ++ /* Initialize the flow control address, type, and PAUSE timer ++ * registers to their default values. This is done even if flow ++ * control is disabled, because it does not hurt anything to ++ * initialize these registers. ++ */ ++ hw_dbg(hw, "Initializing the Flow Control address, type and timer regs\n"); ++ ew32(FCT, FLOW_CONTROL_TYPE); ++ ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); ++ ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); ++ ++ ew32(FCTTV, mac->fc_pause_time); ++ ++ ret_val = e1000_set_fc_watermarks(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_commit_fc_settings_generic - Configure flow control ++ * @hw: pointer to the HW structure ++ * ++ * Write the flow control settings to the Transmit Config Word Register (TXCW) ++ * base on the flow control settings in e1000_mac_info. ++ **/ ++static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 txcw; ++ s32 ret_val = E1000_SUCCESS; ++ ++ /* Check for a software override of the flow control settings, and ++ * setup the device accordingly. If auto-negotiation is enabled, then ++ * software will have to set the "PAUSE" bits to the correct value in ++ * the Transmit Config Word Register (TXCW) and re-start auto- ++ * negotiation. However, if auto-negotiation is disabled, then ++ * software will have to manually configure the two flow control enable ++ * bits in the CTRL register. ++ * ++ * The possible values of the "fc" parameter are: ++ * 0: Flow control is completely disabled ++ * 1: Rx flow control is enabled (we can receive pause frames, ++ * but not send pause frames). ++ * 2: Tx flow control is enabled (we can send pause frames but we ++ * do not support receiving pause frames). ++ * 3: Both Rx and TX flow control (symmetric) are enabled. ++ */ ++ switch (mac->fc) { ++ case e1000_fc_none: ++ /* Flow control completely disabled by a software over-ride. */ ++ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); ++ break; ++ case e1000_fc_rx_pause: ++ /* RX Flow control is enabled and TX Flow control is disabled ++ * by a software over-ride. Since there really isn't a way to ++ * advertise that we are capable of RX Pause ONLY, we will ++ * advertise that we support both symmetric and asymmetric RX ++ * PAUSE. Later, we will disable the adapter's ability to send ++ * PAUSE frames. ++ */ ++ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); ++ break; ++ case e1000_fc_tx_pause: ++ /* TX Flow control is enabled, and RX Flow control is disabled, ++ * by a software over-ride. ++ */ ++ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); ++ break; ++ case e1000_fc_full: ++ /* Flow control (both RX and TX) is enabled by a software ++ * over-ride. ++ */ ++ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); ++ break; ++ default: ++ hw_dbg(hw, "Flow control param set incorrectly\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ break; ++ } ++ ++ ew32(TXCW, txcw); ++ mac->txcw = txcw; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_poll_fiber_serdes_link_generic - Poll for link up ++ * @hw: pointer to the HW structure ++ * ++ * Polls for link up by reading the status register, if link fails to come ++ * up with auto-negotiation, then the link is forced if a signal is detected. ++ **/ ++static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 i, status; ++ s32 ret_val = E1000_SUCCESS; ++ ++ /* If we have a signal (the cable is plugged in, or assumed true for ++ * serdes media) then poll for a "Link-Up" indication in the Device ++ * Status Register. Time-out if a link isn't seen in 500 milliseconds ++ * seconds (Auto-negotiation should complete in less than 500 ++ * milliseconds even if the other end is doing it in SW). ++ */ ++ for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { ++ msleep(10); ++ status = er32(STATUS); ++ if (status & E1000_STATUS_LU) ++ break; ++ } ++ if (i == FIBER_LINK_UP_LIMIT) { ++ hw_dbg(hw, "Never got a valid link from auto-neg!!!\n"); ++ mac->autoneg_failed = 1; ++ /* AutoNeg failed to achieve a link, so we'll call ++ * mac->check_for_link. This routine will force the ++ * link up if we detect a signal. This will allow us to ++ * communicate with non-autonegotiating link partners. ++ */ ++ ret_val = mac->ops.check_for_link(hw); ++ if (ret_val) { ++ hw_dbg(hw, "Error while checking for link\n"); ++ goto out; ++ } ++ mac->autoneg_failed = 0; ++ } else { ++ mac->autoneg_failed = 0; ++ hw_dbg(hw, "Valid Link Found\n"); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_setup_fiber_serdes_link - Setup link for fiber/serdes ++ * @hw: pointer to the HW structure ++ * ++ * Configures collision distance and flow control for fiber and serdes ++ * links. Upon successful setup, poll for link. ++ **/ ++s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ s32 ret_val = E1000_SUCCESS; ++ ++ ctrl = er32(CTRL); ++ ++ /* Take the link out of reset */ ++ ctrl &= ~E1000_CTRL_LRST; ++ ++ e1000_config_collision_dist(hw); ++ ++ ret_val = e1000_commit_fc_settings_generic(hw); ++ if (ret_val) ++ goto out; ++ ++ /* Since auto-negotiation is enabled, take the link out of reset (the ++ * link will be in reset, because we previously reset the chip). This ++ * will restart auto-negotiation. If auto-negotiation is successful ++ * then the link-up status bit will be set and the flow control enable ++ * bits (RFCE and TFCE) will be set according to their negotiated value. ++ */ ++ hw_dbg(hw, "Auto-negotiation enabled\n"); ++ ++ ew32(CTRL, ctrl); ++ e1e_flush(); ++ msleep(1); ++ ++ /* For these adapters, the SW defineable pin 1 is set when the optics ++ * detect a signal. If we have a signal, then poll for a "Link-Up" ++ * indication. ++ */ ++ if (hw->media_type == e1000_media_type_internal_serdes || ++ (er32(CTRL) & E1000_CTRL_SWDPIN1)) { ++ ret_val = e1000_poll_fiber_serdes_link_generic(hw); ++ } else { ++ hw_dbg(hw, "No signal detected\n"); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_config_collision_dist - Configure collision distance ++ * @hw: pointer to the HW structure ++ * ++ * Configures the collision distance to the default value and is used ++ * during link setup. Currently no func pointer exists and all ++ * implementations are handled in the generic version of this function. ++ **/ ++void e1000_config_collision_dist(struct e1000_hw *hw) ++{ ++ u32 tctl; ++ ++ tctl = er32(TCTL); ++ ++ tctl &= ~E1000_TCTL_COLD; ++ tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; ++ ++ ew32(TCTL, tctl); ++ e1e_flush(); ++} ++ ++/** ++ * e1000_set_fc_watermarks - Set flow control high/low watermarks ++ * @hw: pointer to the HW structure ++ * ++ * Sets the flow control high/low threshold (watermark) registers. If ++ * flow control XON frame transmission is enabled, then set XON frame ++ * tansmission as well. ++ **/ ++s32 e1000_set_fc_watermarks(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ s32 ret_val = E1000_SUCCESS; ++ u32 fcrtl = 0, fcrth = 0; ++ ++ /* Set the flow control receive threshold registers. Normally, ++ * these registers will be set to a default threshold that may be ++ * adjusted later by the driver's runtime code. However, if the ++ * ability to transmit pause frames is not enabled, then these ++ * registers will be set to 0. ++ */ ++ if (mac->fc & e1000_fc_tx_pause) { ++ /* We need to set up the Receive Threshold high and low water ++ * marks as well as (optionally) enabling the transmission of ++ * XON frames. ++ */ ++ fcrtl = mac->fc_low_water; ++ fcrtl |= E1000_FCRTL_XONE; ++ ++ fcrth = mac->fc_high_water; ++ } ++ ew32(FCRTL, fcrtl); ++ ew32(FCRTH, fcrth); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_force_mac_fc - Force the MAC's flow control settings ++ * @hw: pointer to the HW structure ++ * ++ * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the ++ * device control register to reflect the adapter settings. TFCE and RFCE ++ * need to be explicitly set by software when a copper PHY is used because ++ * autonegotiation is managed by the PHY rather than the MAC. Software must ++ * also configure these bits when link is forced on a fiber connection. ++ **/ ++s32 e1000_force_mac_fc(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 ctrl; ++ s32 ret_val = E1000_SUCCESS; ++ ++ ctrl = er32(CTRL); ++ ++ /* Because we didn't get link via the internal auto-negotiation ++ * mechanism (we either forced link or we got link via PHY ++ * auto-neg), we have to manually enable/disable transmit an ++ * receive flow control. ++ * ++ * The "Case" statement below enables/disable flow control ++ * according to the "mac->fc" parameter. ++ * ++ * The possible values of the "fc" parameter are: ++ * 0: Flow control is completely disabled ++ * 1: Rx flow control is enabled (we can receive pause ++ * frames but not send pause frames). ++ * 2: Tx flow control is enabled (we can send pause frames ++ * frames but we do not receive pause frames). ++ * 3: Both Rx and TX flow control (symmetric) is enabled. ++ * other: No other values should be possible at this point. ++ */ ++ hw_dbg(hw, "mac->fc = %u\n", mac->fc); ++ ++ switch (mac->fc) { ++ case e1000_fc_none: ++ ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); ++ break; ++ case e1000_fc_rx_pause: ++ ctrl &= (~E1000_CTRL_TFCE); ++ ctrl |= E1000_CTRL_RFCE; ++ break; ++ case e1000_fc_tx_pause: ++ ctrl &= (~E1000_CTRL_RFCE); ++ ctrl |= E1000_CTRL_TFCE; ++ break; ++ case e1000_fc_full: ++ ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); ++ break; ++ default: ++ hw_dbg(hw, "Flow control param set incorrectly\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ ew32(CTRL, ctrl); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_config_fc_after_link_up - Configures flow control after link ++ * @hw: pointer to the HW structure ++ * ++ * Checks the status of auto-negotiation after link up to ensure that the ++ * speed and duplex were not forced. If the link needed to be forced, then ++ * flow control needs to be forced also. If auto-negotiation is enabled ++ * and did not fail, then we configure flow control based on our link ++ * partner. ++ **/ ++s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ s32 ret_val = E1000_SUCCESS; ++ u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; ++ u16 speed, duplex; ++ ++ /* Check for the case where we have fiber media and auto-neg failed ++ * so we had to force link. In this case, we need to force the ++ * configuration of the MAC to match the "fc" parameter. ++ */ ++ if (mac->autoneg_failed) { ++ if (hw->media_type == e1000_media_type_fiber || ++ hw->media_type == e1000_media_type_internal_serdes) ++ ret_val = e1000_force_mac_fc(hw); ++ } else { ++ if (hw->media_type == e1000_media_type_copper) ++ ret_val = e1000_force_mac_fc(hw); ++ } ++ ++ if (ret_val) { ++ hw_dbg(hw, "Error forcing flow control settings\n"); ++ goto out; ++ } ++ ++ /* Check for the case where we have copper media and auto-neg is ++ * enabled. In this case, we need to check and see if Auto-Neg ++ * has completed, and if so, how the PHY and link partner has ++ * flow control configured. ++ */ ++ if ((hw->media_type == e1000_media_type_copper) && mac->autoneg) { ++ /* Read the MII Status Register and check to see if AutoNeg ++ * has completed. We read this twice because this reg has ++ * some "sticky" (latched) bits. ++ */ ++ ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg); ++ if (ret_val) ++ goto out; ++ ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg); ++ if (ret_val) ++ goto out; ++ ++ if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { ++ hw_dbg(hw, "Copper PHY and Auto Neg " ++ "has not completed.\n"); ++ goto out; ++ } ++ ++ /* The AutoNeg process has completed, so we now need to ++ * read both the Auto Negotiation Advertisement ++ * Register (Address 4) and the Auto_Negotiation Base ++ * Page Ability Register (Address 5) to determine how ++ * flow control was negotiated. ++ */ ++ ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg); ++ if (ret_val) ++ goto out; ++ ret_val = e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg); ++ if (ret_val) ++ goto out; ++ ++ /* Two bits in the Auto Negotiation Advertisement Register ++ * (Address 4) and two bits in the Auto Negotiation Base ++ * Page Ability Register (Address 5) determine flow control ++ * for both the PHY and the link partner. The following ++ * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, ++ * 1999, describes these PAUSE resolution bits and how flow ++ * control is determined based upon these settings. ++ * NOTE: DC = Don't Care ++ * ++ * LOCAL DEVICE | LINK PARTNER ++ * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution ++ *-------|---------|-------|---------|-------------------- ++ * 0 | 0 | DC | DC | e1000_fc_none ++ * 0 | 1 | 0 | DC | e1000_fc_none ++ * 0 | 1 | 1 | 0 | e1000_fc_none ++ * 0 | 1 | 1 | 1 | e1000_fc_tx_pause ++ * 1 | 0 | 0 | DC | e1000_fc_none ++ * 1 | DC | 1 | DC | e1000_fc_full ++ * 1 | 1 | 0 | 0 | e1000_fc_none ++ * 1 | 1 | 0 | 1 | e1000_fc_rx_pause ++ * ++ */ ++ /* Are both PAUSE bits set to 1? If so, this implies ++ * Symmetric Flow Control is enabled at both ends. The ++ * ASM_DIR bits are irrelevant per the spec. ++ * ++ * For Symmetric Flow Control: ++ * ++ * LOCAL DEVICE | LINK PARTNER ++ * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result ++ *-------|---------|-------|---------|-------------------- ++ * 1 | DC | 1 | DC | E1000_fc_full ++ * ++ */ ++ if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && ++ (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { ++ /* Now we need to check if the user selected RX ONLY ++ * of pause frames. In this case, we had to advertise ++ * FULL flow control because we could not advertise RX ++ * ONLY. Hence, we must now check to see if we need to ++ * turn OFF the TRANSMISSION of PAUSE frames. ++ */ ++ if (mac->original_fc == e1000_fc_full) { ++ mac->fc = e1000_fc_full; ++ hw_dbg(hw, "Flow Control = FULL.\r\n"); ++ } else { ++ mac->fc = e1000_fc_rx_pause; ++ hw_dbg(hw, "Flow Control = " ++ "RX PAUSE frames only.\r\n"); ++ } ++ } ++ /* For receiving PAUSE frames ONLY. ++ * ++ * LOCAL DEVICE | LINK PARTNER ++ * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result ++ *-------|---------|-------|---------|-------------------- ++ * 0 | 1 | 1 | 1 | e1000_fc_tx_pause ++ * ++ */ ++ else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && ++ (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && ++ (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && ++ (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { ++ mac->fc = e1000_fc_tx_pause; ++ hw_dbg(hw, "Flow Control = TX PAUSE frames only.\r\n"); ++ } ++ /* For transmitting PAUSE frames ONLY. ++ * ++ * LOCAL DEVICE | LINK PARTNER ++ * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result ++ *-------|---------|-------|---------|-------------------- ++ * 1 | 1 | 0 | 1 | e1000_fc_rx_pause ++ * ++ */ ++ else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && ++ (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && ++ !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && ++ (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { ++ mac->fc = e1000_fc_rx_pause; ++ hw_dbg(hw, "Flow Control = RX PAUSE frames only.\r\n"); ++ } ++ /* Per the IEEE spec, at this point flow control should be ++ * disabled. However, we want to consider that we could ++ * be connected to a legacy switch that doesn't advertise ++ * desired flow control, but can be forced on the link ++ * partner. So if we advertised no flow control, that is ++ * what we will resolve to. If we advertised some kind of ++ * receive capability (Rx Pause Only or Full Flow Control) ++ * and the link partner advertised none, we will configure ++ * ourselves to enable Rx Flow Control only. We can do ++ * this safely for two reasons: If the link partner really ++ * didn't want flow control enabled, and we enable Rx, no ++ * harm done since we won't be receiving any PAUSE frames ++ * anyway. If the intent on the link partner was to have ++ * flow control enabled, then by us enabling RX only, we ++ * can at least receive pause frames and process them. ++ * This is a good idea because in most cases, since we are ++ * predominantly a server NIC, more times than not we will ++ * be asked to delay transmission of packets than asking ++ * our link partner to pause transmission of frames. ++ */ ++ else if ((mac->original_fc == e1000_fc_none) || ++ (mac->original_fc == e1000_fc_tx_pause)) { ++ mac->fc = e1000_fc_none; ++ hw_dbg(hw, "Flow Control = NONE.\r\n"); ++ } else { ++ mac->fc = e1000_fc_rx_pause; ++ hw_dbg(hw, "Flow Control = RX PAUSE frames only.\r\n"); ++ } ++ ++ /* Now we need to do one last check... If we auto- ++ * negotiated to HALF DUPLEX, flow control should not be ++ * enabled per IEEE 802.3 spec. ++ */ ++ ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); ++ if (ret_val) { ++ hw_dbg(hw, "Error getting link speed and duplex\n"); ++ goto out; ++ } ++ ++ if (duplex == HALF_DUPLEX) ++ mac->fc = e1000_fc_none; ++ ++ /* Now we call a subroutine to actually force the MAC ++ * controller to use the correct flow control settings. ++ */ ++ ret_val = e1000_force_mac_fc(hw); ++ if (ret_val) { ++ hw_dbg(hw, "Error forcing flow control settings\n"); ++ goto out; ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_speed_and_duplex_copper - Retreive current speed/duplex ++ * @hw: pointer to the HW structure ++ * @speed: stores the current speed ++ * @duplex: stores the current duplex ++ * ++ * Read the status register for the current speed/duplex and store the current ++ * speed and duplex for copper connections. ++ **/ ++s32 e1000_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex) ++{ ++ u32 status; ++ ++ status = er32(STATUS); ++ if (status & E1000_STATUS_SPEED_1000) { ++ *speed = SPEED_1000; ++ hw_dbg(hw, "1000 Mbs, "); ++ } else if (status & E1000_STATUS_SPEED_100) { ++ *speed = SPEED_100; ++ hw_dbg(hw, "100 Mbs, "); ++ } else { ++ *speed = SPEED_10; ++ hw_dbg(hw, "10 Mbs, "); ++ } ++ ++ if (status & E1000_STATUS_FD) { ++ *duplex = FULL_DUPLEX; ++ hw_dbg(hw, "Full Duplex\n"); ++ } else { ++ *duplex = HALF_DUPLEX; ++ hw_dbg(hw, "Half Duplex\n"); ++ } ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_get_speed_and_duplex_fiber_serdes - Retreive current speed/duplex ++ * @hw: pointer to the HW structure ++ * @speed: stores the current speed ++ * @duplex: stores the current duplex ++ * ++ * Sets the speed and duplex to gigabit full duplex (the only possible option) ++ * for fiber/serdes links. ++ **/ ++s32 e1000_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex) ++{ ++ *speed = SPEED_1000; ++ *duplex = FULL_DUPLEX; ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_get_hw_semaphore - Acquire hardware semaphore ++ * @hw: pointer to the HW structure ++ * ++ * Acquire the HW semaphore to access the PHY or NVM ++ **/ ++s32 e1000_get_hw_semaphore(struct e1000_hw *hw) ++{ ++ u32 swsm; ++ s32 ret_val = E1000_SUCCESS; ++ s32 timeout = hw->nvm.word_size + 1; ++ s32 i = 0; ++ ++ /* Get the SW semaphore */ ++ while (i < timeout) { ++ swsm = er32(SWSM); ++ if (!(swsm & E1000_SWSM_SMBI)) ++ break; ++ ++ udelay(50); ++ i++; ++ } ++ ++ if (i == timeout) { ++ hw_dbg(hw, "Driver can't access device - SMBI bit is set.\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++ /* Get the FW semaphore. */ ++ for (i = 0; i < timeout; i++) { ++ swsm = er32(SWSM); ++ ew32(SWSM, swsm | E1000_SWSM_SWESMBI); ++ ++ /* Semaphore acquired if bit latched */ ++ if (er32(SWSM) & E1000_SWSM_SWESMBI) ++ break; ++ ++ udelay(50); ++ } ++ ++ if (i == timeout) { ++ /* Release semaphores */ ++ e1000_put_hw_semaphore(hw); ++ hw_dbg(hw, "Driver can't access the NVM\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_put_hw_semaphore - Release hardware semaphore ++ * @hw: pointer to the HW structure ++ * ++ * Release hardware semaphore used to access the PHY or NVM ++ **/ ++void e1000_put_hw_semaphore(struct e1000_hw *hw) ++{ ++ u32 swsm; ++ ++ swsm = er32(SWSM); ++ ++ swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); ++ ++ ew32(SWSM, swsm); ++} ++ ++/** ++ * e1000_get_auto_rd_done - Check for auto read completion ++ * @hw: pointer to the HW structure ++ * ++ * Check EEPROM for Auto Read done bit. ++ **/ ++s32 e1000_get_auto_rd_done(struct e1000_hw *hw) ++{ ++ s32 i = 0; ++ s32 ret_val = E1000_SUCCESS; ++ ++ while (i < AUTO_READ_DONE_TIMEOUT) { ++ if (er32(EECD) & E1000_EECD_AUTO_RD) ++ break; ++ msleep(1); ++ i++; ++ } ++ ++ if (i == AUTO_READ_DONE_TIMEOUT) { ++ hw_dbg(hw, "Auto read by HW from NVM has not completed.\n"); ++ ret_val = -E1000_ERR_RESET; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_valid_led_default - Verify a valid default LED config ++ * @hw: pointer to the HW structure ++ * @data: pointer to the NVM (EEPROM) ++ * ++ * Read the EEPROM for the current default LED configuration. If the ++ * LED configuration is not valid, set to a valid LED configuration. ++ **/ ++s32 e1000_valid_led_default(struct e1000_hw *hw, u16 *data) ++{ ++ s32 ret_val; ++ ++ ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); ++ if (ret_val) { ++ hw_dbg(hw, "NVM Read Error\n"); ++ goto out; ++ } ++ ++ if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) ++ *data = ID_LED_DEFAULT; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_id_led_init - ++ * @hw: pointer to the HW structure ++ * ++ **/ ++s32 e1000_id_led_init(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ s32 ret_val; ++ const u32 ledctl_mask = 0x000000FF; ++ const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; ++ const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; ++ u16 data, i, temp; ++ const u16 led_mask = 0x0F; ++ ++ ret_val = hw->nvm.ops.valid_led_default(hw, &data); ++ if (ret_val) ++ goto out; ++ ++ mac->ledctl_default = er32(LEDCTL); ++ mac->ledctl_mode1 = mac->ledctl_default; ++ mac->ledctl_mode2 = mac->ledctl_default; ++ ++ for (i = 0; i < 4; i++) { ++ temp = (data >> (i << 2)) & led_mask; ++ switch (temp) { ++ case ID_LED_ON1_DEF2: ++ case ID_LED_ON1_ON2: ++ case ID_LED_ON1_OFF2: ++ mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); ++ mac->ledctl_mode1 |= ledctl_on << (i << 3); ++ break; ++ case ID_LED_OFF1_DEF2: ++ case ID_LED_OFF1_ON2: ++ case ID_LED_OFF1_OFF2: ++ mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); ++ mac->ledctl_mode1 |= ledctl_off << (i << 3); ++ break; ++ default: ++ /* Do nothing */ ++ break; ++ } ++ switch (temp) { ++ case ID_LED_DEF1_ON2: ++ case ID_LED_ON1_ON2: ++ case ID_LED_OFF1_ON2: ++ mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); ++ mac->ledctl_mode2 |= ledctl_on << (i << 3); ++ break; ++ case ID_LED_DEF1_OFF2: ++ case ID_LED_ON1_OFF2: ++ case ID_LED_OFF1_OFF2: ++ mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); ++ mac->ledctl_mode2 |= ledctl_off << (i << 3); ++ break; ++ default: ++ /* Do nothing */ ++ break; ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_cleanup_led_generic - Set LED config to default operation ++ * @hw: pointer to the HW structure ++ * ++ * Remove the current LED configuration and set the LED configuration ++ * to the default value, saved from the EEPROM. ++ **/ ++s32 e1000_cleanup_led_generic(struct e1000_hw *hw) ++{ ++ ew32(LEDCTL, hw->mac.ledctl_default); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_blink_led - Blink LED ++ * @hw: pointer to the HW structure ++ * ++ * Blink the led's which are set to be on. ++ **/ ++s32 e1000_blink_led(struct e1000_hw *hw) ++{ ++ u32 ledctl_blink = 0; ++ u32 i; ++ ++ if (hw->media_type == e1000_media_type_fiber) { ++ /* always blink LED0 for PCI-E fiber */ ++ ledctl_blink = E1000_LEDCTL_LED0_BLINK | ++ (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); ++ } else { ++ /* set the blink bit for each LED that's "on" (0x0E) ++ * in ledctl_mode2 */ ++ ledctl_blink = hw->mac.ledctl_mode2; ++ for (i = 0; i < 4; i++) ++ if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == ++ E1000_LEDCTL_MODE_LED_ON) ++ ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << ++ (i * 8)); ++ } ++ ++ ew32(LEDCTL, ledctl_blink); ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_led_on_generic - Turn LED on ++ * @hw: pointer to the HW structure ++ * ++ * Turn LED on. ++ **/ ++s32 e1000_led_on_generic(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ ++ switch (hw->media_type) { ++ case e1000_media_type_fiber: ++ ctrl = er32(CTRL); ++ ctrl &= ~E1000_CTRL_SWDPIN0; ++ ctrl |= E1000_CTRL_SWDPIO0; ++ ew32(CTRL, ctrl); ++ break; ++ case e1000_media_type_copper: ++ ew32(LEDCTL, hw->mac.ledctl_mode2); ++ break; ++ default: ++ break; ++ } ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_led_off_generic - Turn LED off ++ * @hw: pointer to the HW structure ++ * ++ * Turn LED off. ++ **/ ++s32 e1000_led_off_generic(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ ++ switch (hw->media_type) { ++ case e1000_media_type_fiber: ++ ctrl = er32(CTRL); ++ ctrl |= E1000_CTRL_SWDPIN0; ++ ctrl |= E1000_CTRL_SWDPIO0; ++ ew32(CTRL, ctrl); ++ break; ++ case e1000_media_type_copper: ++ ew32(LEDCTL, hw->mac.ledctl_mode1); ++ break; ++ default: ++ break; ++ } ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_set_pcie_no_snoop - Set PCI-express capabilities ++ * @hw: pointer to the HW structure ++ * @no_snoop: bitmap of snoop events ++ * ++ * Set the PCI-express register to snoop for events enabled in 'no_snoop'. ++ **/ ++void e1000_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop) ++{ ++ u32 gcr; ++ ++ if (no_snoop) { ++ gcr = er32(GCR); ++ gcr &= ~(PCIE_NO_SNOOP_ALL); ++ gcr |= no_snoop; ++ ew32(GCR, gcr); ++ } ++} ++ ++/** ++ * e1000_disable_pcie_master - Disables PCI-express master access ++ * @hw: pointer to the HW structure ++ * ++ * Returns 0 (E1000_SUCCESS) if successful, else returns -10 ++ * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not casued ++ * the master requests to be disabled. ++ * ++ * Disables PCI-Express master access and verifies there are no pending ++ * requests. ++ **/ ++s32 e1000_disable_pcie_master(struct e1000_hw *hw) ++{ ++ u32 ctrl; ++ s32 timeout = MASTER_DISABLE_TIMEOUT; ++ s32 ret_val = E1000_SUCCESS; ++ ++ ctrl = er32(CTRL); ++ ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; ++ ew32(CTRL, ctrl); ++ ++ while (timeout) { ++ if (!(er32(STATUS) & ++ E1000_STATUS_GIO_MASTER_ENABLE)) ++ break; ++ udelay(100); ++ timeout--; ++ } ++ ++ if (!timeout) { ++ hw_dbg(hw, "Master requests are pending.\n"); ++ ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_reset_adaptive - Reset Adaptive Interframe Spacing ++ * @hw: pointer to the HW structure ++ * ++ * Reset the Adaptive Interframe Spacing throttle to default values. ++ **/ ++void e1000_reset_adaptive(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ ++ mac->current_ifs_val = 0; ++ mac->ifs_min_val = IFS_MIN; ++ mac->ifs_max_val = IFS_MAX; ++ mac->ifs_step_size = IFS_STEP; ++ mac->ifs_ratio = IFS_RATIO; ++ ++ mac->in_ifs_mode = 0; ++ ew32(AIT, 0); ++} ++ ++/** ++ * e1000_update_adaptive - Update Adaptive Interframe Spacing ++ * @hw: pointer to the HW structure ++ * ++ * Update the Adaptive Interframe Spacing Throttle value based on the ++ * time between transmitted packets and time between collisions. ++ **/ ++void e1000_update_adaptive(struct e1000_hw *hw) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ ++ if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { ++ if (mac->tx_packet_delta > MIN_NUM_XMITS) { ++ mac->in_ifs_mode = 1; ++ if (mac->current_ifs_val < mac->ifs_max_val) { ++ if (!mac->current_ifs_val) ++ mac->current_ifs_val = mac->ifs_min_val; ++ else ++ mac->current_ifs_val += ++ mac->ifs_step_size; ++ ew32(AIT, ++ mac->current_ifs_val); ++ } ++ } ++ } else { ++ if (mac->in_ifs_mode && ++ (mac->tx_packet_delta <= MIN_NUM_XMITS)) { ++ mac->current_ifs_val = 0; ++ mac->in_ifs_mode = 0; ++ ew32(AIT, 0); ++ } ++ } ++} ++ ++/** ++ * e1000_raise_eec_clk - Raise EEPROM clock ++ * @hw: pointer to the HW structure ++ * @eecd: pointer to the EEPROM ++ * ++ * Enable/Raise the EEPROM clock bit. ++ **/ ++static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) ++{ ++ *eecd = *eecd | E1000_EECD_SK; ++ ew32(EECD, *eecd); ++ e1e_flush(); ++ udelay(hw->nvm.delay_usec); ++} ++ ++/** ++ * e1000_lower_eec_clk - Lower EEPROM clock ++ * @hw: pointer to the HW structure ++ * @eecd: pointer to the EEPROM ++ * ++ * Clear/Lower the EEPROM clock bit. ++ **/ ++static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) ++{ ++ *eecd = *eecd & ~E1000_EECD_SK; ++ ew32(EECD, *eecd); ++ e1e_flush(); ++ udelay(hw->nvm.delay_usec); ++} ++ ++/** ++ * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM ++ * @hw: pointer to the HW structure ++ * @data: data to send to the EEPROM ++ * @count: number of bits to shift out ++ * ++ * We need to shift 'count' bits out to the EEPROM. So, the value in the ++ * "data" parameter will be shifted out to the EEPROM one bit at a time. ++ * In order to do this, "data" must be broken down into bits. ++ **/ ++static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ u32 eecd = er32(EECD); ++ u32 mask; ++ ++ mask = 0x01 << (count - 1); ++ if (nvm->type == e1000_nvm_eeprom_spi) ++ eecd |= E1000_EECD_DO; ++ ++ do { ++ eecd &= ~E1000_EECD_DI; ++ ++ if (data & mask) ++ eecd |= E1000_EECD_DI; ++ ++ ew32(EECD, eecd); ++ e1e_flush(); ++ ++ udelay(nvm->delay_usec); ++ ++ e1000_raise_eec_clk(hw, &eecd); ++ e1000_lower_eec_clk(hw, &eecd); ++ ++ mask >>= 1; ++ } while (mask); ++ ++ eecd &= ~E1000_EECD_DI; ++ ew32(EECD, eecd); ++} ++ ++/** ++ * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM ++ * @hw: pointer to the HW structure ++ * @count: number of bits to shift in ++ * ++ * In order to read a register from the EEPROM, we need to shift 'count' bits ++ * in from the EEPROM. Bits are "shifted in" by raising the clock input to ++ * the EEPROM (setting the SK bit), and then reading the value of the data out ++ * "DO" bit. During this "shifting in" process the data in "DI" bit should ++ * always be clear. ++ **/ ++static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count) ++{ ++ u32 eecd; ++ u32 i; ++ u16 data; ++ ++ eecd = er32(EECD); ++ ++ eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); ++ data = 0; ++ ++ for (i = 0; i < count; i++) { ++ data <<= 1; ++ e1000_raise_eec_clk(hw, &eecd); ++ ++ eecd = er32(EECD); ++ ++ eecd &= ~E1000_EECD_DI; ++ if (eecd & E1000_EECD_DO) ++ data |= 1; ++ ++ e1000_lower_eec_clk(hw, &eecd); ++ } ++ ++ return data; ++} ++ ++/** ++ * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion ++ * @hw: pointer to the HW structure ++ * @ee_reg: EEPROM flag for polling ++ * ++ * Polls the EEPROM status bit for either read or write completion based ++ * upon the value of 'ee_reg'. ++ **/ ++s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) ++{ ++ u32 attempts = 100000; ++ u32 i, reg = 0; ++ s32 ret_val = -E1000_ERR_NVM; ++ ++ for (i = 0; i < attempts; i++) { ++ if (ee_reg == E1000_NVM_POLL_READ) ++ reg = er32(EERD); ++ else ++ reg = er32(EEWR); ++ ++ if (reg & E1000_NVM_RW_REG_DONE) { ++ ret_val = E1000_SUCCESS; ++ break; ++ } ++ ++ udelay(5); ++ } ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_acquire_nvm - Generic request for access to EEPROM ++ * @hw: pointer to the HW structure ++ * ++ * Set the EEPROM access request bit and wait for EEPROM access grant bit. ++ * Return successful if access grant bit set, else clear the request for ++ * EEPROM access and return -E1000_ERR_NVM (-1). ++ **/ ++s32 e1000_acquire_nvm(struct e1000_hw *hw) ++{ ++ u32 eecd = er32(EECD); ++ s32 timeout = E1000_NVM_GRANT_ATTEMPTS; ++ s32 ret_val = E1000_SUCCESS; ++ ++ ew32(EECD, eecd | E1000_EECD_REQ); ++ eecd = er32(EECD); ++ ++ while (timeout) { ++ if (eecd & E1000_EECD_GNT) ++ break; ++ udelay(5); ++ eecd = er32(EECD); ++ timeout--; ++ } ++ ++ if (!timeout) { ++ eecd &= ~E1000_EECD_REQ; ++ ew32(EECD, eecd); ++ hw_dbg(hw, "Could not acquire NVM grant\n"); ++ ret_val = -E1000_ERR_NVM; ++ } ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_standby_nvm - Return EEPROM to standby state ++ * @hw: pointer to the HW structure ++ * ++ * Return the EEPROM to a standby state. ++ **/ ++static void e1000_standby_nvm(struct e1000_hw *hw) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ u32 eecd = er32(EECD); ++ ++ if (nvm->type == e1000_nvm_eeprom_spi) { ++ /* Toggle CS to flush commands */ ++ eecd |= E1000_EECD_CS; ++ ew32(EECD, eecd); ++ e1e_flush(); ++ udelay(nvm->delay_usec); ++ eecd &= ~E1000_EECD_CS; ++ ew32(EECD, eecd); ++ e1e_flush(); ++ udelay(nvm->delay_usec); ++ } ++} ++ ++/** ++ * e1000_stop_nvm - Terminate EEPROM command ++ * @hw: pointer to the HW structure ++ * ++ * Terminates the current command by inverting the EEPROM's chip select pin. ++ **/ ++static void e1000_stop_nvm(struct e1000_hw *hw) ++{ ++ u32 eecd; ++ ++ eecd = er32(EECD); ++ if (hw->nvm.type == e1000_nvm_eeprom_spi) { ++ /* Pull CS high */ ++ eecd |= E1000_EECD_CS; ++ e1000_lower_eec_clk(hw, &eecd); ++ } ++} ++ ++/** ++ * e1000_release_nvm - Release exclusive access to EEPROM ++ * @hw: pointer to the HW structure ++ * ++ * Stop any current commands to the EEPROM and clear the EEPROM request bit. ++ **/ ++void e1000_release_nvm(struct e1000_hw *hw) ++{ ++ u32 eecd; ++ ++ e1000_stop_nvm(hw); ++ ++ eecd = er32(EECD); ++ eecd &= ~E1000_EECD_REQ; ++ ew32(EECD, eecd); ++} ++ ++/** ++ * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write ++ * @hw: pointer to the HW structure ++ * ++ * Setups the EEPROM for reading and writing. ++ **/ ++static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ u32 eecd = er32(EECD); ++ s32 ret_val = E1000_SUCCESS; ++ u16 timeout = 0; ++ u8 spi_stat_reg; ++ ++ if (nvm->type == e1000_nvm_eeprom_spi) { ++ /* Clear SK and CS */ ++ eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); ++ ew32(EECD, eecd); ++ udelay(1); ++ timeout = NVM_MAX_RETRY_SPI; ++ ++ /* Read "Status Register" repeatedly until the LSB is cleared. ++ * The EEPROM will signal that the command has been completed ++ * by clearing bit 0 of the internal status register. If it's ++ * not cleared within 'timeout', then error out. */ ++ while (timeout) { ++ e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, ++ hw->nvm.opcode_bits); ++ spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8); ++ if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) ++ break; ++ ++ udelay(5); ++ e1000_standby_nvm(hw); ++ timeout--; ++ } ++ ++ if (!timeout) { ++ hw_dbg(hw, "SPI NVM Status error\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_read_nvm_spi - Read EEPROM's using SPI ++ * @hw: pointer to the HW structure ++ * @offset: offset of word in the EEPROM to read ++ * @words: number of words to read ++ * @data: word read from the EEPROM ++ * ++ * Reads a 16 bit word from the EEPROM. ++ **/ ++s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ u32 i = 0; ++ s32 ret_val; ++ u16 word_in; ++ u8 read_opcode = NVM_READ_OPCODE_SPI; ++ ++ /* A check for invalid values: offset too large, too many words, ++ * and not enough words. */ ++ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || ++ (words == 0)) { ++ hw_dbg(hw, "nvm parameter(s) out of bounds\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++ ret_val = nvm->ops.acquire_nvm(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000_ready_nvm_eeprom(hw); ++ if (ret_val) ++ goto release; ++ ++ e1000_standby_nvm(hw); ++ ++ if ((nvm->address_bits == 8) && (offset >= 128)) ++ read_opcode |= NVM_A8_OPCODE_SPI; ++ ++ /* Send the READ command (opcode + addr) */ ++ e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); ++ e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits); ++ ++ /* Read the data. SPI NVMs increment the address with each byte ++ * read and will roll over if reading beyond the end. This allows ++ * us to read the whole NVM from any offset */ ++ for (i = 0; i < words; i++) { ++ word_in = e1000_shift_in_eec_bits(hw, 16); ++ data[i] = (word_in >> 8) | (word_in << 8); ++ } ++ ++release: ++ nvm->ops.release_nvm(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_read_nvm_eerd - Reads EEPROM using EERD register ++ * @hw: pointer to the HW structure ++ * @offset: offset of word in the EEPROM to read ++ * @words: number of words to read ++ * @data: word read from the EEPROM ++ * ++ * Reads a 16 bit word from the EEPROM using the EERD register. ++ **/ ++s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ u32 i, eerd = 0; ++ s32 ret_val = E1000_SUCCESS; ++ ++ /* A check for invalid values: offset too large, too many words, ++ * and not enough words. */ ++ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || ++ (words == 0)) { ++ hw_dbg(hw, "nvm parameter(s) out of bounds\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++ for (i = 0; i < words; i++) { ++ eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) + ++ E1000_NVM_RW_REG_START; ++ ++ ew32(EERD, eerd); ++ ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); ++ if (ret_val) ++ break; ++ ++ data[i] = (er32(EERD) >> ++ E1000_NVM_RW_REG_DATA); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_write_nvm_spi - Write to EEPROM using SPI ++ * @hw: pointer to the HW structure ++ * @offset: offset within the EEPROM to be written to ++ * @words: number of words to write ++ * @data: 16 bit word(s) to be written to the EEPROM ++ * ++ * Writes data to EEPROM at offset using SPI interface. ++ * ++ * If e1000_update_nvm_checksum is not called after this function , the ++ * EEPROM will most likley contain an invalid checksum. ++ **/ ++s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) ++{ ++ struct e1000_nvm_info *nvm = &hw->nvm; ++ s32 ret_val; ++ u16 widx = 0; ++ ++ /* A check for invalid values: offset too large, too many words, ++ * and not enough words. */ ++ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || ++ (words == 0)) { ++ hw_dbg(hw, "nvm parameter(s) out of bounds\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++ ret_val = nvm->ops.acquire_nvm(hw); ++ if (ret_val) ++ goto out; ++ ++ msleep(10); ++ ++ while (widx < words) { ++ u8 write_opcode = NVM_WRITE_OPCODE_SPI; ++ ++ ret_val = e1000_ready_nvm_eeprom(hw); ++ if (ret_val) ++ goto release; ++ ++ e1000_standby_nvm(hw); ++ ++ /* Send the WRITE ENABLE command (8 bit opcode) */ ++ e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, ++ nvm->opcode_bits); ++ ++ e1000_standby_nvm(hw); ++ ++ /* Some SPI eeproms use the 8th address bit embedded in the ++ * opcode */ ++ if ((nvm->address_bits == 8) && (offset >= 128)) ++ write_opcode |= NVM_A8_OPCODE_SPI; ++ ++ /* Send the Write command (8-bit opcode + addr) */ ++ e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); ++ e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), ++ nvm->address_bits); ++ ++ /* Loop to allow for up to whole page write of eeprom */ ++ while (widx < words) { ++ u16 word_out = data[widx]; ++ word_out = (word_out >> 8) | (word_out << 8); ++ e1000_shift_out_eec_bits(hw, word_out, 16); ++ widx++; ++ ++ if ((((offset + widx) * 2) % nvm->page_size) == 0) { ++ e1000_standby_nvm(hw); ++ break; ++ } ++ } ++ } ++ ++ msleep(10); ++release: ++ nvm->ops.release_nvm(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_read_mac_addr - Read device MAC address ++ * @hw: pointer to the HW structure ++ * ++ * Reads the device MAC address from the EEPROM and stores the value. ++ * Since devices with two ports use the same EEPROM, we increment the ++ * last bit in the MAC address for the second port. ++ **/ ++s32 e1000_read_mac_addr(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 offset, nvm_data, i; ++ ++ for (i = 0; i < ETH_ALEN; i += 2) { ++ offset = i >> 1; ++ ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data); ++ if (ret_val) { ++ hw_dbg(hw, "NVM Read Error\n"); ++ goto out; ++ } ++ hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); ++ hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8); ++ } ++ ++ /* Flip last bit of mac address if we're on second port */ ++ if (hw->bus.func == E1000_FUNC_1) ++ hw->mac.perm_addr[5] ^= 1; ++ ++ for (i = 0; i < ETH_ALEN; i++) ++ hw->mac.addr[i] = hw->mac.perm_addr[i]; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum ++ * @hw: pointer to the HW structure ++ * ++ * Calculates the EEPROM checksum by reading/adding each word of the EEPROM ++ * and then verifies that the sum of the EEPROM is equal to 0xBABA. ++ **/ ++s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 checksum = 0; ++ u16 i, nvm_data; ++ ++ for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { ++ ret_val = e1000_read_nvm(hw, i, 1, &nvm_data); ++ if (ret_val) { ++ hw_dbg(hw, "NVM Read Error\n"); ++ goto out; ++ } ++ checksum += nvm_data; ++ } ++ ++ if (checksum != (u16) NVM_SUM) { ++ hw_dbg(hw, "NVM Checksum Invalid\n"); ++ ret_val = -E1000_ERR_NVM; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_update_nvm_checksum_generic - Update EEPROM checksum ++ * @hw: pointer to the HW structure ++ * ++ * Updates the EEPROM checksum by reading/adding each word of the EEPROM ++ * up to the checksum. Then calculates the EEPROM checksum and writes the ++ * value to the EEPROM. ++ **/ ++s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw) ++{ ++ s32 ret_val; ++ u16 checksum = 0; ++ u16 i, nvm_data; ++ ++ for (i = 0; i < NVM_CHECKSUM_REG; i++) { ++ ret_val = e1000_read_nvm(hw, i, 1, &nvm_data); ++ if (ret_val) { ++ hw_dbg(hw, "NVM Read Error while updating checksum.\n"); ++ goto out; ++ } ++ checksum += nvm_data; ++ } ++ checksum = (u16) NVM_SUM - checksum; ++ ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum); ++ if (ret_val) { ++ hw_dbg(hw, "NVM Write Error while updating checksum.\n"); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_reload_nvm - Reloads EEPROM ++ * @hw: pointer to the HW structure ++ * ++ * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the ++ * extended control register. ++ **/ ++void e1000_reload_nvm(struct e1000_hw *hw) ++{ ++ u32 ctrl_ext; ++ ++ udelay(10); ++ ctrl_ext = er32(CTRL_EXT); ++ ctrl_ext |= E1000_CTRL_EXT_EE_RST; ++ ew32(CTRL_EXT, ctrl_ext); ++ e1e_flush(); ++} ++ ++/** ++ * e1000_calculate_checksum - Calculate checksum for buffer ++ * @buffer: pointer to EEPROM ++ * @length: size of EEPROM to calculate a checksum for ++ * ++ * Calculates the checksum for some buffer on a specified length. The ++ * checksum calculated is returned. ++ **/ ++static u8 e1000_calculate_checksum(u8 *buffer, u32 length) ++{ ++ u32 i; ++ u8 sum = 0; ++ ++ if (!buffer) ++ return 0; ++ ++ for (i = 0; i < length; i++) ++ sum += buffer[i]; ++ ++ return (u8) (0 - sum); ++} ++ ++/** ++ * e1000_mng_enable_host_if - Checks host interface is enabled ++ * @hw: pointer to the HW structure ++ * ++ * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND ++ * ++ * This function checks whether the HOST IF is enabled for command operaton ++ * and also checks whether the previous command is completed. It busy waits ++ * in case of previous command is not completed. ++ **/ ++static s32 e1000_mng_enable_host_if(struct e1000_hw *hw) ++{ ++ u32 hicr; ++ s32 ret_val = E1000_SUCCESS; ++ u8 i; ++ ++ /* Check that the host interface is enabled. */ ++ hicr = er32(HICR); ++ if ((hicr & E1000_HICR_EN) == 0) { ++ hw_dbg(hw, "E1000_HOST_EN bit disabled.\n"); ++ ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND; ++ goto out; ++ } ++ /* check the previous command is completed */ ++ for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { ++ hicr = er32(HICR); ++ if (!(hicr & E1000_HICR_C)) ++ break; ++ mdelay(1); ++ } ++ ++ if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { ++ hw_dbg(hw, "Previous command timeout failed .\n"); ++ ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_check_mng_mode - check managament mode ++ * @hw: pointer to the HW structure ++ * ++ * Reads the firmware semaphore register and returns true (>0) if ++ * manageability is enabled, else false (0). ++ **/ ++bool e1000_check_mng_mode(struct e1000_hw *hw) ++{ ++ u32 fwsm = er32(FWSM); ++ ++ return (fwsm & E1000_FWSM_MODE_MASK) == hw->mac.ops.mng_mode_enab; ++} ++ ++/** ++ * e1000_enable_tx_pkt_filtering - Enable packet filtering on TX ++ * @hw: pointer to the HW structure ++ * ++ * Enables packet filtering on transmit packets if manageability is enabled ++ * and host interface is enabled. ++ **/ ++bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) ++{ ++ struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie; ++ u32 *buffer = (u32 *)&hw->mng_cookie; ++ u32 offset; ++ s32 ret_val, hdr_csum, csum; ++ u8 i, len; ++ bool tx_filter = 1; ++ ++ /* No manageability, no filtering */ ++ if (!e1000_check_mng_mode(hw)) { ++ tx_filter = 0; ++ goto out; ++ } ++ ++ /* If we can't read from the host interface for whatever ++ * reason, disable filtering. ++ */ ++ ret_val = e1000_mng_enable_host_if(hw); ++ if (ret_val != E1000_SUCCESS) { ++ tx_filter = 0; ++ goto out; ++ } ++ ++ /* Read in the header. Length and offset are in dwords. */ ++ len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2; ++ offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2; ++ for (i = 0; i < len; i++) ++ *(buffer + i) = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset + i); ++ hdr_csum = hdr->checksum; ++ hdr->checksum = 0; ++ csum = e1000_calculate_checksum((u8 *)hdr, ++ E1000_MNG_DHCP_COOKIE_LENGTH); ++ /* If either the checksums or signature don't match, then ++ * the cookie area isn't considered valid, in which case we ++ * take the safe route of assuming Tx filtering is enabled. ++ */ ++ if (hdr_csum != csum) ++ goto out; ++ if (hdr->signature != E1000_IAMT_SIGNATURE) ++ goto out; ++ ++ /* Cookie area is valid, make the final check for filtering. */ ++ if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) ++ tx_filter = 0; ++ ++out: ++ hw->mac.tx_pkt_filtering = tx_filter; ++ return tx_filter; ++} ++ ++/** ++ * e1000_mng_write_cmd_header - Writes manageability command header ++ * @hw: pointer to the HW structure ++ * @hdr: pointer to the host interface command header ++ * ++ * Writes the command header after does the checksum calculation. ++ **/ ++s32 e1000_mng_write_cmd_header(struct e1000_hw *hw, ++ struct e1000_host_mng_command_header *hdr) ++{ ++ u16 i, length = sizeof(struct e1000_host_mng_command_header); ++ ++ /* Write the whole command header structure with new checksum. */ ++ ++ hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length); ++ ++ length >>= 2; ++ /* Write the relevant command block into the ram area. */ ++ for (i = 0; i < length; i++) { ++ E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, i, ++ *((u32 *) hdr + i)); ++ e1e_flush(); ++ } ++ ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_mng_host_if_write - Writes to the manageability host interface ++ * @hw: pointer to the HW structure ++ * @buffer: pointer to the host interface buffer ++ * @length: size of the buffer ++ * @offset: location in the buffer to write to ++ * @sum: sum of the data (not checksum) ++ * ++ * This function writes the buffer content at the offset given on the host if. ++ * It also does alignment considerations to do the writes in most efficient ++ * way. Also fills up the sum of the buffer in *buffer parameter. ++ **/ ++static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, ++ u16 length, u16 offset, u8 *sum) ++{ ++ u8 *tmp; ++ u8 *bufptr = buffer; ++ u32 data = 0; ++ s32 ret_val = E1000_SUCCESS; ++ u16 remaining, i, j, prev_bytes; ++ ++ /* sum = only sum of the data and it is not checksum */ ++ ++ if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) { ++ ret_val = -E1000_ERR_PARAM; ++ goto out; ++ } ++ ++ tmp = (u8 *)&data; ++ prev_bytes = offset & 0x3; ++ offset >>= 2; ++ ++ if (prev_bytes) { ++ data = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset); ++ for (j = prev_bytes; j < sizeof(u32); j++) { ++ *(tmp + j) = *bufptr++; ++ *sum += *(tmp + j); ++ } ++ E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset, data); ++ length -= j - prev_bytes; ++ offset++; ++ } ++ ++ remaining = length & 0x3; ++ length -= remaining; ++ ++ /* Calculate length in DWORDs */ ++ length >>= 2; ++ ++ /* The device driver writes the relevant command block into the ++ * ram area. */ ++ for (i = 0; i < length; i++) { ++ for (j = 0; j < sizeof(u32); j++) { ++ *(tmp + j) = *bufptr++; ++ *sum += *(tmp + j); ++ } ++ ++ E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data); ++ } ++ if (remaining) { ++ for (j = 0; j < sizeof(u32); j++) { ++ if (j < remaining) ++ *(tmp + j) = *bufptr++; ++ else ++ *(tmp + j) = 0; ++ ++ *sum += *(tmp + j); ++ } ++ E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_mng_write_dhcp_info - Writes DHCP info to host interface ++ * @hw: pointer to the HW structure ++ * @buffer: pointer to the host interface ++ * @length: size of the buffer ++ * ++ * Writes the DHCP information to the host interface. ++ **/ ++s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length) ++{ ++ struct e1000_host_mng_command_header hdr; ++ s32 ret_val; ++ u32 hicr; ++ ++ hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; ++ hdr.command_length = length; ++ hdr.reserved1 = 0; ++ hdr.reserved2 = 0; ++ hdr.checksum = 0; ++ ++ /* Enable the host interface */ ++ ret_val = e1000_mng_enable_host_if(hw); ++ if (ret_val) ++ goto out; ++ ++ /* Populate the host interface with the contents of "buffer". */ ++ ret_val = e1000_mng_host_if_write(hw, buffer, length, ++ sizeof(hdr), &(hdr.checksum)); ++ if (ret_val) ++ goto out; ++ ++ /* Write the manageability command header */ ++ ret_val = e1000_mng_write_cmd_header(hw, &hdr); ++ if (ret_val) ++ goto out; ++ ++ /* Tell the ARC a new command is pending. */ ++ hicr = er32(HICR); ++ ew32(HICR, hicr | E1000_HICR_C); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_enable_mng_pass_thru - Enable processing of ARP's ++ * @hw: pointer to the HW structure ++ * ++ * Verifies the hardware needs to allow ARPs to be processed by the host. ++ **/ ++bool e1000_enable_mng_pass_thru(struct e1000_hw *hw) ++{ ++ u32 manc; ++ u32 fwsm, factps; ++ bool ret_val = 0; ++ ++ manc = er32(MANC); ++ ++ if (!(manc & E1000_MANC_RCV_TCO_EN) || ++ !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) ++ goto out; ++ ++ if (hw->mac.arc_subsystem_valid) { ++ fwsm = er32(FWSM); ++ factps = er32(FACTPS); ++ ++ if (!(factps & E1000_FACTPS_MNGCG) && ++ ((fwsm & E1000_FWSM_MODE_MASK) == ++ (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) { ++ ret_val = 1; ++ goto out; ++ } ++ } else { ++ if ((manc & E1000_MANC_SMBUS_EN) && ++ !(manc & E1000_MANC_ASF_EN)) { ++ ret_val = 1; ++ goto out; ++ } ++ } ++ ++out: ++ return ret_val; ++} ++ +diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c +new file mode 100644 +index 0000000..2d0e78c +--- /dev/null ++++ b/drivers/net/e1000e/netdev.c +@@ -0,0 +1,4413 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2007 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS <linux.nics@intel.com> ++ e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#include <linux/module.h> ++#include <linux/types.h> ++#include <linux/init.h> ++#include <linux/vmalloc.h> ++#include <linux/pagemap.h> ++#include <linux/netdevice.h> ++#include <linux/tcp.h> ++#include <linux/ipv6.h> ++#include <net/checksum.h> ++#include <net/ip6_checksum.h> ++#include <linux/mii.h> ++#include <linux/ethtool.h> ++#include <linux/if_vlan.h> ++#include <linux/cpu.h> ++#include <linux/smp.h> ++ ++#include "e1000.h" ++ ++#define DRV_VERSION "0.2.0" ++char e1000_driver_name[] = "e1000e"; ++const char e1000_driver_version[] = DRV_VERSION; ++ ++const struct e1000_info * e1000_info_tbl[] = { ++ [board_82571] = &e1000_82571_info, ++ [board_82572] = &e1000_82572_info, ++ [board_82573] = &e1000_82573_info, ++ [board_80003es2lan] = &e1000_es2_info, ++ [board_ich8lan] = &e1000_ich8_info, ++ [board_ich9lan] = &e1000_ich9_info, ++}; ++ ++#ifdef DEBUG ++/** ++ * e1000_get_hw_dev_name - return device name string ++ * used by hardware layer to print debugging information ++ **/ ++char *e1000_get_hw_dev_name(struct e1000_hw *hw) ++{ ++ struct e1000_adapter *adapter = hw->back; ++ struct net_device *netdev = adapter->netdev; ++ return netdev->name; ++} ++#endif ++ ++/** ++ * e1000_desc_unused - calculate if we have unused descriptors ++ **/ ++static int e1000_desc_unused(struct e1000_ring *ring) ++{ ++ if (ring->next_to_clean > ring->next_to_use) ++ return ring->next_to_clean - ring->next_to_use - 1; ++ ++ return ring->count + ring->next_to_clean - ring->next_to_use - 1; ++} ++ ++/** ++ * e1000_receive_skb - helper function to handle rx indications ++ * @adapter: board private structure ++ * @status: descriptor status field as written by hardware ++ * @vlan: descriptor vlan field as written by hardware (no le/be conversion) ++ * @skb: pointer to sk_buff to be indicated to stack ++ **/ ++static void e1000_receive_skb(struct e1000_adapter *adapter, ++ struct net_device *netdev, ++ struct sk_buff *skb, ++ u8 status, u16 vlan) ++{ ++ skb->protocol = eth_type_trans(skb, netdev); ++ ++ if (adapter->vlgrp && (status & E1000_RXD_STAT_VP)) ++ vlan_hwaccel_receive_skb(skb, adapter->vlgrp, ++ le16_to_cpu(vlan) & ++ E1000_RXD_SPC_VLAN_MASK); ++ else ++ netif_receive_skb(skb); ++ ++ netdev->last_rx = jiffies; ++} ++ ++/** ++ * e1000_rx_checksum - Receive Checksum Offload for 82543 ++ * @adapter: board private structure ++ * @status_err: receive descriptor status and error fields ++ * @csum: receive descriptor csum field ++ * @sk_buff: socket buffer with received data ++ **/ ++static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err, ++ u32 csum, struct sk_buff *skb) ++{ ++ u16 status = (u16)status_err; ++ u8 errors = (u8)(status_err >> 24); ++ skb->ip_summed = CHECKSUM_NONE; ++ ++ /* Ignore Checksum bit is set */ ++ if (status & E1000_RXD_STAT_IXSM) ++ return; ++ /* TCP/UDP checksum error bit is set */ ++ if (errors & E1000_RXD_ERR_TCPE) { ++ /* let the stack verify checksum errors */ ++ adapter->hw_csum_err++; ++ return; ++ } ++ ++ /* TCP/UDP Checksum has not been calculated */ ++ if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))) ++ return; ++ ++ /* It must be a TCP or UDP packet with a valid checksum */ ++ if (status & E1000_RXD_STAT_TCPCS) { ++ /* TCP checksum is good */ ++ skb->ip_summed = CHECKSUM_UNNECESSARY; ++ } else { ++ /* IP fragment with UDP payload */ ++ /* Hardware complements the payload checksum, so we undo it ++ * and then put the value in host order for further stack use. ++ */ ++ csum = ntohl(csum ^ 0xFFFF); ++ skb->csum = csum; ++ skb->ip_summed = CHECKSUM_COMPLETE; ++ } ++ adapter->hw_csum_good++; ++} ++ ++/** ++ * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended ++ * @adapter: address of board private structure ++ **/ ++static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter, ++ int cleaned_count) ++{ ++ struct net_device *netdev = adapter->netdev; ++ struct pci_dev *pdev = adapter->pdev; ++ struct e1000_ring *rx_ring = adapter->rx_ring; ++ struct e1000_rx_desc *rx_desc; ++ struct e1000_buffer *buffer_info; ++ struct sk_buff *skb; ++ unsigned int i; ++ unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN; ++ ++ i = rx_ring->next_to_use; ++ buffer_info = &rx_ring->buffer_info[i]; ++ ++ while (cleaned_count--) { ++ skb = buffer_info->skb; ++ if (skb) { ++ skb_trim(skb, 0); ++ goto map_skb; ++ } ++ ++ skb = netdev_alloc_skb(netdev, bufsz); ++ if (!skb) { ++ /* Better luck next round */ ++ adapter->alloc_rx_buff_failed++; ++ break; ++ } ++ ++ /* Make buffer alignment 2 beyond a 16 byte boundary ++ * this will result in a 16 byte aligned IP header after ++ * the 14 byte MAC header is removed ++ */ ++ skb_reserve(skb, NET_IP_ALIGN); ++ ++ buffer_info->skb = skb; ++map_skb: ++ buffer_info->dma = pci_map_single(pdev, skb->data, ++ adapter->rx_buffer_len, ++ PCI_DMA_FROMDEVICE); ++ ++ rx_desc = E1000_RX_DESC(*rx_ring, i); ++ rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); ++ ++ i++; ++ if (i == rx_ring->count) ++ i = 0; ++ buffer_info = &rx_ring->buffer_info[i]; ++ } ++ ++ if (rx_ring->next_to_use != i) { ++ rx_ring->next_to_use = i; ++ if (i-- == 0) ++ i = (rx_ring->count - 1); ++ ++ /* Force memory writes to complete before letting h/w ++ * know there are new descriptors to fetch. (Only ++ * applicable for weak-ordered memory model archs, ++ * such as IA-64). */ ++ wmb(); ++ writel(i, adapter->hw.hw_addr + rx_ring->tail); ++ } ++} ++ ++/** ++ * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split ++ * @adapter: address of board private structure ++ **/ ++static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter, ++ int cleaned_count) ++{ ++ struct net_device *netdev = adapter->netdev; ++ struct pci_dev *pdev = adapter->pdev; ++ union e1000_rx_desc_packet_split *rx_desc; ++ struct e1000_ring *rx_ring = adapter->rx_ring; ++ struct e1000_buffer *buffer_info; ++ struct e1000_ps_page *ps_page; ++ struct sk_buff *skb; ++ unsigned int i, j; ++ ++ i = rx_ring->next_to_use; ++ buffer_info = &rx_ring->buffer_info[i]; ++ ++ while (cleaned_count--) { ++ rx_desc = E1000_RX_DESC_PS(*rx_ring, i); ++ ++ for (j = 0; j < PS_PAGE_BUFFERS; j++) { ++ ps_page = &rx_ring->ps_pages[(i * PS_PAGE_BUFFERS) ++ + j]; ++ if (j < adapter->rx_ps_pages) { ++ if (!ps_page->page) { ++ ps_page->page = alloc_page(GFP_ATOMIC); ++ if (!ps_page->page) { ++ adapter->alloc_rx_buff_failed++; ++ goto no_buffers; ++ } ++ ps_page->dma = pci_map_page(pdev, ++ ps_page->page, ++ 0, PAGE_SIZE, ++ PCI_DMA_FROMDEVICE); ++ } ++ /* ++ * Refresh the desc even if buffer_addrs ++ * didn't change because each write-back ++ * erases this info. ++ */ ++ rx_desc->read.buffer_addr[j+1] = ++ cpu_to_le64(ps_page->dma); ++ } else { ++ rx_desc->read.buffer_addr[j+1] = ~0; ++ } ++ } ++ ++ skb = netdev_alloc_skb(netdev, ++ adapter->rx_ps_bsize0 + NET_IP_ALIGN); ++ ++ if (!skb) { ++ adapter->alloc_rx_buff_failed++; ++ break; ++ } ++ ++ /* Make buffer alignment 2 beyond a 16 byte boundary ++ * this will result in a 16 byte aligned IP header after ++ * the 14 byte MAC header is removed ++ */ ++ skb_reserve(skb, NET_IP_ALIGN); ++ ++ buffer_info->skb = skb; ++ buffer_info->dma = pci_map_single(pdev, skb->data, ++ adapter->rx_ps_bsize0, ++ PCI_DMA_FROMDEVICE); ++ ++ rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma); ++ ++ i++; ++ if (i == rx_ring->count) ++ i = 0; ++ buffer_info = &rx_ring->buffer_info[i]; ++ } ++ ++no_buffers: ++ if (rx_ring->next_to_use != i) { ++ rx_ring->next_to_use = i; ++ ++ if (!(i--)) ++ i = (rx_ring->count - 1); ++ ++ /* Force memory writes to complete before letting h/w ++ * know there are new descriptors to fetch. (Only ++ * applicable for weak-ordered memory model archs, ++ * such as IA-64). */ ++ wmb(); ++ /* Hardware increments by 16 bytes, but packet split ++ * descriptors are 32 bytes...so we increment tail ++ * twice as much. ++ */ ++ writel(i<<1, adapter->hw.hw_addr + rx_ring->tail); ++ } ++} ++ ++/** ++ * e1000_alloc_rx_buffers_jumbo - Replace used jumbo receive buffers ++ * ++ * @adapter: address of board private structure ++ * @cleaned_count: number of buffers to allocate this pass ++ **/ ++static void e1000_alloc_rx_buffers_jumbo(struct e1000_adapter *adapter, ++ int cleaned_count) ++{ ++ struct net_device *netdev = adapter->netdev; ++ struct pci_dev *pdev = adapter->pdev; ++ struct e1000_ring *rx_ring = adapter->rx_ring; ++ struct e1000_rx_desc *rx_desc; ++ struct e1000_buffer *buffer_info; ++ struct sk_buff *skb; ++ unsigned int i; ++ unsigned int bufsz = 256 - ++ 16 /*for skb_reserve */ - ++ NET_IP_ALIGN; ++ ++ i = rx_ring->next_to_use; ++ buffer_info = &rx_ring->buffer_info[i]; ++ ++ while (cleaned_count--) { ++ skb = buffer_info->skb; ++ if (skb) { ++ skb_trim(skb, 0); ++ goto check_page; ++ } ++ ++ skb = netdev_alloc_skb(netdev, bufsz); ++ if (!skb) { ++ /* Better luck next round */ ++ adapter->alloc_rx_buff_failed++; ++ break; ++ } ++ ++ /* Make buffer alignment 2 beyond a 16 byte boundary ++ * this will result in a 16 byte aligned IP header after ++ * the 14 byte MAC header is removed ++ */ ++ skb_reserve(skb, NET_IP_ALIGN); ++ ++ buffer_info->skb = skb; ++check_page: ++ /* allocate a new page if necessary */ ++ if (!buffer_info->page) { ++ buffer_info->page = alloc_page(GFP_ATOMIC); ++ if (!buffer_info->page) { ++ adapter->alloc_rx_buff_failed++; ++ break; ++ } ++ } ++ ++ if (!buffer_info->dma) ++ buffer_info->dma = pci_map_page(pdev, ++ buffer_info->page, 0, ++ PAGE_SIZE, ++ PCI_DMA_FROMDEVICE); ++ ++ rx_desc = E1000_RX_DESC(*rx_ring, i); ++ rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); ++ ++ i++; ++ if (i == rx_ring->count) ++ i = 0; ++ buffer_info = &rx_ring->buffer_info[i]; ++ } ++ ++ if (rx_ring->next_to_use != i) { ++ rx_ring->next_to_use = i; ++ if (i-- == 0) ++ i = (rx_ring->count - 1); ++ ++ /* Force memory writes to complete before letting h/w ++ * know there are new descriptors to fetch. (Only ++ * applicable for weak-ordered memory model archs, ++ * such as IA-64). */ ++ wmb(); ++ writel(i, adapter->hw.hw_addr + rx_ring->tail); ++ } ++} ++ ++/** ++ * e1000_clean_rx_irq - Send received data up the network stack; legacy ++ * @adapter: board private structure ++ * ++ * the return value indicates whether actual cleaning was done, there ++ * is no guarantee that everything was cleaned ++ **/ ++static bool e1000_clean_rx_irq(struct e1000_adapter *adapter, ++ int *work_done, int work_to_do) ++{ ++ struct net_device *netdev = adapter->netdev; ++ struct pci_dev *pdev = adapter->pdev; ++ struct e1000_ring *rx_ring = adapter->rx_ring; ++ struct e1000_rx_desc *rx_desc, *next_rxd; ++ struct e1000_buffer *buffer_info, *next_buffer; ++ u32 length; ++ unsigned int i; ++ int cleaned_count = 0; ++ bool cleaned = 0; ++ unsigned int total_rx_bytes = 0, total_rx_packets = 0; ++ ++ i = rx_ring->next_to_clean; ++ rx_desc = E1000_RX_DESC(*rx_ring, i); ++ buffer_info = &rx_ring->buffer_info[i]; ++ ++ while (rx_desc->status & E1000_RXD_STAT_DD) { ++ struct sk_buff *skb; ++ u8 status; ++ ++ if (*work_done >= work_to_do) ++ break; ++ (*work_done)++; ++ ++ status = rx_desc->status; ++ skb = buffer_info->skb; ++ buffer_info->skb = NULL; ++ ++ prefetch(skb->data - NET_IP_ALIGN); ++ ++ i++; ++ if (i == rx_ring->count) ++ i = 0; ++ next_rxd = E1000_RX_DESC(*rx_ring, i); ++ prefetch(next_rxd); ++ ++ next_buffer = &rx_ring->buffer_info[i]; ++ ++ cleaned = 1; ++ cleaned_count++; ++ pci_unmap_single(pdev, ++ buffer_info->dma, ++ adapter->rx_buffer_len, ++ PCI_DMA_FROMDEVICE); ++ buffer_info->dma = 0; ++ ++ length = le16_to_cpu(rx_desc->length); ++ ++ /* !EOP means multiple descriptors were used to store a single ++ * packet, also make sure the frame isn't just CRC only */ ++ if (!(status & E1000_RXD_STAT_EOP) || (length <= 4)) { ++ /* All receives must fit into a single buffer */ ++ ndev_dbg(netdev, "%s: Receive packet consumed " ++ "multiple buffers\n", netdev->name); ++ /* recycle */ ++ buffer_info->skb = skb; ++ goto next_desc; ++ } ++ ++ if (rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { ++ /* recycle */ ++ buffer_info->skb = skb; ++ goto next_desc; ++ } ++ ++ /* adjust length to remove Ethernet CRC */ ++ length -= 4; ++ ++ /* probably a little skewed due to removing CRC */ ++ total_rx_bytes += length; ++ total_rx_packets++; ++ ++ /* code added for copybreak, this should improve ++ * performance for small packets with large amounts ++ * of reassembly being done in the stack */ ++ if (length < copybreak) { ++ struct sk_buff *new_skb = ++ netdev_alloc_skb(netdev, length + NET_IP_ALIGN); ++ if (new_skb) { ++ skb_reserve(new_skb, NET_IP_ALIGN); ++ memcpy(new_skb->data - NET_IP_ALIGN, ++ skb->data - NET_IP_ALIGN, ++ length + NET_IP_ALIGN); ++ /* save the skb in buffer_info as good */ ++ buffer_info->skb = skb; ++ skb = new_skb; ++ } ++ /* else just continue with the old one */ ++ } ++ /* end copybreak code */ ++ skb_put(skb, length); ++ ++ /* Receive Checksum Offload */ ++ e1000_rx_checksum(adapter, ++ (u32)(status) | ++ ((u32)(rx_desc->errors) << 24), ++ le16_to_cpu(rx_desc->csum), skb); ++ ++ e1000_receive_skb(adapter, netdev, skb,status,rx_desc->special); ++ ++next_desc: ++ rx_desc->status = 0; ++ ++ /* return some buffers to hardware, one at a time is too slow */ ++ if (cleaned_count >= E1000_RX_BUFFER_WRITE) { ++ adapter->alloc_rx_buf(adapter, cleaned_count); ++ cleaned_count = 0; ++ } ++ ++ /* use prefetched values */ ++ rx_desc = next_rxd; ++ buffer_info = next_buffer; ++ } ++ rx_ring->next_to_clean = i; ++ ++ cleaned_count = e1000_desc_unused(rx_ring); ++ if (cleaned_count) ++ adapter->alloc_rx_buf(adapter, cleaned_count); ++ ++ adapter->total_rx_packets += total_rx_packets; ++ adapter->total_rx_bytes += total_rx_bytes; ++ return cleaned; ++} ++ ++static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb, ++ u16 length) ++{ ++ bi->page = NULL; ++ skb->len += length; ++ skb->data_len += length; ++ skb->truesize += length; ++} ++ ++static void e1000_put_txbuf(struct e1000_adapter *adapter, ++ struct e1000_buffer *buffer_info) ++{ ++ if (buffer_info->dma) { ++ pci_unmap_page(adapter->pdev, buffer_info->dma, ++ buffer_info->length, PCI_DMA_TODEVICE); ++ buffer_info->dma = 0; ++ } ++ if (buffer_info->skb) { ++ dev_kfree_skb_any(buffer_info->skb); ++ buffer_info->skb = NULL; ++ } ++} ++ ++static void e1000_print_tx_hang(struct e1000_adapter *adapter) ++{ ++ struct e1000_ring *tx_ring = adapter->tx_ring; ++ unsigned int i = tx_ring->next_to_clean; ++ unsigned int eop = tx_ring->buffer_info[i].next_to_watch; ++ struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop); ++ struct net_device *netdev = adapter->netdev; ++ ++ /* detected Tx unit hang */ ++ ndev_err(netdev, ++ "Detected Tx Unit Hang:\n" ++ " TDH <%x>\n" ++ " TDT <%x>\n" ++ " next_to_use <%x>\n" ++ " next_to_clean <%x>\n" ++ "buffer_info[next_to_clean]:\n" ++ " time_stamp <%lx>\n" ++ " next_to_watch <%x>\n" ++ " jiffies <%lx>\n" ++ " next_to_watch.status <%x>\n", ++ readl(adapter->hw.hw_addr + tx_ring->head), ++ readl(adapter->hw.hw_addr + tx_ring->tail), ++ tx_ring->next_to_use, ++ tx_ring->next_to_clean, ++ tx_ring->buffer_info[eop].time_stamp, ++ eop, ++ jiffies, ++ eop_desc->upper.fields.status); ++} ++ ++/** ++ * e1000_clean_tx_irq - Reclaim resources after transmit completes ++ * @adapter: board private structure ++ * ++ * the return value indicates whether actual cleaning was done, there ++ * is no guarantee that everything was cleaned ++ **/ ++static bool e1000_clean_tx_irq(struct e1000_adapter *adapter) ++{ ++ struct net_device *netdev = adapter->netdev; ++ struct e1000_hw *hw = &adapter->hw; ++ struct e1000_ring *tx_ring = adapter->tx_ring; ++ struct e1000_tx_desc *tx_desc, *eop_desc; ++ struct e1000_buffer *buffer_info; ++ unsigned int i, eop; ++ unsigned int count = 0; ++ bool cleaned = 0; ++ unsigned int total_tx_bytes = 0, total_tx_packets = 0; ++ ++ i = tx_ring->next_to_clean; ++ eop = tx_ring->buffer_info[i].next_to_watch; ++ eop_desc = E1000_TX_DESC(*tx_ring, eop); ++ ++ while (eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) { ++ for (cleaned = 0; !cleaned; ) { ++ tx_desc = E1000_TX_DESC(*tx_ring, i); ++ buffer_info = &tx_ring->buffer_info[i]; ++ cleaned = (i == eop); ++ ++ if (cleaned) { ++ struct sk_buff *skb = buffer_info->skb; ++ unsigned int segs, bytecount; ++ segs = skb_shinfo(skb)->gso_segs ?: 1; ++ /* multiply data chunks by size of headers */ ++ bytecount = ((segs - 1) * skb_headlen(skb)) + ++ skb->len; ++ total_tx_packets += segs; ++ total_tx_bytes += bytecount; ++ } ++ ++ e1000_put_txbuf(adapter, buffer_info); ++ tx_desc->upper.data = 0; ++ ++ i++; ++ if (i == tx_ring->count) ++ i = 0; ++ } ++ ++ eop = tx_ring->buffer_info[i].next_to_watch; ++ eop_desc = E1000_TX_DESC(*tx_ring, eop); ++#define E1000_TX_WEIGHT 64 ++ /* weight of a sort for tx, to avoid endless transmit cleanup */ ++ if (count++ == E1000_TX_WEIGHT) ++ break; ++ } ++ ++ tx_ring->next_to_clean = i; ++ ++#define TX_WAKE_THRESHOLD 32 ++ if (cleaned && netif_carrier_ok(netdev) && ++ e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) { ++ /* Make sure that anybody stopping the queue after this ++ * sees the new next_to_clean. ++ */ ++ smp_mb(); ++ ++ if (netif_queue_stopped(netdev) && ++ !(test_bit(__E1000_DOWN, &adapter->state))) { ++ netif_wake_queue(netdev); ++ ++adapter->restart_queue; ++ } ++ } ++ ++ if (adapter->detect_tx_hung) { ++ /* Detect a transmit hang in hardware, this serializes the ++ * check with the clearing of time_stamp and movement of i */ ++ adapter->detect_tx_hung = 0; ++ if (tx_ring->buffer_info[eop].dma && ++ time_after(jiffies, tx_ring->buffer_info[eop].time_stamp ++ + (adapter->tx_timeout_factor * HZ)) ++ && !(er32(STATUS) & ++ E1000_STATUS_TXOFF)) { ++ e1000_print_tx_hang(adapter); ++ netif_stop_queue(netdev); ++ } ++ } ++ adapter->total_tx_bytes += total_tx_bytes; ++ adapter->total_tx_packets += total_tx_packets; ++ return cleaned; ++} ++ ++/** ++ * e1000_clean_rx_irq_jumbo - Send received data up the network stack; legacy ++ * @adapter: board private structure ++ * ++ * the return value indicates whether actual cleaning was done, there ++ * is no guarantee that everything was cleaned ++ **/ ++static bool e1000_clean_rx_irq_jumbo(struct e1000_adapter *adapter, ++ int *work_done, int work_to_do) ++{ ++ struct net_device *netdev = adapter->netdev; ++ struct pci_dev *pdev = adapter->pdev; ++ struct e1000_ring *rx_ring = adapter->rx_ring; ++ struct e1000_rx_desc *rx_desc, *next_rxd; ++ struct e1000_buffer *buffer_info, *next_buffer; ++ u32 length; ++ unsigned int i; ++ int cleaned_count = 0; ++ bool cleaned = 0; ++ unsigned int total_rx_bytes = 0, total_rx_packets = 0; ++ ++ i = rx_ring->next_to_clean; ++ rx_desc = E1000_RX_DESC(*rx_ring, i); ++ buffer_info = &rx_ring->buffer_info[i]; ++ ++ while (rx_desc->status & E1000_RXD_STAT_DD) { ++ struct sk_buff *skb; ++ u8 status; ++ ++ if (*work_done >= work_to_do) ++ break; ++ (*work_done)++; ++ ++ status = rx_desc->status; ++ skb = buffer_info->skb; ++ buffer_info->skb = NULL; ++ ++ i++; ++ if (i == rx_ring->count) ++ i = 0; ++ next_rxd = E1000_RX_DESC(*rx_ring, i); ++ prefetch(next_rxd); ++ ++ next_buffer = &rx_ring->buffer_info[i]; ++ ++ cleaned = 1; ++ cleaned_count++; ++ pci_unmap_page(pdev, ++ buffer_info->dma, ++ PAGE_SIZE, ++ PCI_DMA_FROMDEVICE); ++ buffer_info->dma = 0; ++ ++ length = le16_to_cpu(rx_desc->length); ++ ++ /* errors is only valid for DD + EOP descriptors */ ++ if ((status & E1000_RXD_STAT_EOP) && ++ (rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK)) { ++ /* recycle both page and skb */ ++ buffer_info->skb = skb; ++ /* an error means any chain goes out the window too */ ++ if (rx_ring->rx_skb_top) ++ dev_kfree_skb(rx_ring->rx_skb_top); ++ rx_ring->rx_skb_top = NULL; ++ goto next_desc; ++ } ++ ++#define rxtop rx_ring->rx_skb_top ++ if (!(status & E1000_RXD_STAT_EOP)) { ++ /* this descriptor is only the beginning (or middle) */ ++ if (!rxtop) { ++ /* this is the beginning of a chain */ ++ rxtop = skb; ++ skb_fill_page_desc(rxtop, 0, buffer_info->page, ++ 0, length); ++ } else { ++ /* this is the middle of a chain */ ++ skb_fill_page_desc(rxtop, ++ skb_shinfo(rxtop)->nr_frags, ++ buffer_info->page, 0, ++ length); ++ /* re-use the skb, only consumed the page */ ++ buffer_info->skb = skb; ++ } ++ e1000_consume_page(buffer_info, rxtop, length); ++ goto next_desc; ++ } else { ++ if (rxtop) { ++ /* end of the chain */ ++ skb_fill_page_desc(rxtop, ++ skb_shinfo(rxtop)->nr_frags, ++ buffer_info->page, 0, length); ++ /* re-use the current skb, we only consumed the ++ * page */ ++ buffer_info->skb = skb; ++ skb = rxtop; ++ rxtop = NULL; ++ e1000_consume_page(buffer_info, skb, length); ++ } else { ++ /* no chain, got EOP, this buf is the packet ++ * copybreak to save the put_page/alloc_page */ ++ if (length <= copybreak && ++ skb_tailroom(skb) >= length) { ++ u8 *vaddr; ++ vaddr = kmap_atomic(buffer_info->page, ++ KM_SKB_DATA_SOFTIRQ); ++ memcpy(skb_tail_pointer(skb), ++ vaddr, length); ++ kunmap_atomic(vaddr, ++ KM_SKB_DATA_SOFTIRQ); ++ /* re-use the page, so don't erase ++ * buffer_info->page */ ++ skb_put(skb, length); ++ } else { ++ skb_fill_page_desc(skb, 0, ++ buffer_info->page, 0, ++ length); ++ e1000_consume_page(buffer_info, skb, ++ length); ++ } ++ } ++ } ++ ++ /* Receive Checksum Offload XXX recompute due to CRC strip? */ ++ e1000_rx_checksum(adapter, ++ (u32)(status) | ++ ((u32)(rx_desc->errors) << 24), ++ le16_to_cpu(rx_desc->csum), skb); ++ ++ pskb_trim(skb, skb->len - 4); ++ ++ /* probably a little skewed due to removing CRC */ ++ total_rx_bytes += skb->len; ++ total_rx_packets++; ++ ++ /* eth type trans needs skb->data to point to something */ ++ if (!pskb_may_pull(skb, ETH_HLEN)) { ++ ndev_err(netdev, "__pskb_pull_tail failed.\n"); ++ dev_kfree_skb(skb); ++ goto next_desc; ++ } ++ ++ e1000_receive_skb(adapter, netdev, skb,status,rx_desc->special); ++ ++next_desc: ++ rx_desc->status = 0; ++ ++ /* return some buffers to hardware, one at a time is too slow */ ++ if (cleaned_count >= E1000_RX_BUFFER_WRITE) { ++ adapter->alloc_rx_buf(adapter, cleaned_count); ++ cleaned_count = 0; ++ } ++ ++ /* use prefetched values */ ++ rx_desc = next_rxd; ++ buffer_info = next_buffer; ++ } ++ rx_ring->next_to_clean = i; ++ ++ cleaned_count = e1000_desc_unused(rx_ring); ++ if (cleaned_count) ++ adapter->alloc_rx_buf(adapter, cleaned_count); ++ ++ adapter->total_rx_packets += total_rx_packets; ++ adapter->total_rx_bytes += total_rx_bytes; ++ return cleaned; ++} ++ ++/** ++ * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split ++ * @adapter: board private structure ++ * ++ * the return value indicates whether actual cleaning was done, there ++ * is no guarantee that everything was cleaned ++ **/ ++static bool e1000_clean_rx_irq_ps(struct e1000_adapter *adapter, ++ int *work_done, int work_to_do) ++{ ++ union e1000_rx_desc_packet_split *rx_desc, *next_rxd; ++ struct net_device *netdev = adapter->netdev; ++ struct pci_dev *pdev = adapter->pdev; ++ struct e1000_ring *rx_ring = adapter->rx_ring; ++ struct e1000_buffer *buffer_info, *next_buffer; ++ struct e1000_ps_page *ps_page; ++ struct sk_buff *skb; ++ unsigned int i, j; ++ u32 length, staterr; ++ int cleaned_count = 0; ++ bool cleaned = 0; ++ unsigned int total_rx_bytes = 0, total_rx_packets = 0; ++ ++ i = rx_ring->next_to_clean; ++ rx_desc = E1000_RX_DESC_PS(*rx_ring, i); ++ staterr = le32_to_cpu(rx_desc->wb.middle.status_error); ++ buffer_info = &rx_ring->buffer_info[i]; ++ ++ while (staterr & E1000_RXD_STAT_DD) { ++ if (*work_done >= work_to_do) ++ break; ++ (*work_done)++; ++ skb = buffer_info->skb; ++ ++ /* in the packet split case this is header only */ ++ prefetch(skb->data - NET_IP_ALIGN); ++ ++ i++; ++ if (i == rx_ring->count) ++ i = 0; ++ next_rxd = E1000_RX_DESC_PS(*rx_ring, i); ++ prefetch(next_rxd); ++ ++ next_buffer = &rx_ring->buffer_info[i]; ++ ++ cleaned = 1; ++ cleaned_count++; ++ pci_unmap_single(pdev, buffer_info->dma, ++ adapter->rx_ps_bsize0, ++ PCI_DMA_FROMDEVICE); ++ buffer_info->dma = 0; ++ ++ if (!(staterr & E1000_RXD_STAT_EOP)) { ++ ndev_dbg(netdev, "%s: Packet Split buffers didn't pick " ++ "up the full packet\n", netdev->name); ++ dev_kfree_skb_irq(skb); ++ goto next_desc; ++ } ++ ++ if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) { ++ dev_kfree_skb_irq(skb); ++ goto next_desc; ++ } ++ ++ length = le16_to_cpu(rx_desc->wb.middle.length0); ++ ++ if (!length) { ++ ndev_dbg(netdev, "%s: Last part of the packet spanning" ++ " multiple descriptors\n", netdev->name); ++ dev_kfree_skb_irq(skb); ++ goto next_desc; ++ } ++ ++ /* Good Receive */ ++ skb_put(skb, length); ++ ++ { ++ /* this looks ugly, but it seems compiler issues make it ++ more efficient than reusing j */ ++ int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]); ++ ++ /* page alloc/put takes too long and effects small packet ++ * throughput, so unsplit small packets and save the alloc/put*/ ++ if (l1 && (l1 <= copybreak) && ++ ((length + l1) <= adapter->rx_ps_bsize0)) { ++ u8 *vaddr; ++ ++ ps_page = &rx_ring->ps_pages[i * PS_PAGE_BUFFERS]; ++ ++ /* there is no documentation about how to call ++ * kmap_atomic, so we can't hold the mapping ++ * very long */ ++ pci_dma_sync_single_for_cpu(pdev, ps_page->dma, ++ PAGE_SIZE, PCI_DMA_FROMDEVICE); ++ vaddr = kmap_atomic(ps_page->page, KM_SKB_DATA_SOFTIRQ); ++ memcpy(skb_tail_pointer(skb), vaddr, l1); ++ kunmap_atomic(vaddr, KM_SKB_DATA_SOFTIRQ); ++ pci_dma_sync_single_for_device(pdev, ps_page->dma, ++ PAGE_SIZE, PCI_DMA_FROMDEVICE); ++ /* remove the CRC */ ++ l1 -= 4; ++ skb_put(skb, l1); ++ goto copydone; ++ } /* if */ ++ } ++ ++ for (j = 0; j < PS_PAGE_BUFFERS; j++) { ++ length = le16_to_cpu(rx_desc->wb.upper.length[j]); ++ if (!length) ++ break; ++ ++ ps_page = &rx_ring->ps_pages[(i * PS_PAGE_BUFFERS) + j]; ++ pci_unmap_page(pdev, ps_page->dma, PAGE_SIZE, ++ PCI_DMA_FROMDEVICE); ++ ps_page->dma = 0; ++ skb_fill_page_desc(skb, j, ps_page->page, 0, length); ++ ps_page->page = NULL; ++ skb->len += length; ++ skb->data_len += length; ++ skb->truesize += length; ++ } ++ ++ /* strip the ethernet crc, problem is we're using pages now so ++ * this whole operation can get a little cpu intensive */ ++ pskb_trim(skb, skb->len - 4); ++ ++copydone: ++ total_rx_bytes += skb->len; ++ total_rx_packets++; ++ ++ e1000_rx_checksum(adapter, staterr, le16_to_cpu( ++ rx_desc->wb.lower.hi_dword.csum_ip.csum), skb); ++ ++ if (rx_desc->wb.upper.header_status & ++ cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)) ++ adapter->rx_hdr_split++; ++ ++ e1000_receive_skb(adapter, netdev, skb, ++ staterr, rx_desc->wb.middle.vlan); ++ ++next_desc: ++ rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF); ++ buffer_info->skb = NULL; ++ ++ /* return some buffers to hardware, one at a time is too slow */ ++ if (cleaned_count >= E1000_RX_BUFFER_WRITE) { ++ adapter->alloc_rx_buf(adapter, cleaned_count); ++ cleaned_count = 0; ++ } ++ ++ /* use prefetched values */ ++ rx_desc = next_rxd; ++ buffer_info = next_buffer; ++ ++ staterr = le32_to_cpu(rx_desc->wb.middle.status_error); ++ } ++ rx_ring->next_to_clean = i; ++ ++ cleaned_count = e1000_desc_unused(rx_ring); ++ if (cleaned_count) ++ adapter->alloc_rx_buf(adapter, cleaned_count); ++ ++ adapter->total_rx_packets += total_rx_packets; ++ adapter->total_rx_bytes += total_rx_bytes; ++ return cleaned; ++} ++ ++/** ++ * e1000_clean_rx_ring - Free Rx Buffers per Queue ++ * @adapter: board private structure ++ **/ ++static void e1000_clean_rx_ring(struct e1000_adapter *adapter) ++{ ++ struct e1000_ring *rx_ring = adapter->rx_ring; ++ struct e1000_buffer *buffer_info; ++ struct e1000_ps_page *ps_page; ++ struct pci_dev *pdev = adapter->pdev; ++ unsigned long size; ++ unsigned int i, j; ++ ++ /* Free all the Rx ring sk_buffs */ ++ for (i = 0; i < rx_ring->count; i++) { ++ buffer_info = &rx_ring->buffer_info[i]; ++ if (buffer_info->dma) { ++ if (adapter->clean_rx == e1000_clean_rx_irq) ++ pci_unmap_single(pdev, buffer_info->dma, ++ adapter->rx_buffer_len, ++ PCI_DMA_FROMDEVICE); ++ else if (adapter->clean_rx == e1000_clean_rx_irq_jumbo) ++ pci_unmap_page(pdev, buffer_info->dma, ++ PAGE_SIZE, PCI_DMA_FROMDEVICE); ++ else if (adapter->clean_rx == e1000_clean_rx_irq_ps) ++ pci_unmap_single(pdev, buffer_info->dma, ++ adapter->rx_ps_bsize0, ++ PCI_DMA_FROMDEVICE); ++ buffer_info->dma = 0; ++ } ++ ++ if (buffer_info->page) { ++ put_page(buffer_info->page); ++ buffer_info->page = NULL; ++ } ++ ++ if (buffer_info->skb) { ++ dev_kfree_skb(buffer_info->skb); ++ buffer_info->skb = NULL; ++ } ++ ++ for (j = 0; j < PS_PAGE_BUFFERS; j++) { ++ ps_page = &rx_ring->ps_pages[(i * PS_PAGE_BUFFERS) ++ + j]; ++ if (!ps_page->page) ++ break; ++ pci_unmap_page(pdev, ps_page->dma, PAGE_SIZE, ++ PCI_DMA_FROMDEVICE); ++ ps_page->dma = 0; ++ put_page(ps_page->page); ++ ps_page->page = NULL; ++ } ++ } ++ ++ /* there also may be some cached data from a chained receive */ ++ if (rx_ring->rx_skb_top) { ++ dev_kfree_skb(rx_ring->rx_skb_top); ++ rx_ring->rx_skb_top = NULL; ++ } ++ ++ size = sizeof(struct e1000_buffer) * rx_ring->count; ++ memset(rx_ring->buffer_info, 0, size); ++ size = sizeof(struct e1000_ps_page) ++ * (rx_ring->count * PS_PAGE_BUFFERS); ++ memset(rx_ring->ps_pages, 0, size); ++ ++ /* Zero out the descriptor ring */ ++ memset(rx_ring->desc, 0, rx_ring->size); ++ ++ rx_ring->next_to_clean = 0; ++ rx_ring->next_to_use = 0; ++ ++ writel(0, adapter->hw.hw_addr + rx_ring->head); ++ writel(0, adapter->hw.hw_addr + rx_ring->tail); ++} ++ ++/** ++ * e1000_intr_msi - Interrupt Handler ++ * @irq: interrupt number ++ * @data: pointer to a network interface device structure ++ **/ ++static irqreturn_t e1000_intr_msi(int irq, void *data) ++{ ++ struct net_device *netdev = data; ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ struct e1000_hw *hw = &adapter->hw; ++ u32 icr = er32(ICR); ++ ++ /* read ICR disables interrupts using IAM, so keep up with our ++ * enable/disable accounting */ ++ atomic_inc(&adapter->irq_sem); ++ ++ if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { ++ hw->mac.get_link_status = 1; ++ /* ICH8 workaround-- Call gig speed drop workaround on cable ++ * disconnect (LSC) before accessing any PHY registers */ ++ if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && ++ (!(er32(STATUS) & E1000_STATUS_LU))) ++ e1000_gig_downshift_workaround_ich8lan(hw); ++ ++ /* 80003ES2LAN workaround-- For packet buffer work-around on ++ * link down event; disable receives here in the ISR and reset ++ * adapter in watchdog */ ++ if (netif_carrier_ok(netdev) && ++ adapter->flags & FLAG_RX_NEEDS_RESTART) { ++ /* disable receives */ ++ u32 rctl = er32(RCTL); ++ ew32(RCTL, rctl & ~E1000_RCTL_EN); ++ } ++ /* guard against interrupt when we're going down */ ++ if (!test_bit(__E1000_DOWN, &adapter->state)) ++ mod_timer(&adapter->watchdog_timer, jiffies + 1); ++ } ++ ++ if (netif_rx_schedule_prep(netdev)) { ++ adapter->total_tx_bytes = 0; ++ adapter->total_tx_packets = 0; ++ adapter->total_rx_bytes = 0; ++ adapter->total_rx_packets = 0; ++ __netif_rx_schedule(netdev); ++ } else { ++ atomic_dec(&adapter->irq_sem); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++/** ++ * e1000_intr - Interrupt Handler ++ * @irq: interrupt number ++ * @data: pointer to a network interface device structure ++ **/ ++static irqreturn_t e1000_intr(int irq, void *data) ++{ ++ struct net_device *netdev = data; ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ struct e1000_hw *hw = &adapter->hw; ++ ++ u32 rctl, icr = er32(ICR); ++ if (!icr) ++ return IRQ_NONE; /* Not our interrupt */ ++ ++ /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is ++ * not set, then the adapter didn't send an interrupt */ ++ if (!(icr & E1000_ICR_INT_ASSERTED)) ++ return IRQ_NONE; ++ ++ /* Interrupt Auto-Mask...upon reading ICR, ++ * interrupts are masked. No need for the ++ * IMC write, but it does mean we should ++ * account for it ASAP. */ ++ atomic_inc(&adapter->irq_sem); ++ ++ if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { ++ hw->mac.get_link_status = 1; ++ /* ICH8 workaround-- Call gig speed drop workaround on cable ++ * disconnect (LSC) before accessing any PHY registers */ ++ if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && ++ (!(er32(STATUS) & E1000_STATUS_LU))) ++ e1000_gig_downshift_workaround_ich8lan(hw); ++ ++ /* 80003ES2LAN workaround-- ++ * For packet buffer work-around on link down event; ++ * disable receives here in the ISR and ++ * reset adapter in watchdog ++ */ ++ if (netif_carrier_ok(netdev) && ++ (adapter->flags & FLAG_RX_NEEDS_RESTART)) { ++ /* disable receives */ ++ rctl = er32(RCTL); ++ ew32(RCTL, rctl & ~E1000_RCTL_EN); ++ } ++ /* guard against interrupt when we're going down */ ++ if (!test_bit(__E1000_DOWN, &adapter->state)) ++ mod_timer(&adapter->watchdog_timer, jiffies + 1); ++ } ++ ++ if (netif_rx_schedule_prep(netdev)) { ++ adapter->total_tx_bytes = 0; ++ adapter->total_tx_packets = 0; ++ adapter->total_rx_bytes = 0; ++ adapter->total_rx_packets = 0; ++ __netif_rx_schedule(netdev); ++ } else { ++ atomic_dec(&adapter->irq_sem); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int e1000_request_irq(struct e1000_adapter *adapter) ++{ ++ struct net_device *netdev = adapter->netdev; ++ void (*handler) = &e1000_intr; ++ int irq_flags = IRQF_SHARED; ++ int err; ++ ++ err = pci_enable_msi(adapter->pdev); ++ if (err) { ++ ndev_warn(netdev, ++ "Unable to allocate MSI interrupt Error: %d\n", err); ++ } else { ++ adapter->flags |= FLAG_MSI_ENABLED; ++ handler = &e1000_intr_msi; ++ irq_flags = 0; ++ } ++ ++ err = request_irq(adapter->pdev->irq, handler, irq_flags, netdev->name, ++ netdev); ++ if (err) { ++ if (adapter->flags & FLAG_MSI_ENABLED) ++ pci_disable_msi(adapter->pdev); ++ ndev_err(netdev, ++ "Unable to allocate interrupt Error: %d\n", err); ++ } ++ ++ return err; ++} ++ ++static void e1000_free_irq(struct e1000_adapter *adapter) ++{ ++ struct net_device *netdev = adapter->netdev; ++ ++ free_irq(adapter->pdev->irq, netdev); ++ if (adapter->flags & FLAG_MSI_ENABLED) { ++ pci_disable_msi(adapter->pdev); ++ adapter->flags &= ~FLAG_MSI_ENABLED; ++ } ++} ++ ++/** ++ * e1000_irq_disable - Mask off interrupt generation on the NIC ++ **/ ++static void e1000_irq_disable(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ ++ atomic_inc(&adapter->irq_sem); ++ ew32(IMC, ~0); ++ e1e_flush(); ++ synchronize_irq(adapter->pdev->irq); ++} ++ ++/** ++ * e1000_irq_enable - Enable default interrupt generation settings ++ **/ ++static void e1000_irq_enable(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ ++ if (atomic_dec_and_test(&adapter->irq_sem)) { ++ ew32(IMS, IMS_ENABLE_MASK); ++ e1e_flush(); ++ } ++} ++ ++/** ++ * e1000_get_hw_control - get control of the h/w from f/w ++ * @adapter: address of board private structure ++ * ++ * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit. ++ * For ASF and Pass Through versions of f/w this means that ++ * the driver is loaded. For AMT version (only with 82573) ++ * of the f/w this means that the network i/f is open. ++ **/ ++static void e1000_get_hw_control(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ u32 ctrl_ext; ++ u32 swsm; ++ ++ /* Let firmware know the driver has taken over */ ++ if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { ++ swsm = er32(SWSM); ++ ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD); ++ } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { ++ ctrl_ext = er32(CTRL_EXT); ++ ew32(CTRL_EXT, ++ ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); ++ } ++} ++ ++/** ++ * e1000_release_hw_control - release control of the h/w to f/w ++ * @adapter: address of board private structure ++ * ++ * e1000_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. ++ * For ASF and Pass Through versions of f/w this means that the ++ * driver is no longer loaded. For AMT version (only with 82573) i ++ * of the f/w this means that the network i/f is closed. ++ * ++ **/ ++static void e1000_release_hw_control(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ u32 ctrl_ext; ++ u32 swsm; ++ ++ /* Let firmware taken over control of h/w */ ++ if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { ++ swsm = er32(SWSM); ++ ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD); ++ } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { ++ ctrl_ext = er32(CTRL_EXT); ++ ew32(CTRL_EXT, ++ ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); ++ } ++} ++ ++static void e1000_release_manageability(struct e1000_adapter *adapter) ++{ ++ if (adapter->flags & FLAG_MNG_PT_ENABLED) { ++ struct e1000_hw *hw = &adapter->hw; ++ ++ u32 manc = er32(MANC); ++ ++ /* re-enable hardware interception of ARP */ ++ manc |= E1000_MANC_ARP_EN; ++ manc &= ~E1000_MANC_EN_MNG2HOST; ++ ++ /* don't explicitly have to mess with MANC2H since ++ * MANC has an enable disable that gates MANC2H */ ++ ew32(MANC, manc); ++ } ++} ++ ++/** ++ * @e1000_alloc_ring - allocate memory for a ring structure ++ **/ ++static int e1000_alloc_ring_dma(struct e1000_adapter *adapter, ++ struct e1000_ring *ring) ++{ ++ struct pci_dev *pdev = adapter->pdev; ++ ++ ring->desc = pci_alloc_consistent(pdev, ring->size, &ring->dma); ++ if (!ring->desc) ++ return -ENOMEM; ++ ++ return 0; ++} ++ ++/** ++ * e1000_setup_tx_resources - allocate Tx resources (Descriptors) ++ * @adapter: board private structure ++ * ++ * Return 0 on success, negative on failure ++ **/ ++int e1000_setup_tx_resources(struct e1000_adapter *adapter) ++{ ++ struct e1000_ring *tx_ring = adapter->tx_ring; ++ int err = -ENOMEM, size; ++ ++ size = sizeof(struct e1000_buffer) * tx_ring->count; ++ tx_ring->buffer_info = vmalloc(size); ++ if (!tx_ring->buffer_info) ++ goto err; ++ memset(tx_ring->buffer_info, 0, size); ++ ++ /* round up to nearest 4K */ ++ tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); ++ tx_ring->size = ALIGN(tx_ring->size, 4096); ++ ++ err = e1000_alloc_ring_dma(adapter, tx_ring); ++ if (err) ++ goto err; ++ ++ tx_ring->next_to_use = 0; ++ tx_ring->next_to_clean = 0; ++ spin_lock_init(&adapter->tx_queue_lock); ++ ++ return 0; ++err: ++ vfree(tx_ring->buffer_info); ++ ndev_err(adapter->netdev, ++ "Unable to allocate memory for the transmit descriptor ring\n"); ++ return err; ++} ++ ++/** ++ * e1000_setup_rx_resources - allocate Rx resources (Descriptors) ++ * @adapter: board private structure ++ * ++ * Returns 0 on success, negative on failure ++ **/ ++int e1000_setup_rx_resources(struct e1000_adapter *adapter) ++{ ++ struct e1000_ring *rx_ring = adapter->rx_ring; ++ int size, desc_len, err = -ENOMEM; ++ ++ size = sizeof(struct e1000_buffer) * rx_ring->count; ++ rx_ring->buffer_info = vmalloc(size); ++ if (!rx_ring->buffer_info) ++ goto err; ++ memset(rx_ring->buffer_info, 0, size); ++ ++ rx_ring->ps_pages = kcalloc(rx_ring->count * PS_PAGE_BUFFERS, ++ sizeof(struct e1000_ps_page), ++ GFP_KERNEL); ++ if (!rx_ring->ps_pages) ++ goto err; ++ ++ desc_len = sizeof(union e1000_rx_desc_packet_split); ++ ++ /* Round up to nearest 4K */ ++ rx_ring->size = rx_ring->count * desc_len; ++ rx_ring->size = ALIGN(rx_ring->size, 4096); ++ ++ err = e1000_alloc_ring_dma(adapter, rx_ring); ++ if (err) ++ goto err; ++ ++ rx_ring->next_to_clean = 0; ++ rx_ring->next_to_use = 0; ++ rx_ring->rx_skb_top = NULL; ++ ++ return 0; ++err: ++ vfree(rx_ring->buffer_info); ++ kfree(rx_ring->ps_pages); ++ ndev_err(adapter->netdev, ++ "Unable to allocate memory for the transmit descriptor ring\n"); ++ return err; ++} ++ ++/** ++ * e1000_clean_tx_ring - Free Tx Buffers ++ * @adapter: board private structure ++ **/ ++static void e1000_clean_tx_ring(struct e1000_adapter *adapter) ++{ ++ struct e1000_ring *tx_ring = adapter->tx_ring; ++ struct e1000_buffer *buffer_info; ++ unsigned long size; ++ unsigned int i; ++ ++ for (i = 0; i < tx_ring->count; i++) { ++ buffer_info = &tx_ring->buffer_info[i]; ++ e1000_put_txbuf(adapter, buffer_info); ++ } ++ ++ size = sizeof(struct e1000_buffer) * tx_ring->count; ++ memset(tx_ring->buffer_info, 0, size); ++ ++ memset(tx_ring->desc, 0, tx_ring->size); ++ ++ tx_ring->next_to_use = 0; ++ tx_ring->next_to_clean = 0; ++ tx_ring->last_tx_tso = 0; ++ ++ writel(0, adapter->hw.hw_addr + tx_ring->head); ++ writel(0, adapter->hw.hw_addr + tx_ring->tail); ++} ++ ++/** ++ * e1000_free_tx_resources - Free Tx Resources per Queue ++ * @adapter: board private structure ++ * ++ * Free all transmit software resources ++ **/ ++void e1000_free_tx_resources(struct e1000_adapter *adapter) ++{ ++ struct pci_dev *pdev = adapter->pdev; ++ struct e1000_ring *tx_ring = adapter->tx_ring; ++ ++ e1000_clean_tx_ring(adapter); ++ ++ vfree(tx_ring->buffer_info); ++ tx_ring->buffer_info = NULL; ++ ++ pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma); ++ tx_ring->desc = NULL; ++} ++ ++/** ++ * e1000_free_rx_resources - Free Rx Resources ++ * @adapter: board private structure ++ * ++ * Free all receive software resources ++ **/ ++ ++void e1000_free_rx_resources(struct e1000_adapter *adapter) ++{ ++ struct pci_dev *pdev = adapter->pdev; ++ struct e1000_ring *rx_ring = adapter->rx_ring; ++ ++ e1000_clean_rx_ring(adapter); ++ ++ vfree(rx_ring->buffer_info); ++ rx_ring->buffer_info = NULL; ++ ++ kfree(rx_ring->ps_pages); ++ rx_ring->ps_pages = NULL; ++ ++ pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); ++ rx_ring->desc = NULL; ++} ++ ++/** ++ * e1000_update_itr - update the dynamic ITR value based on statistics ++ * Stores a new ITR value based on packets and byte ++ * counts during the last interrupt. The advantage of per interrupt ++ * computation is faster updates and more accurate ITR for the current ++ * traffic pattern. Constants in this function were computed ++ * based on theoretical maximum wire speed and thresholds were set based ++ * on testing data as well as attempting to minimize response time ++ * while increasing bulk throughput. ++ * this functionality is controlled by the InterruptThrottleRate module ++ * parameter (see e1000_param.c) ++ * @adapter: pointer to adapter ++ * @itr_setting: current adapter->itr ++ * @packets: the number of packets during this measurement interval ++ * @bytes: the number of bytes during this measurement interval ++ **/ ++static unsigned int e1000_update_itr(struct e1000_adapter *adapter, ++ u16 itr_setting, int packets, ++ int bytes) ++{ ++ unsigned int retval = itr_setting; ++ ++ if (packets == 0) ++ goto update_itr_done; ++ ++ switch (itr_setting) { ++ case lowest_latency: ++ /* handle TSO and jumbo frames */ ++ if (bytes/packets > 8000) ++ retval = bulk_latency; ++ else if ((packets < 5) && (bytes > 512)) { ++ retval = low_latency; ++ } ++ break; ++ case low_latency: /* 50 usec aka 20000 ints/s */ ++ if (bytes > 10000) { ++ /* this if handles the TSO accounting */ ++ if (bytes/packets > 8000) { ++ retval = bulk_latency; ++ } else if ((packets < 10) || ((bytes/packets) > 1200)) { ++ retval = bulk_latency; ++ } else if ((packets > 35)) { ++ retval = lowest_latency; ++ } ++ } else if (bytes/packets > 2000) { ++ retval = bulk_latency; ++ } else if (packets <= 2 && bytes < 512) { ++ retval = lowest_latency; ++ } ++ break; ++ case bulk_latency: /* 250 usec aka 4000 ints/s */ ++ if (bytes > 25000) { ++ if (packets > 35) { ++ retval = low_latency; ++ } ++ } else if (bytes < 6000) { ++ retval = low_latency; ++ } ++ break; ++ } ++ ++update_itr_done: ++ return retval; ++} ++ ++static void e1000_set_itr(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ u16 current_itr; ++ u32 new_itr = adapter->itr; ++ ++ /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ ++ if (adapter->link_speed != SPEED_1000) { ++ current_itr = 0; ++ new_itr = 4000; ++ goto set_itr_now; ++ } ++ ++ adapter->tx_itr = e1000_update_itr(adapter, ++ adapter->tx_itr, ++ adapter->total_tx_packets, ++ adapter->total_tx_bytes); ++ /* conservative mode (itr 3) eliminates the lowest_latency setting */ ++ if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency) ++ adapter->tx_itr = low_latency; ++ ++ adapter->rx_itr = e1000_update_itr(adapter, ++ adapter->rx_itr, ++ adapter->total_rx_packets, ++ adapter->total_rx_bytes); ++ /* conservative mode (itr 3) eliminates the lowest_latency setting */ ++ if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency) ++ adapter->rx_itr = low_latency; ++ ++ current_itr = max(adapter->rx_itr, adapter->tx_itr); ++ ++ switch (current_itr) { ++ /* counts and packets in update_itr are dependent on these numbers */ ++ case lowest_latency: ++ new_itr = 70000; ++ break; ++ case low_latency: ++ new_itr = 20000; /* aka hwitr = ~200 */ ++ break; ++ case bulk_latency: ++ new_itr = 4000; ++ break; ++ default: ++ break; ++ } ++ ++set_itr_now: ++ if (new_itr != adapter->itr) { ++ /* this attempts to bias the interrupt rate towards Bulk ++ * by adding intermediate steps when interrupt rate is ++ * increasing */ ++ new_itr = new_itr > adapter->itr ? ++ min(adapter->itr + (new_itr >> 2), new_itr) : ++ new_itr; ++ adapter->itr = new_itr; ++ ew32(ITR, 1000000000 / (new_itr * 256)); ++ } ++} ++ ++/** ++ * e1000_clean - NAPI Rx polling callback ++ * @adapter: board private structure ++ **/ ++static int e1000_clean(struct net_device *poll_dev, int *budget) ++{ ++ struct e1000_adapter *adapter; ++ int work_to_do = min(*budget, poll_dev->quota); ++ int tx_cleaned = 0, work_done = 0; ++ ++ /* Must NOT use netdev_priv macro here. */ ++ adapter = poll_dev->priv; ++ ++ /* Keep link state information with original netdev */ ++ if (!netif_carrier_ok(poll_dev)) ++ goto quit_polling; ++ ++ /* e1000_clean is called per-cpu. This lock protects ++ * tx_ring from being cleaned by multiple cpus ++ * simultaneously. A failure obtaining the lock means ++ * tx_ring is currently being cleaned anyway. */ ++ if (spin_trylock(&adapter->tx_queue_lock)) { ++ tx_cleaned = e1000_clean_tx_irq(adapter); ++ spin_unlock(&adapter->tx_queue_lock); ++ } ++ ++ adapter->clean_rx(adapter, &work_done, work_to_do); ++ *budget -= work_done; ++ poll_dev->quota -= work_done; ++ ++ /* If no Tx and not enough Rx work done, exit the polling mode */ ++ if ((!tx_cleaned && (work_done == 0)) || ++ !netif_running(poll_dev)) { ++quit_polling: ++ if (adapter->itr_setting & 3) ++ e1000_set_itr(adapter); ++ netif_rx_complete(poll_dev); ++ if (test_bit(__E1000_DOWN, &adapter->state)) ++ atomic_dec(&adapter->irq_sem); ++ else ++ e1000_irq_enable(adapter); ++ return 0; ++ } ++ ++ return 1; ++} ++ ++static void e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ struct e1000_hw *hw = &adapter->hw; ++ u32 vfta, index; ++ ++ /* don't update vlan cookie if already programmed */ ++ if ((adapter->hw.mng_cookie.status & ++ E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && ++ (vid == adapter->mng_vlan_id)) ++ return; ++ /* add VID to filter table */ ++ index = (vid >> 5) & 0x7F; ++ vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); ++ vfta |= (1 << (vid & 0x1F)); ++ e1000_write_vfta(hw, index, vfta); ++} ++ ++static void e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ struct e1000_hw *hw = &adapter->hw; ++ u32 vfta, index; ++ ++ e1000_irq_disable(adapter); ++ vlan_group_set_device(adapter->vlgrp, vid, NULL); ++ e1000_irq_enable(adapter); ++ ++ if ((adapter->hw.mng_cookie.status & ++ E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && ++ (vid == adapter->mng_vlan_id)) { ++ /* release control to f/w */ ++ e1000_release_hw_control(adapter); ++ return; ++ } ++ ++ /* remove VID from filter table */ ++ index = (vid >> 5) & 0x7F; ++ vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); ++ vfta &= ~(1 << (vid & 0x1F)); ++ e1000_write_vfta(hw, index, vfta); ++} ++ ++static void e1000_update_mng_vlan(struct e1000_adapter *adapter) ++{ ++ struct net_device *netdev = adapter->netdev; ++ u16 vid = adapter->hw.mng_cookie.vlan_id; ++ u16 old_vid = adapter->mng_vlan_id; ++ ++ if (!adapter->vlgrp) ++ return; ++ ++ if (!vlan_group_get_device(adapter->vlgrp, vid)) { ++ adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; ++ if (adapter->hw.mng_cookie.status & ++ E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { ++ e1000_vlan_rx_add_vid(netdev, vid); ++ adapter->mng_vlan_id = vid; ++ } ++ ++ if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && ++ (vid != old_vid) && ++ !vlan_group_get_device(adapter->vlgrp, old_vid)) ++ e1000_vlan_rx_kill_vid(netdev, old_vid); ++ } else { ++ adapter->mng_vlan_id = vid; ++ } ++} ++ ++ ++static void e1000_vlan_rx_register(struct net_device *netdev, ++ struct vlan_group *grp) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ struct e1000_hw *hw = &adapter->hw; ++ u32 ctrl, rctl; ++ ++ e1000_irq_disable(adapter); ++ adapter->vlgrp = grp; ++ ++ if (grp) { ++ /* enable VLAN tag insert/strip */ ++ ctrl = er32(CTRL); ++ ctrl |= E1000_CTRL_VME; ++ ew32(CTRL, ctrl); ++ ++ if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { ++ /* enable VLAN receive filtering */ ++ rctl = er32(RCTL); ++ rctl |= E1000_RCTL_VFE; ++ rctl &= ~E1000_RCTL_CFIEN; ++ ew32(RCTL, rctl); ++ e1000_update_mng_vlan(adapter); ++ } ++ } else { ++ /* disable VLAN tag insert/strip */ ++ ctrl = er32(CTRL); ++ ctrl &= ~E1000_CTRL_VME; ++ ew32(CTRL, ctrl); ++ ++ if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { ++ /* disable VLAN filtering */ ++ rctl = er32(RCTL); ++ rctl &= ~E1000_RCTL_VFE; ++ ew32(RCTL, rctl); ++ if (adapter->mng_vlan_id != ++ (u16)E1000_MNG_VLAN_NONE) { ++ e1000_vlan_rx_kill_vid(netdev, ++ adapter->mng_vlan_id); ++ adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; ++ } ++ } ++ } ++ ++ e1000_irq_enable(adapter); ++} ++ ++static void e1000_restore_vlan(struct e1000_adapter *adapter) ++{ ++ u16 vid; ++ ++ e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp); ++ ++ if (!adapter->vlgrp) ++ return; ++ ++ for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) { ++ if (!vlan_group_get_device(adapter->vlgrp, vid)) ++ continue; ++ e1000_vlan_rx_add_vid(adapter->netdev, vid); ++ } ++} ++ ++static void e1000_init_manageability(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ u32 manc, manc2h; ++ ++ if (!(adapter->flags & FLAG_MNG_PT_ENABLED)) ++ return; ++ ++ manc = er32(MANC); ++ ++ /* disable hardware interception of ARP */ ++ manc &= ~(E1000_MANC_ARP_EN); ++ ++ /* enable receiving management packets to the host. this will probably ++ * generate destination unreachable messages from the host OS, but ++ * the packets will be handled on SMBUS */ ++ manc |= E1000_MANC_EN_MNG2HOST; ++ manc2h = er32(MANC2H); ++#define E1000_MNG2HOST_PORT_623 (1 << 5) ++#define E1000_MNG2HOST_PORT_664 (1 << 6) ++ manc2h |= E1000_MNG2HOST_PORT_623; ++ manc2h |= E1000_MNG2HOST_PORT_664; ++ ew32(MANC2H, manc2h); ++ ew32(MANC, manc); ++} ++ ++/** ++ * e1000_configure_tx - Configure 8254x Transmit Unit after Reset ++ * @adapter: board private structure ++ * ++ * Configure the Tx unit of the MAC after a reset. ++ **/ ++static void e1000_configure_tx(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ struct e1000_ring *tx_ring = adapter->tx_ring; ++ u64 tdba; ++ u32 tdlen, tctl, tipg, tarc; ++ u32 ipgr1, ipgr2; ++ ++ /* Setup the HW Tx Head and Tail descriptor pointers */ ++ tdba = tx_ring->dma; ++ tdlen = tx_ring->count * sizeof(struct e1000_tx_desc); ++ ew32(TDBAL, (tdba & DMA_32BIT_MASK)); ++ ew32(TDBAH, (tdba >> 32)); ++ ew32(TDLEN, tdlen); ++ ew32(TDH, 0); ++ ew32(TDT, 0); ++ tx_ring->head = E1000_TDH; ++ tx_ring->tail = E1000_TDT; ++ ++ /* Set the default values for the Tx Inter Packet Gap timer */ ++ tipg = DEFAULT_82543_TIPG_IPGT_COPPER; /* 8 */ ++ ipgr1 = DEFAULT_82543_TIPG_IPGR1; /* 8 */ ++ ipgr2 = DEFAULT_82543_TIPG_IPGR2; /* 6 */ ++ ++ if (adapter->flags & FLAG_TIPG_MEDIUM_FOR_80003ESLAN) ++ ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2; /* 7 */ ++ ++ tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT; ++ tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT; ++ ew32(TIPG, tipg); ++ ++ /* Set the Tx Interrupt Delay register */ ++ ew32(TIDV, adapter->tx_int_delay); ++ /* tx irq moderation */ ++ ew32(TADV, adapter->tx_abs_int_delay); ++ ++ /* Program the Transmit Control Register */ ++ tctl = er32(TCTL); ++ tctl &= ~E1000_TCTL_CT; ++ tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | ++ (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); ++ ++ if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) { ++ tarc = er32(TARC0); ++ /* set the speed mode bit, we'll clear it if we're not at ++ * gigabit link later */ ++#define SPEED_MODE_BIT (1 << 21) ++ tarc |= SPEED_MODE_BIT; ++ ew32(TARC0, tarc); ++ } ++ ++ /* errata: program both queues to unweighted RR */ ++ if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) { ++ tarc = er32(TARC0); ++ tarc |= 1; ++ ew32(TARC0, tarc); ++ tarc = er32(TARC1); ++ tarc |= 1; ++ ew32(TARC1, tarc); ++ } ++ ++ e1000_config_collision_dist(hw); ++ ++ /* Setup Transmit Descriptor Settings for eop descriptor */ ++ adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; ++ ++ /* only set IDE if we are delaying interrupts using the timers */ ++ if (adapter->tx_int_delay) ++ adapter->txd_cmd |= E1000_TXD_CMD_IDE; ++ ++ /* enable Report Status bit */ ++ adapter->txd_cmd |= E1000_TXD_CMD_RS; ++ ++ ew32(TCTL, tctl); ++ ++ adapter->tx_queue_len = adapter->netdev->tx_queue_len; ++} ++ ++/** ++ * e1000_setup_rctl - configure the receive control registers ++ * @adapter: Board private structure ++ **/ ++#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \ ++ (((S) & (PAGE_SIZE - 1)) ? 1 : 0)) ++static void e1000_setup_rctl(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ u32 rctl, rfctl; ++ u32 psrctl = 0; ++ u32 pages = 0; ++ ++ /* Program MC offset vector base */ ++ rctl = er32(RCTL); ++ rctl &= ~(3 << E1000_RCTL_MO_SHIFT); ++ rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | ++ E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | ++ (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); ++ ++ /* Do not Store bad packets */ ++ rctl &= ~E1000_RCTL_SBP; ++ ++ /* Enable Long Packet receive */ ++ if (adapter->netdev->mtu <= ETH_DATA_LEN) ++ rctl &= ~E1000_RCTL_LPE; ++ else ++ rctl |= E1000_RCTL_LPE; ++ ++ /* Setup buffer sizes */ ++ rctl &= ~E1000_RCTL_SZ_4096; ++ rctl |= E1000_RCTL_BSEX; ++ switch (adapter->rx_buffer_len) { ++ case 256: ++ rctl |= E1000_RCTL_SZ_256; ++ rctl &= ~E1000_RCTL_BSEX; ++ break; ++ case 512: ++ rctl |= E1000_RCTL_SZ_512; ++ rctl &= ~E1000_RCTL_BSEX; ++ break; ++ case 1024: ++ rctl |= E1000_RCTL_SZ_1024; ++ rctl &= ~E1000_RCTL_BSEX; ++ break; ++ case 2048: ++ default: ++ rctl |= E1000_RCTL_SZ_2048; ++ rctl &= ~E1000_RCTL_BSEX; ++ break; ++ case 4096: ++ rctl |= E1000_RCTL_SZ_4096; ++ break; ++ case 8192: ++ rctl |= E1000_RCTL_SZ_8192; ++ break; ++ case 16384: ++ rctl |= E1000_RCTL_SZ_16384; ++ break; ++ } ++ ++#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT ++ /* ++ * 82571 and greater support packet-split where the protocol ++ * header is placed in skb->data and the packet data is ++ * placed in pages hanging off of skb_shinfo(skb)->nr_frags. ++ * In the case of a non-split, skb->data is linearly filled, ++ * followed by the page buffers. Therefore, skb->data is ++ * sized to hold the largest protocol header. ++ * ++ * allocations using alloc_page take too long for regular MTU ++ * so only enable packet split for jumbo frames ++ * ++ * Using pages when the page size is greater than 16k wastes ++ * a lot of memory, since we allocate 3 pages at all times ++ * per packet. ++ */ ++ adapter->rx_ps_pages = 0; ++ pages = PAGE_USE_COUNT(adapter->netdev->mtu); ++ if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE)) ++ adapter->rx_ps_pages = pages; ++#endif ++ if (adapter->rx_ps_pages) { ++ /* Configure extra packet-split registers */ ++ rfctl = er32(RFCTL); ++ rfctl |= E1000_RFCTL_EXTEN; ++ /* disable packet split support for IPv6 extension headers, ++ * because some malformed IPv6 headers can hang the RX */ ++ rfctl |= (E1000_RFCTL_IPV6_EX_DIS | ++ E1000_RFCTL_NEW_IPV6_EXT_DIS); ++ ++ ew32(RFCTL, rfctl); ++ ++ /* disable the stripping of CRC because it breaks ++ * BMC firmware connected over SMBUS */ ++ rctl |= E1000_RCTL_DTYP_PS /* | E1000_RCTL_SECRC */; ++ ++ psrctl |= adapter->rx_ps_bsize0 >> ++ E1000_PSRCTL_BSIZE0_SHIFT; ++ ++ switch (adapter->rx_ps_pages) { ++ case 3: ++ psrctl |= PAGE_SIZE << ++ E1000_PSRCTL_BSIZE3_SHIFT; ++ case 2: ++ psrctl |= PAGE_SIZE << ++ E1000_PSRCTL_BSIZE2_SHIFT; ++ case 1: ++ psrctl |= PAGE_SIZE >> ++ E1000_PSRCTL_BSIZE1_SHIFT; ++ break; ++ } ++ ++ ew32(PSRCTL, psrctl); ++ } ++ ++ ew32(RCTL, rctl); ++} ++ ++/** ++ * e1000_configure_rx - Configure Receive Unit after Reset ++ * @adapter: board private structure ++ * ++ * Configure the Rx unit of the MAC after a reset. ++ **/ ++static void e1000_configure_rx(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ struct e1000_ring *rx_ring = adapter->rx_ring; ++ u64 rdba; ++ u32 rdlen, rctl, rxcsum, ctrl_ext; ++ ++ if (adapter->rx_ps_pages) { ++ /* this is a 32 byte descriptor */ ++ rdlen = rx_ring->count * ++ sizeof(union e1000_rx_desc_packet_split); ++ adapter->clean_rx = e1000_clean_rx_irq_ps; ++ adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps; ++ } else if (adapter->netdev->mtu > ETH_FRAME_LEN + VLAN_HLEN + 4) { ++ rdlen = rx_ring->count * ++ sizeof(struct e1000_rx_desc); ++ adapter->clean_rx = e1000_clean_rx_irq_jumbo; ++ adapter->alloc_rx_buf = e1000_alloc_rx_buffers_jumbo; ++ } else { ++ rdlen = rx_ring->count * ++ sizeof(struct e1000_rx_desc); ++ adapter->clean_rx = e1000_clean_rx_irq; ++ adapter->alloc_rx_buf = e1000_alloc_rx_buffers; ++ } ++ ++ /* disable receives while setting up the descriptors */ ++ rctl = er32(RCTL); ++ ew32(RCTL, rctl & ~E1000_RCTL_EN); ++ e1e_flush(); ++ msleep(10); ++ ++ /* set the Receive Delay Timer Register */ ++ ew32(RDTR, adapter->rx_int_delay); ++ ++ /* irq moderation */ ++ ew32(RADV, adapter->rx_abs_int_delay); ++ if (adapter->itr_setting != 0) ++ ew32(ITR, ++ 1000000000 / (adapter->itr * 256)); ++ ++ ctrl_ext = er32(CTRL_EXT); ++ /* Reset delay timers after every interrupt */ ++ ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR; ++ /* Auto-Mask interrupts upon ICR access */ ++ ctrl_ext |= E1000_CTRL_EXT_IAME; ++ ew32(IAM, 0xffffffff); ++ ew32(CTRL_EXT, ctrl_ext); ++ e1e_flush(); ++ ++ /* Setup the HW Rx Head and Tail Descriptor Pointers and ++ * the Base and Length of the Rx Descriptor Ring */ ++ rdba = rx_ring->dma; ++ ew32(RDBAL, (rdba & DMA_32BIT_MASK)); ++ ew32(RDBAH, (rdba >> 32)); ++ ew32(RDLEN, rdlen); ++ ew32(RDH, 0); ++ ew32(RDT, 0); ++ rx_ring->head = E1000_RDH; ++ rx_ring->tail = E1000_RDT; ++ ++ /* Enable Receive Checksum Offload for TCP and UDP */ ++ rxcsum = er32(RXCSUM); ++ if (adapter->flags & FLAG_RX_CSUM_ENABLED) { ++ rxcsum |= E1000_RXCSUM_TUOFL; ++ ++ /* IPv4 payload checksum for UDP fragments must be ++ * used in conjunction with packet-split. */ ++ if (adapter->rx_ps_pages) ++ rxcsum |= E1000_RXCSUM_IPPCSE; ++ } else { ++ rxcsum &= ~E1000_RXCSUM_TUOFL; ++ /* no need to clear IPPCSE as it defaults to 0 */ ++ } ++ ew32(RXCSUM, rxcsum); ++ ++ /* Enable early receives on supported devices, only takes effect when ++ * packet size is equal or larger than the specified value (in 8 byte ++ * units), e.g. using jumbo frames when setting to E1000_ERT_2048 */ ++ if ((adapter->flags & FLAG_HAS_ERT) && ++ (adapter->netdev->mtu > ETH_DATA_LEN)) ++ ew32(ERT, E1000_ERT_2048); ++ ++ /* Enable Receives */ ++ ew32(RCTL, rctl); ++} ++ ++/** ++ * e1000_mc_addr_list_update - Update Multicast addresses ++ * @hw: pointer to the HW structure ++ * @mc_addr_list: array of multicast addresses to program ++ * @mc_addr_count: number of multicast addresses to program ++ * @rar_used_count: the first RAR register free to program ++ * @rar_count: total number of supported Receive Address Registers ++ * ++ * Updates the Receive Address Registers and Multicast Table Array. ++ * The caller must have a packed mc_addr_list of multicast addresses. ++ * The parameter rar_count will usually be hw->mac.rar_entry_count ++ * unless there are workarounds that change this. Currently no func pointer ++ * exists and all implementations are handled in the generic version of this ++ * function. ++ **/ ++static void e1000_mc_addr_list_update(struct e1000_hw *hw, u8 *mc_addr_list, ++ u32 mc_addr_count, u32 rar_used_count, ++ u32 rar_count) ++{ ++ hw->mac.ops.mc_addr_list_update(hw, mc_addr_list, mc_addr_count, ++ rar_used_count, rar_count); ++} ++ ++/** ++ * e1000_set_multi - Multicast and Promiscuous mode set ++ * @netdev: network interface device structure ++ * ++ * The set_multi entry point is called whenever the multicast address ++ * list or the network interface flags are updated. This routine is ++ * responsible for configuring the hardware for proper multicast, ++ * promiscuous mode, and all-multi behavior. ++ **/ ++static void e1000_set_multi(struct net_device *netdev) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ struct e1000_hw *hw = &adapter->hw; ++ struct e1000_mac_info *mac = &hw->mac; ++ struct dev_mc_list *mc_ptr; ++ u8 *mta_list; ++ u32 rctl; ++ int i; ++ ++ /* Check for Promiscuous and All Multicast modes */ ++ ++ rctl = er32(RCTL); ++ ++ if (netdev->flags & IFF_PROMISC) { ++ rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); ++ } else if (netdev->flags & IFF_ALLMULTI) { ++ rctl |= E1000_RCTL_MPE; ++ rctl &= ~E1000_RCTL_UPE; ++ } else { ++ rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); ++ } ++ ++ ew32(RCTL, rctl); ++ ++ if (netdev->mc_count) { ++ mta_list = kmalloc(netdev->mc_count * 6, GFP_ATOMIC); ++ if (!mta_list) ++ return; ++ ++ /* prepare a packed array of only addresses. */ ++ mc_ptr = netdev->mc_list; ++ ++ for (i = 0; i < netdev->mc_count; i++) { ++ if (!mc_ptr) ++ break; ++ memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ++ ETH_ALEN); ++ mc_ptr = mc_ptr->next; ++ } ++ ++ e1000_mc_addr_list_update(hw, mta_list, i, 1, ++ mac->rar_entry_count); ++ kfree(mta_list); ++ } else { ++ /* ++ * if we're called from probe, we might not have ++ * anything to do here, so clear out the list ++ */ ++ e1000_mc_addr_list_update(hw, NULL, 0, 1, ++ mac->rar_entry_count); ++ } ++} ++ ++/** ++ * e1000_configure - configure the hardware for RX and TX ++ * @adapter: private board structure ++ **/ ++static void e1000_configure(struct e1000_adapter *adapter) ++{ ++ e1000_set_multi(adapter->netdev); ++ ++ e1000_restore_vlan(adapter); ++ e1000_init_manageability(adapter); ++ ++ e1000_configure_tx(adapter); ++ e1000_setup_rctl(adapter); ++ e1000_configure_rx(adapter); ++ adapter->alloc_rx_buf(adapter, ++ e1000_desc_unused(adapter->rx_ring)); ++} ++ ++/** ++ * e1000_power_up_phy - restore link in case the phy was powered down ++ * @adapter: address of board private structure ++ * ++ * The phy may be powered down to save power and turn off link when the ++ * driver is unloaded and wake on lan is not enabled (among others) ++ * *** this routine MUST be followed by a call to e1000_reset *** ++ **/ ++void e1000_power_up_phy(struct e1000_adapter *adapter) ++{ ++ u16 mii_reg = 0; ++ ++ /* Just clear the power down bit to wake the phy back up */ ++ if (adapter->hw.media_type == e1000_media_type_copper) { ++ /* according to the manual, the phy will retain its ++ * settings across a power-down/up cycle */ ++ e1e_rphy(&adapter->hw, PHY_CONTROL, &mii_reg); ++ mii_reg &= ~MII_CR_POWER_DOWN; ++ e1e_wphy(&adapter->hw, PHY_CONTROL, mii_reg); ++ } ++ ++ adapter->hw.mac.ops.setup_link(&adapter->hw); ++} ++ ++/** ++ * e1000_power_down_phy - Power down the PHY ++ * ++ * Power down the PHY so no link is implied when interface is down ++ * The PHY cannot be powered down is management or WoL is active ++ */ ++static void e1000_power_down_phy(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ u16 mii_reg; ++ ++ /* WoL is enabled */ ++ if (!adapter->wol) ++ return; ++ ++ /* non-copper PHY? */ ++ if (adapter->hw.media_type != e1000_media_type_copper) ++ return; ++ ++ /* reset is blocked because of a SoL/IDER session */ ++ if (e1000_check_mng_mode(hw) || ++ e1000_check_reset_block(hw)) ++ return; ++ ++ /* managebility (AMT) is enabled */ ++ if (er32(MANC) & E1000_MANC_SMBUS_EN) ++ return; ++ ++ /* power down the PHY */ ++ e1e_rphy(hw, PHY_CONTROL, &mii_reg); ++ mii_reg |= MII_CR_POWER_DOWN; ++ e1e_wphy(hw, PHY_CONTROL, mii_reg); ++ mdelay(1); ++} ++ ++/** ++ * e1000_reset - bring the hardware into a known good state ++ * ++ * This function boots the hardware and enables some settings that ++ * require a configuration cycle of the hardware - those cannot be ++ * set/changed during runtime. After reset the device needs to be ++ * properly configured for rx, tx etc. ++ */ ++void e1000_reset(struct e1000_adapter *adapter) ++{ ++ struct e1000_mac_info *mac = &adapter->hw.mac; ++ struct e1000_hw *hw = &adapter->hw; ++ u32 tx_space, min_tx_space, min_rx_space; ++ u16 hwm; ++ ++ if (mac->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN ) { ++ /* To maintain wire speed transmits, the Tx FIFO should be ++ * large enough to accommodate two full transmit packets, ++ * rounded up to the next 1KB and expressed in KB. Likewise, ++ * the Rx FIFO should be large enough to accommodate at least ++ * one full receive packet and is similarly rounded up and ++ * expressed in KB. */ ++ adapter->pba = er32(PBA); ++ /* upper 16 bits has Tx packet buffer allocation size in KB */ ++ tx_space = adapter->pba >> 16; ++ /* lower 16 bits has Rx packet buffer allocation size in KB */ ++ adapter->pba &= 0xffff; ++ /* the tx fifo also stores 16 bytes of information about the tx ++ * but don't include ethernet FCS because hardware appends it */ ++ min_tx_space = (mac->max_frame_size + ++ sizeof(struct e1000_tx_desc) - ++ ETH_FCS_LEN) * 2; ++ min_tx_space = ALIGN(min_tx_space, 1024); ++ min_tx_space >>= 10; ++ /* software strips receive CRC, so leave room for it */ ++ min_rx_space = mac->max_frame_size; ++ min_rx_space = ALIGN(min_rx_space, 1024); ++ min_rx_space >>= 10; ++ ++ /* If current Tx allocation is less than the min Tx FIFO size, ++ * and the min Tx FIFO size is less than the current Rx FIFO ++ * allocation, take space away from current Rx allocation */ ++ if (tx_space < min_tx_space && ++ ((min_tx_space - tx_space) < adapter->pba)) { ++ adapter->pba -= - (min_tx_space - tx_space); ++ ++ /* if short on rx space, rx wins and must trump tx ++ * adjustment or use Early Receive if available */ ++ if ((adapter->pba < min_rx_space) && ++ (!(adapter->flags & FLAG_HAS_ERT))) ++ /* ERT enabled in e1000_configure_rx */ ++ adapter->pba = min_rx_space; ++ } ++ } ++ ++ ew32(PBA, adapter->pba); ++ ++ /* flow control settings */ ++ /* The high water mark must be low enough to fit one full frame ++ * (or the size used for early receive) above it in the Rx FIFO. ++ * Set it to the lower of: ++ * - 90% of the Rx FIFO size, and ++ * - the full Rx FIFO size minus the early receive size (for parts ++ * with ERT support assuming ERT set to E1000_ERT_2048), or ++ * - the full Rx FIFO size minus one full frame */ ++ if (adapter->flags & FLAG_HAS_ERT) ++ hwm = min(((adapter->pba << 10) * 9 / 10), ++ ((adapter->pba << 10) - (E1000_ERT_2048 << 3))); ++ else ++ hwm = min(((adapter->pba << 10) * 9 / 10), ++ ((adapter->pba << 10) - mac->max_frame_size)); ++ ++ mac->fc_high_water = hwm & 0xFFF8; /* 8-byte granularity */ ++ mac->fc_low_water = mac->fc_high_water - 8; ++ ++ if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) ++ mac->fc_pause_time = 0xFFFF; ++ else ++ mac->fc_pause_time = E1000_FC_PAUSE_TIME; ++ mac->fc = mac->original_fc; ++ ++ /* Allow time for pending master requests to run */ ++ mac->ops.reset_hw(hw); ++ ew32(WUC, 0); ++ ++ if (mac->ops.init_hw(hw)) ++ ndev_err(adapter->netdev, "Hardware Error\n"); ++ ++ e1000_update_mng_vlan(adapter); ++ ++ /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ ++ ew32(VET, ETH_P_8021Q); ++ ++ e1000_reset_adaptive(hw); ++ e1000_get_phy_info(hw); ++ ++ if (!(adapter->flags & FLAG_SMART_POWER_DOWN)) { ++ u16 phy_data = 0; ++ /* speed up time to link by disabling smart power down, ignore ++ * the return value of this function because there is nothing ++ * different we would do if it failed */ ++ e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); ++ phy_data &= ~IGP02E1000_PM_SPD; ++ e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); ++ } ++ ++ e1000_release_manageability(adapter); ++} ++ ++int e1000_up(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ ++ /* hardware has been reset, we need to reload some things */ ++ e1000_configure(adapter); ++ ++ clear_bit(__E1000_DOWN, &adapter->state); ++ ++ netif_poll_enable(adapter->netdev); ++ e1000_irq_enable(adapter); ++ ++ /* fire a link change interrupt to start the watchdog */ ++ ew32(ICS, E1000_ICS_LSC); ++ return 0; ++} ++ ++void e1000_down(struct e1000_adapter *adapter) ++{ ++ struct net_device *netdev = adapter->netdev; ++ struct e1000_hw *hw = &adapter->hw; ++ u32 tctl, rctl; ++ ++ /* signal that we're down so the interrupt handler does not ++ * reschedule our watchdog timer */ ++ set_bit(__E1000_DOWN, &adapter->state); ++ ++ /* disable receives in the hardware */ ++ rctl = er32(RCTL); ++ ew32(RCTL, rctl & ~E1000_RCTL_EN); ++ /* flush and sleep below */ ++ ++ netif_stop_queue(netdev); ++ ++ /* disable transmits in the hardware */ ++ tctl = er32(TCTL); ++ tctl &= ~E1000_TCTL_EN; ++ ew32(TCTL, tctl); ++ /* flush both disables and wait for them to finish */ ++ e1e_flush(); ++ msleep(10); ++ ++ netif_poll_disable(netdev); ++ e1000_irq_disable(adapter); ++ ++ del_timer_sync(&adapter->watchdog_timer); ++ del_timer_sync(&adapter->phy_info_timer); ++ ++ netdev->tx_queue_len = adapter->tx_queue_len; ++ netif_carrier_off(netdev); ++ adapter->link_speed = 0; ++ adapter->link_duplex = 0; ++ ++ e1000_reset(adapter); ++ e1000_clean_tx_ring(adapter); ++ e1000_clean_rx_ring(adapter); ++ ++ /* ++ * TODO: for power management, we could drop the link and ++ * pci_disable_device here. ++ */ ++} ++ ++void e1000_reinit_locked(struct e1000_adapter *adapter) ++{ ++ might_sleep(); ++ while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) ++ msleep(1); ++ e1000_down(adapter); ++ e1000_up(adapter); ++ clear_bit(__E1000_RESETTING, &adapter->state); ++} ++ ++/** ++ * e1000_sw_init - Initialize general software structures (struct e1000_adapter) ++ * @adapter: board private structure to initialize ++ * ++ * e1000_sw_init initializes the Adapter private data structure. ++ * Fields are initialized based on PCI device information and ++ * OS network device settings (MTU size). ++ **/ ++static int __devinit e1000_sw_init(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ struct net_device *netdev = adapter->netdev; ++ ++ adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN; ++ adapter->rx_ps_bsize0 = 128; ++ hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; ++ hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN; ++ ++ adapter->tx_ring = kzalloc(sizeof(struct e1000_ring), GFP_KERNEL); ++ if (!adapter->tx_ring) ++ goto err; ++ ++ adapter->rx_ring = kzalloc(sizeof(struct e1000_ring), GFP_KERNEL); ++ if (!adapter->rx_ring) ++ goto err; ++ ++ spin_lock_init(&adapter->tx_queue_lock); ++ ++ /* Explicitly disable IRQ since the NIC can be in any state. */ ++ atomic_set(&adapter->irq_sem, 0); ++ e1000_irq_disable(adapter); ++ ++ spin_lock_init(&adapter->stats_lock); ++ ++ set_bit(__E1000_DOWN, &adapter->state); ++ return 0; ++ ++err: ++ ndev_err(netdev, "Unable to allocate memory for queues\n"); ++ kfree(adapter->rx_ring); ++ kfree(adapter->tx_ring); ++ return -ENOMEM; ++} ++ ++/** ++ * e1000_open - Called when a network interface is made active ++ * @netdev: network interface device structure ++ * ++ * Returns 0 on success, negative value on failure ++ * ++ * The open entry point is called when a network interface is made ++ * active by the system (IFF_UP). At this point all resources needed ++ * for transmit and receive operations are allocated, the interrupt ++ * handler is registered with the OS, the watchdog timer is started, ++ * and the stack is notified that the interface is ready. ++ **/ ++static int e1000_open(struct net_device *netdev) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ struct e1000_hw *hw = &adapter->hw; ++ int err; ++ ++ /* disallow open during test */ ++ if (test_bit(__E1000_TESTING, &adapter->state)) ++ return -EBUSY; ++ ++ /* allocate transmit descriptors */ ++ err = e1000_setup_tx_resources(adapter); ++ if (err) ++ goto err_setup_tx; ++ ++ /* allocate receive descriptors */ ++ err = e1000_setup_rx_resources(adapter); ++ if (err) ++ goto err_setup_rx; ++ ++ e1000_power_up_phy(adapter); ++ ++ adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; ++ if ((adapter->hw.mng_cookie.status & ++ E1000_MNG_DHCP_COOKIE_STATUS_VLAN)) ++ e1000_update_mng_vlan(adapter); ++ ++ /* If AMT is enabled, let the firmware know that the network ++ * interface is now open */ ++ if ((adapter->flags & FLAG_HAS_AMT) && ++ e1000_check_mng_mode(&adapter->hw)) ++ e1000_get_hw_control(adapter); ++ ++ /* before we allocate an interrupt, we must be ready to handle it. ++ * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt ++ * as soon as we call pci_request_irq, so we have to setup our ++ * clean_rx handler before we do so. */ ++ e1000_configure(adapter); ++ ++ err = e1000_request_irq(adapter); ++ if (err) ++ goto err_req_irq; ++ ++ /* From here on the code is the same as e1000_up() */ ++ clear_bit(__E1000_DOWN, &adapter->state); ++ ++ netif_poll_enable(netdev); ++ ++ e1000_irq_enable(adapter); ++ ++ /* fire a link status change interrupt to start the watchdog */ ++ ew32(ICS, E1000_ICS_LSC); ++ ++ return E1000_SUCCESS; ++ ++err_req_irq: ++ e1000_release_hw_control(adapter); ++ e1000_power_down_phy(adapter); ++ e1000_free_rx_resources(adapter); ++err_setup_rx: ++ e1000_free_tx_resources(adapter); ++err_setup_tx: ++ e1000_reset(adapter); ++ ++ return err; ++} ++ ++/** ++ * e1000_close - Disables a network interface ++ * @netdev: network interface device structure ++ * ++ * Returns 0, this is not allowed to fail ++ * ++ * The close entry point is called when an interface is de-activated ++ * by the OS. The hardware is still under the drivers control, but ++ * needs to be disabled. A global MAC reset is issued to stop the ++ * hardware, and all transmit and receive resources are freed. ++ **/ ++static int e1000_close(struct net_device *netdev) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ ++ WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); ++ e1000_down(adapter); ++ e1000_power_down_phy(adapter); ++ e1000_free_irq(adapter); ++ ++ e1000_free_tx_resources(adapter); ++ e1000_free_rx_resources(adapter); ++ ++ /* kill manageability vlan ID if supported, but not if a vlan with ++ * the same ID is registered on the host OS (let 8021q kill it) */ ++ if ((adapter->hw.mng_cookie.status & ++ E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && ++ !(adapter->vlgrp && ++ vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id))) ++ e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); ++ ++ /* If AMT is enabled, let the firmware know that the network ++ * interface is now closed */ ++ if ((adapter->flags & FLAG_HAS_AMT) && ++ e1000_check_mng_mode(&adapter->hw)) ++ e1000_release_hw_control(adapter); ++ ++ return 0; ++} ++/** ++ * e1000_set_mac - Change the Ethernet Address of the NIC ++ * @netdev: network interface device structure ++ * @p: pointer to an address structure ++ * ++ * Returns 0 on success, negative on failure ++ **/ ++static int e1000_set_mac(struct net_device *netdev, void *p) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ struct sockaddr *addr = p; ++ ++ if (!is_valid_ether_addr(addr->sa_data)) ++ return -EADDRNOTAVAIL; ++ ++ memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); ++ memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len); ++ ++ e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); ++ ++ if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) { ++ /* activate the work around */ ++ e1000_set_laa_state_82571(&adapter->hw, 1); ++ ++ /* Hold a copy of the LAA in RAR[14] This is done so that ++ * between the time RAR[0] gets clobbered and the time it ++ * gets fixed (in e1000_watchdog), the actual LAA is in one ++ * of the RARs and no incoming packets directed to this port ++ * are dropped. Eventually the LAA will be in RAR[0] and ++ * RAR[14] */ ++ e1000_rar_set(&adapter->hw, ++ adapter->hw.mac.addr, ++ adapter->hw.mac.rar_entry_count - 1); ++ } ++ ++ return 0; ++} ++ ++/* Need to wait a few seconds after link up to get diagnostic information from ++ * the phy */ ++static void e1000_update_phy_info(unsigned long data) ++{ ++ struct e1000_adapter *adapter = (struct e1000_adapter *) data; ++ e1000_get_phy_info(&adapter->hw); ++} ++ ++/** ++ * e1000_update_stats - Update the board statistics counters ++ * @adapter: board private structure ++ **/ ++void e1000_update_stats(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ struct pci_dev *pdev = adapter->pdev; ++ unsigned long irq_flags; ++ u16 phy_tmp; ++ ++#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF ++ ++ /* ++ * Prevent stats update while adapter is being reset, or if the pci ++ * connection is down. ++ */ ++ if (adapter->link_speed == 0) ++ return; ++ if (pci_channel_offline(pdev)) ++ return; ++ ++ spin_lock_irqsave(&adapter->stats_lock, irq_flags); ++ ++ /* these counters are modified from e1000_adjust_tbi_stats, ++ * called from the interrupt context, so they must only ++ * be written while holding adapter->stats_lock ++ */ ++ ++ adapter->stats.crcerrs += er32(CRCERRS); ++ adapter->stats.gprc += er32(GPRC); ++ adapter->stats.gorcl += er32(GORCL); ++ adapter->stats.gorch += er32(GORCH); ++ adapter->stats.bprc += er32(BPRC); ++ adapter->stats.mprc += er32(MPRC); ++ adapter->stats.roc += er32(ROC); ++ ++ if (adapter->flags & FLAG_HAS_STATS_PTC_PRC) { ++ adapter->stats.prc64 += er32(PRC64); ++ adapter->stats.prc127 += er32(PRC127); ++ adapter->stats.prc255 += er32(PRC255); ++ adapter->stats.prc511 += er32(PRC511); ++ adapter->stats.prc1023 += er32(PRC1023); ++ adapter->stats.prc1522 += er32(PRC1522); ++ adapter->stats.symerrs += er32(SYMERRS); ++ adapter->stats.sec += er32(SEC); ++ } ++ ++ adapter->stats.mpc += er32(MPC); ++ adapter->stats.scc += er32(SCC); ++ adapter->stats.ecol += er32(ECOL); ++ adapter->stats.mcc += er32(MCC); ++ adapter->stats.latecol += er32(LATECOL); ++ adapter->stats.dc += er32(DC); ++ adapter->stats.rlec += er32(RLEC); ++ adapter->stats.xonrxc += er32(XONRXC); ++ adapter->stats.xontxc += er32(XONTXC); ++ adapter->stats.xoffrxc += er32(XOFFRXC); ++ adapter->stats.xofftxc += er32(XOFFTXC); ++ adapter->stats.fcruc += er32(FCRUC); ++ adapter->stats.gptc += er32(GPTC); ++ adapter->stats.gotcl += er32(GOTCL); ++ adapter->stats.gotch += er32(GOTCH); ++ adapter->stats.rnbc += er32(RNBC); ++ adapter->stats.ruc += er32(RUC); ++ adapter->stats.rfc += er32(RFC); ++ adapter->stats.rjc += er32(RJC); ++ adapter->stats.torl += er32(TORL); ++ adapter->stats.torh += er32(TORH); ++ adapter->stats.totl += er32(TOTL); ++ adapter->stats.toth += er32(TOTH); ++ adapter->stats.tpr += er32(TPR); ++ ++ if (adapter->flags & FLAG_HAS_STATS_PTC_PRC) { ++ adapter->stats.ptc64 += er32(PTC64); ++ adapter->stats.ptc127 += er32(PTC127); ++ adapter->stats.ptc255 += er32(PTC255); ++ adapter->stats.ptc511 += er32(PTC511); ++ adapter->stats.ptc1023 += er32(PTC1023); ++ adapter->stats.ptc1522 += er32(PTC1522); ++ } ++ ++ adapter->stats.mptc += er32(MPTC); ++ adapter->stats.bptc += er32(BPTC); ++ ++ /* used for adaptive IFS */ ++ ++ hw->mac.tx_packet_delta = er32(TPT); ++ adapter->stats.tpt += hw->mac.tx_packet_delta; ++ hw->mac.collision_delta = er32(COLC); ++ adapter->stats.colc += hw->mac.collision_delta; ++ ++ adapter->stats.algnerrc += er32(ALGNERRC); ++ adapter->stats.rxerrc += er32(RXERRC); ++ adapter->stats.tncrs += er32(TNCRS); ++ adapter->stats.cexterr += er32(CEXTERR); ++ adapter->stats.tsctc += er32(TSCTC); ++ adapter->stats.tsctfc += er32(TSCTFC); ++ ++ adapter->stats.iac += er32(IAC); ++ ++ if (adapter->flags & FLAG_HAS_STATS_ICR_ICT) { ++ adapter->stats.icrxoc += er32(ICRXOC); ++ adapter->stats.icrxptc += er32(ICRXPTC); ++ adapter->stats.icrxatc += er32(ICRXATC); ++ adapter->stats.ictxptc += er32(ICTXPTC); ++ adapter->stats.ictxatc += er32(ICTXATC); ++ adapter->stats.ictxqec += er32(ICTXQEC); ++ adapter->stats.ictxqmtc += er32(ICTXQMTC); ++ adapter->stats.icrxdmtc += er32(ICRXDMTC); ++ } ++ ++ /* Fill out the OS statistics structure */ ++ adapter->net_stats.rx_packets = adapter->stats.gprc; ++ adapter->net_stats.tx_packets = adapter->stats.gptc; ++ adapter->net_stats.rx_bytes = adapter->stats.gorcl; ++ adapter->net_stats.tx_bytes = adapter->stats.gotcl; ++ adapter->net_stats.multicast = adapter->stats.mprc; ++ adapter->net_stats.collisions = adapter->stats.colc; ++ ++ /* Rx Errors */ ++ ++ /* RLEC on some newer hardware can be incorrect so build ++ * our own version based on RUC and ROC */ ++ adapter->net_stats.rx_errors = adapter->stats.rxerrc + ++ adapter->stats.crcerrs + adapter->stats.algnerrc + ++ adapter->stats.ruc + adapter->stats.roc + ++ adapter->stats.cexterr; ++ adapter->net_stats.rx_length_errors = adapter->stats.ruc + ++ adapter->stats.roc; ++ adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs; ++ adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc; ++ adapter->net_stats.rx_missed_errors = adapter->stats.mpc; ++ ++ /* Tx Errors */ ++ adapter->net_stats.tx_errors = adapter->stats.ecol + ++ adapter->stats.latecol; ++ adapter->net_stats.tx_aborted_errors = adapter->stats.ecol; ++ adapter->net_stats.tx_window_errors = adapter->stats.latecol; ++ adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs; ++ ++ /* Tx Dropped needs to be maintained elsewhere */ ++ ++ /* Phy Stats */ ++ if (hw->media_type == e1000_media_type_copper) { ++ if ((adapter->link_speed == SPEED_1000) && ++ (!e1e_rphy(hw, PHY_1000T_STATUS, &phy_tmp))) { ++ phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK; ++ adapter->phy_stats.idle_errors += phy_tmp; ++ } ++ } ++ ++ /* Management Stats */ ++ adapter->stats.mgptc += er32(MGTPTC); ++ adapter->stats.mgprc += er32(MGTPRC); ++ adapter->stats.mgpdc += er32(MGTPDC); ++ ++ spin_unlock_irqrestore(&adapter->stats_lock, irq_flags); ++} ++ ++static void e1000_print_link_info(struct e1000_adapter *adapter) ++{ ++ struct net_device *netdev = adapter->netdev; ++ struct e1000_hw *hw = &adapter->hw; ++ u32 ctrl = er32(CTRL); ++ ++ ndev_info(netdev, ++ "Link is Up %d Mbps %s, Flow Control: %s\n", ++ adapter->link_speed, ++ (adapter->link_duplex == FULL_DUPLEX) ? ++ "Full Duplex" : "Half Duplex", ++ ((ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE)) ? ++ "RX/TX" : ++ ((ctrl & E1000_CTRL_RFCE) ? "RX" : ++ ((ctrl & E1000_CTRL_TFCE) ? "TX" : "None" ))); ++} ++ ++/** ++ * e1000_watchdog - Timer Call-back ++ * @data: pointer to adapter cast into an unsigned long ++ **/ ++static void e1000_watchdog(unsigned long data) ++{ ++ struct e1000_adapter *adapter = (struct e1000_adapter *) data; ++ ++ /* Do the rest outside of interrupt context */ ++ schedule_work(&adapter->watchdog_task); ++ ++ /* TODO: make this use queue_delayed_work() */ ++} ++ ++static void e1000_watchdog_task(struct work_struct *work) ++{ ++ struct e1000_adapter *adapter = container_of(work, ++ struct e1000_adapter, watchdog_task); ++ ++ struct net_device *netdev = adapter->netdev; ++ struct e1000_mac_info *mac = &adapter->hw.mac; ++ struct e1000_ring *tx_ring = adapter->tx_ring; ++ struct e1000_hw *hw = &adapter->hw; ++ u32 link, tctl; ++ s32 ret_val; ++ int tx_pending = 0; ++ ++ if ((netif_carrier_ok(netdev)) && ++ (er32(STATUS) & E1000_STATUS_LU)) ++ goto link_up; ++ ++ ret_val = mac->ops.check_for_link(hw); ++ if ((ret_val == E1000_ERR_PHY) && ++ (adapter->hw.phy.type == e1000_phy_igp_3) && ++ (er32(CTRL) & ++ E1000_PHY_CTRL_GBE_DISABLE)) { ++ /* See e1000_kmrn_lock_loss_workaround_ich8lan() */ ++ ndev_info(netdev, ++ "Gigabit has been disabled, downgrading speed\n"); ++ } ++ ++ if ((e1000_enable_tx_pkt_filtering(hw)) && ++ (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)) ++ e1000_update_mng_vlan(adapter); ++ ++ if ((adapter->hw.media_type == e1000_media_type_internal_serdes) && ++ !(er32(TXCW) & E1000_TXCW_ANE)) ++ link = adapter->hw.mac.serdes_has_link; ++ else ++ link = er32(STATUS) & E1000_STATUS_LU; ++ ++ if (link) { ++ if (!netif_carrier_ok(netdev)) { ++ bool txb2b = 1; ++ mac->ops.get_link_up_info(&adapter->hw, ++ &adapter->link_speed, ++ &adapter->link_duplex); ++ e1000_print_link_info(adapter); ++ /* tweak tx_queue_len according to speed/duplex ++ * and adjust the timeout factor */ ++ netdev->tx_queue_len = adapter->tx_queue_len; ++ adapter->tx_timeout_factor = 1; ++ switch (adapter->link_speed) { ++ case SPEED_10: ++ txb2b = 0; ++ netdev->tx_queue_len = 10; ++ adapter->tx_timeout_factor = 14; ++ break; ++ case SPEED_100: ++ txb2b = 0; ++ netdev->tx_queue_len = 100; ++ /* maybe add some timeout factor ? */ ++ break; ++ } ++ ++ /* workaround: re-program speed mode bit after ++ * link-up event */ ++ if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) && ++ !txb2b) { ++ u32 tarc0; ++ tarc0 = er32(TARC0); ++ tarc0 &= ~SPEED_MODE_BIT; ++ ew32(TARC0, tarc0); ++ } ++ ++ /* disable TSO for pcie and 10/100 speeds, to avoid ++ * some hardware issues */ ++ if (!(adapter->flags & FLAG_TSO_FORCE)) { ++ switch (adapter->link_speed) { ++ case SPEED_10: ++ case SPEED_100: ++ ndev_info(netdev, ++ "10/100 speed: disabling TSO\n"); ++ netdev->features &= ~NETIF_F_TSO; ++ netdev->features &= ~NETIF_F_TSO6; ++ break; ++ case SPEED_1000: ++ netdev->features |= NETIF_F_TSO; ++ netdev->features |= NETIF_F_TSO6; ++ break; ++ default: ++ /* oops */ ++ break; ++ } ++ } ++ ++ /* enable transmits in the hardware, need to do this ++ * after setting TARC0 */ ++ tctl = er32(TCTL); ++ tctl |= E1000_TCTL_EN; ++ ew32(TCTL, tctl); ++ ++ netif_carrier_on(netdev); ++ netif_wake_queue(netdev); ++ ++ if (!test_bit(__E1000_DOWN, &adapter->state)) ++ mod_timer(&adapter->phy_info_timer, ++ round_jiffies(jiffies + 2 * HZ)); ++ } else { ++ /* make sure the receive unit is started */ ++ if (adapter->flags & FLAG_RX_NEEDS_RESTART) { ++ struct e1000_hw *hw = &adapter->hw; ++ u32 rctl = er32(RCTL); ++ ew32(RCTL, rctl | ++ E1000_RCTL_EN); ++ } ++ } ++ } else { ++ if (netif_carrier_ok(netdev)) { ++ adapter->link_speed = 0; ++ adapter->link_duplex = 0; ++ ndev_info(netdev, "Link is Down\n"); ++ netif_carrier_off(netdev); ++ netif_stop_queue(netdev); ++ if (!test_bit(__E1000_DOWN, &adapter->state)) ++ mod_timer(&adapter->phy_info_timer, ++ round_jiffies(jiffies + 2 * HZ)); ++ ++ if (adapter->flags & FLAG_RX_NEEDS_RESTART) ++ schedule_work(&adapter->reset_task); ++ } ++ } ++ ++link_up: ++ e1000_update_stats(adapter); ++ ++ mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; ++ adapter->tpt_old = adapter->stats.tpt; ++ mac->collision_delta = adapter->stats.colc - adapter->colc_old; ++ adapter->colc_old = adapter->stats.colc; ++ ++ adapter->gorcl = adapter->stats.gorcl - adapter->gorcl_old; ++ adapter->gorcl_old = adapter->stats.gorcl; ++ adapter->gotcl = adapter->stats.gotcl - adapter->gotcl_old; ++ adapter->gotcl_old = adapter->stats.gotcl; ++ ++ e1000_update_adaptive(&adapter->hw); ++ ++ if (!netif_carrier_ok(netdev)) { ++ tx_pending = (e1000_desc_unused(tx_ring) + 1 < ++ tx_ring->count); ++ if (tx_pending) { ++ /* We've lost link, so the controller stops DMA, ++ * but we've got queued Tx work that's never going ++ * to get done, so reset controller to flush Tx. ++ * (Do the reset outside of interrupt context). */ ++ adapter->tx_timeout_count++; ++ schedule_work(&adapter->reset_task); ++ } ++ } ++ ++ /* Cause software interrupt to ensure rx ring is cleaned */ ++ ew32(ICS, E1000_ICS_RXDMT0); ++ ++ /* Force detection of hung controller every watchdog period */ ++ adapter->detect_tx_hung = 1; ++ ++ /* With 82571 controllers, LAA may be overwritten due to controller ++ * reset from the other port. Set the appropriate LAA in RAR[0] */ ++ if (e1000_get_laa_state_82571(hw)) ++ e1000_rar_set(hw, adapter->hw.mac.addr, 0); ++ ++ /* Reset the timer */ ++ if (!test_bit(__E1000_DOWN, &adapter->state)) ++ mod_timer(&adapter->watchdog_timer, ++ round_jiffies(jiffies + 2 * HZ)); ++} ++ ++#define E1000_TX_FLAGS_CSUM 0x00000001 ++#define E1000_TX_FLAGS_VLAN 0x00000002 ++#define E1000_TX_FLAGS_TSO 0x00000004 ++#define E1000_TX_FLAGS_IPV4 0x00000008 ++#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000 ++#define E1000_TX_FLAGS_VLAN_SHIFT 16 ++ ++static int e1000_tso(struct e1000_adapter *adapter, ++ struct sk_buff *skb) ++{ ++ struct e1000_ring *tx_ring = adapter->tx_ring; ++ struct e1000_context_desc *context_desc; ++ struct e1000_buffer *buffer_info; ++ unsigned int i; ++ u32 cmd_length = 0; ++ u16 ipcse = 0, tucse, mss; ++ u8 ipcss, ipcso, tucss, tucso, hdr_len; ++ int err; ++ ++ if (skb_is_gso(skb)) { ++ if (skb_header_cloned(skb)) { ++ err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); ++ if (err) ++ return err; ++ } ++ ++ hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); ++ mss = skb_shinfo(skb)->gso_size; ++ if (skb->protocol == htons(ETH_P_IP)) { ++ struct iphdr *iph = ip_hdr(skb); ++ iph->tot_len = 0; ++ iph->check = 0; ++ tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, ++ iph->daddr, 0, ++ IPPROTO_TCP, ++ 0); ++ cmd_length = E1000_TXD_CMD_IP; ++ ipcse = skb_transport_offset(skb) - 1; ++ } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) { ++ ipv6_hdr(skb)->payload_len = 0; ++ tcp_hdr(skb)->check = ++ ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, ++ &ipv6_hdr(skb)->daddr, ++ 0, IPPROTO_TCP, 0); ++ ipcse = 0; ++ } ++ ipcss = skb_network_offset(skb); ++ ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data; ++ tucss = skb_transport_offset(skb); ++ tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data; ++ tucse = 0; ++ ++ cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE | ++ E1000_TXD_CMD_TCP | (skb->len - (hdr_len))); ++ ++ i = tx_ring->next_to_use; ++ context_desc = E1000_CONTEXT_DESC(*tx_ring, i); ++ buffer_info = &tx_ring->buffer_info[i]; ++ ++ context_desc->lower_setup.ip_fields.ipcss = ipcss; ++ context_desc->lower_setup.ip_fields.ipcso = ipcso; ++ context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse); ++ context_desc->upper_setup.tcp_fields.tucss = tucss; ++ context_desc->upper_setup.tcp_fields.tucso = tucso; ++ context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse); ++ context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss); ++ context_desc->tcp_seg_setup.fields.hdr_len = hdr_len; ++ context_desc->cmd_and_length = cpu_to_le32(cmd_length); ++ ++ buffer_info->time_stamp = jiffies; ++ buffer_info->next_to_watch = i; ++ ++ i++; ++ if (i == tx_ring->count) ++ i = 0; ++ tx_ring->next_to_use = i; ++ ++ return 1; ++ } ++ ++ return 0; ++} ++ ++static bool e1000_tx_csum(struct e1000_adapter *adapter, struct sk_buff *skb) ++{ ++ struct e1000_ring *tx_ring = adapter->tx_ring; ++ struct e1000_context_desc *context_desc; ++ struct e1000_buffer *buffer_info; ++ unsigned int i; ++ u8 css; ++ ++ if (skb->ip_summed == CHECKSUM_PARTIAL) { ++ css = skb_transport_offset(skb); ++ ++ i = tx_ring->next_to_use; ++ buffer_info = &tx_ring->buffer_info[i]; ++ context_desc = E1000_CONTEXT_DESC(*tx_ring, i); ++ ++ context_desc->lower_setup.ip_config = 0; ++ context_desc->upper_setup.tcp_fields.tucss = css; ++ context_desc->upper_setup.tcp_fields.tucso = ++ css + skb->csum_offset; ++ context_desc->upper_setup.tcp_fields.tucse = 0; ++ context_desc->tcp_seg_setup.data = 0; ++ context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT); ++ ++ buffer_info->time_stamp = jiffies; ++ buffer_info->next_to_watch = i; ++ ++ i++; ++ if (i == tx_ring->count) ++ i = 0; ++ tx_ring->next_to_use = i; ++ ++ return 1; ++ } ++ ++ return 0; ++} ++ ++#define E1000_MAX_PER_TXD 8192 ++#define E1000_MAX_TXD_PWR 12 ++ ++static int e1000_tx_map(struct e1000_adapter *adapter, ++ struct sk_buff *skb, unsigned int first, ++ unsigned int max_per_txd, unsigned int nr_frags, ++ unsigned int mss) ++{ ++ struct e1000_ring *tx_ring = adapter->tx_ring; ++ struct e1000_buffer *buffer_info; ++ unsigned int len = skb->len - skb->data_len; ++ unsigned int offset = 0, size, count = 0, i; ++ unsigned int f; ++ ++ i = tx_ring->next_to_use; ++ ++ while (len) { ++ buffer_info = &tx_ring->buffer_info[i]; ++ size = min(len, max_per_txd); ++ /* Workaround for Controller erratum -- ++ * descriptor for non-tso packet in a linear SKB that follows a ++ * tso gets written back prematurely before the data is fully ++ * DMA'd to the controller */ ++ if (tx_ring->last_tx_tso && !skb_is_gso(skb)) { ++ tx_ring->last_tx_tso = 0; ++ if (!skb->data_len) ++ size -= 4; ++ } ++ ++ /* Workaround for premature desc write-backs ++ * in TSO mode. Append 4-byte sentinel desc */ ++ if (mss && !nr_frags && size == len && size > 8) ++ size -= 4; ++ ++ buffer_info->length = size; ++ /* set time_stamp *before* dma to help avoid a possible race */ ++ buffer_info->time_stamp = jiffies; ++ buffer_info->dma = ++ pci_map_single(adapter->pdev, ++ skb->data + offset, ++ size, ++ PCI_DMA_TODEVICE); ++ buffer_info->next_to_watch = i; ++ ++ len -= size; ++ offset += size; ++ count++; ++ i++; ++ if (i == tx_ring->count) ++ i = 0; ++ } ++ ++ for (f = 0; f < nr_frags; f++) { ++ struct skb_frag_struct *frag; ++ ++ frag = &skb_shinfo(skb)->frags[f]; ++ len = frag->size; ++ offset = frag->page_offset; ++ ++ while (len) { ++ buffer_info = &tx_ring->buffer_info[i]; ++ size = min(len, max_per_txd); ++ /* Workaround for premature desc write-backs ++ * in TSO mode. Append 4-byte sentinel desc */ ++ if (mss && f == (nr_frags-1) && size == len && size > 8) ++ size -= 4; ++ ++ buffer_info->length = size; ++ buffer_info->time_stamp = jiffies; ++ buffer_info->dma = ++ pci_map_page(adapter->pdev, ++ frag->page, ++ offset, ++ size, ++ PCI_DMA_TODEVICE); ++ buffer_info->next_to_watch = i; ++ ++ len -= size; ++ offset += size; ++ count++; ++ ++ i++; ++ if (i == tx_ring->count) ++ i = 0; ++ } ++ } ++ ++ if (i == 0) ++ i = tx_ring->count - 1; ++ else ++ i--; ++ ++ tx_ring->buffer_info[i].skb = skb; ++ tx_ring->buffer_info[first].next_to_watch = i; ++ ++ return count; ++} ++ ++static void e1000_tx_queue(struct e1000_adapter *adapter, ++ int tx_flags, int count) ++{ ++ struct e1000_ring *tx_ring = adapter->tx_ring; ++ struct e1000_tx_desc *tx_desc = NULL; ++ struct e1000_buffer *buffer_info; ++ u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS; ++ unsigned int i; ++ ++ if (tx_flags & E1000_TX_FLAGS_TSO) { ++ txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D | ++ E1000_TXD_CMD_TSE; ++ txd_upper |= E1000_TXD_POPTS_TXSM << 8; ++ ++ if (tx_flags & E1000_TX_FLAGS_IPV4) ++ txd_upper |= E1000_TXD_POPTS_IXSM << 8; ++ } ++ ++ if (tx_flags & E1000_TX_FLAGS_CSUM) { ++ txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; ++ txd_upper |= E1000_TXD_POPTS_TXSM << 8; ++ } ++ ++ if (tx_flags & E1000_TX_FLAGS_VLAN) { ++ txd_lower |= E1000_TXD_CMD_VLE; ++ txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK); ++ } ++ ++ i = tx_ring->next_to_use; ++ ++ while (count--) { ++ buffer_info = &tx_ring->buffer_info[i]; ++ tx_desc = E1000_TX_DESC(*tx_ring, i); ++ tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); ++ tx_desc->lower.data = ++ cpu_to_le32(txd_lower | buffer_info->length); ++ tx_desc->upper.data = cpu_to_le32(txd_upper); ++ ++ i++; ++ if (i == tx_ring->count) ++ i = 0; ++ } ++ ++ tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd); ++ ++ /* Force memory writes to complete before letting h/w ++ * know there are new descriptors to fetch. (Only ++ * applicable for weak-ordered memory model archs, ++ * such as IA-64). */ ++ wmb(); ++ ++ tx_ring->next_to_use = i; ++ writel(i, adapter->hw.hw_addr + tx_ring->tail); ++ /* we need this if more than one processor can write to our tail ++ * at a time, it synchronizes IO on IA64/Altix systems */ ++ mmiowb(); ++} ++ ++#define MINIMUM_DHCP_PACKET_SIZE 282 ++static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter, ++ struct sk_buff *skb) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ u16 length, offset; ++ ++ if (vlan_tx_tag_present(skb)) { ++ if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) ++ && (adapter->hw.mng_cookie.status & ++ E1000_MNG_DHCP_COOKIE_STATUS_VLAN))) ++ return 0; ++ } ++ ++ if (skb->len <= MINIMUM_DHCP_PACKET_SIZE) ++ return 0; ++ ++ if (((struct ethhdr *) skb->data)->h_proto != htons(ETH_P_IP)) ++ return 0; ++ ++ { ++ const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data+14); ++ struct udphdr *udp; ++ ++ if (ip->protocol != IPPROTO_UDP) ++ return 0; ++ ++ udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2)); ++ if (ntohs(udp->dest) != 67) ++ return 0; ++ ++ offset = (u8 *)udp + 8 - skb->data; ++ length = skb->len - offset; ++ return e1000_mng_write_dhcp_info(hw, (u8 *)udp + 8, length); ++ } ++ ++ return 0; ++} ++ ++static int __e1000_maybe_stop_tx(struct net_device *netdev, int size) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ ++ netif_stop_queue(netdev); ++ /* Herbert's original patch had: ++ * smp_mb__after_netif_stop_queue(); ++ * but since that doesn't exist yet, just open code it. */ ++ smp_mb(); ++ ++ /* We need to check again in a case another CPU has just ++ * made room available. */ ++ if (e1000_desc_unused(adapter->tx_ring) < size) ++ return -EBUSY; ++ ++ /* A reprieve! */ ++ netif_start_queue(netdev); ++ ++adapter->restart_queue; ++ return 0; ++} ++ ++static int e1000_maybe_stop_tx(struct net_device *netdev, int size) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ ++ if (e1000_desc_unused(adapter->tx_ring) >= size) ++ return 0; ++ return __e1000_maybe_stop_tx(netdev, size); ++} ++ ++#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 ) ++static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ struct e1000_ring *tx_ring = adapter->tx_ring; ++ unsigned int first; ++ unsigned int max_per_txd = E1000_MAX_PER_TXD; ++ unsigned int max_txd_pwr = E1000_MAX_TXD_PWR; ++ unsigned int tx_flags = 0; ++ unsigned int len = skb->len; ++ unsigned long irq_flags; ++ unsigned int nr_frags = 0; ++ unsigned int mss = 0; ++ int count = 0; ++ int tso; ++ unsigned int f; ++ len -= skb->data_len; ++ ++ if (test_bit(__E1000_DOWN, &adapter->state)) { ++ dev_kfree_skb_any(skb); ++ return NETDEV_TX_OK; ++ } ++ ++ if (skb->len <= 0) { ++ dev_kfree_skb_any(skb); ++ return NETDEV_TX_OK; ++ } ++ ++ mss = skb_shinfo(skb)->gso_size; ++ /* The controller does a simple calculation to ++ * make sure there is enough room in the FIFO before ++ * initiating the DMA for each buffer. The calc is: ++ * 4 = ceil(buffer len/mss). To make sure we don't ++ * overrun the FIFO, adjust the max buffer len if mss ++ * drops. */ ++ if (mss) { ++ u8 hdr_len; ++ max_per_txd = min(mss << 2, max_per_txd); ++ max_txd_pwr = fls(max_per_txd) - 1; ++ ++ /* TSO Workaround for 82571/2/3 Controllers -- if skb->data ++ * points to just header, pull a few bytes of payload from ++ * frags into skb->data */ ++ hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); ++ if (skb->data_len && (hdr_len == (skb->len - skb->data_len))) { ++ unsigned int pull_size; ++ ++ pull_size = min((unsigned int)4, skb->data_len); ++ if (!__pskb_pull_tail(skb, pull_size)) { ++ ndev_err(netdev, ++ "__pskb_pull_tail failed.\n"); ++ dev_kfree_skb_any(skb); ++ return NETDEV_TX_OK; ++ } ++ len = skb->len - skb->data_len; ++ } ++ } ++ ++ /* reserve a descriptor for the offload context */ ++ if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL)) ++ count++; ++ count++; ++ ++ /* Controller Erratum workaround */ ++ if (!skb->data_len && tx_ring->last_tx_tso && !skb_is_gso(skb)) ++ count++; ++ ++ count += TXD_USE_COUNT(len, max_txd_pwr); ++ ++ nr_frags = skb_shinfo(skb)->nr_frags; ++ for (f = 0; f < nr_frags; f++) ++ count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size, ++ max_txd_pwr); ++ ++ if (adapter->hw.mac.tx_pkt_filtering) ++ e1000_transfer_dhcp_info(adapter, skb); ++ ++ if (!spin_trylock_irqsave(&adapter->tx_queue_lock, irq_flags)) ++ /* Collision - tell upper layer to requeue */ ++ return NETDEV_TX_LOCKED; ++ ++ /* need: count + 2 desc gap to keep tail from touching ++ * head, otherwise try next time */ ++ if (e1000_maybe_stop_tx(netdev, count + 2)) { ++ spin_unlock_irqrestore(&adapter->tx_queue_lock, irq_flags); ++ return NETDEV_TX_BUSY; ++ } ++ ++ if (adapter->vlgrp && vlan_tx_tag_present(skb)) { ++ tx_flags |= E1000_TX_FLAGS_VLAN; ++ tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT); ++ } ++ ++ first = tx_ring->next_to_use; ++ ++ tso = e1000_tso(adapter, skb); ++ if (tso < 0) { ++ dev_kfree_skb_any(skb); ++ spin_unlock_irqrestore(&adapter->tx_queue_lock, irq_flags); ++ return NETDEV_TX_OK; ++ } ++ ++ if (tso) { ++ tx_ring->last_tx_tso = 1; ++ tx_flags |= E1000_TX_FLAGS_TSO; ++ } else if (e1000_tx_csum(adapter, skb)) { ++ tx_flags |= E1000_TX_FLAGS_CSUM; ++ } ++ ++ /* Old method was to assume IPv4 packet by default if TSO was enabled. ++ * 82571 hardware supports TSO capabilities for IPv6 as well... ++ * no longer assume, we must. */ ++ if (skb->protocol == htons(ETH_P_IP)) ++ tx_flags |= E1000_TX_FLAGS_IPV4; ++ ++ e1000_tx_queue(adapter, tx_flags, ++ e1000_tx_map(adapter, skb, first, ++ max_per_txd, nr_frags, mss)); ++ ++ netdev->trans_start = jiffies; ++ ++ /* Make sure there is space in the ring for the next send. */ ++ e1000_maybe_stop_tx(netdev, MAX_SKB_FRAGS + 2); ++ ++ spin_unlock_irqrestore(&adapter->tx_queue_lock, irq_flags); ++ return NETDEV_TX_OK; ++} ++ ++/** ++ * e1000_tx_timeout - Respond to a Tx Hang ++ * @netdev: network interface device structure ++ **/ ++static void e1000_tx_timeout(struct net_device *netdev) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ ++ /* Do the reset outside of interrupt context */ ++ adapter->tx_timeout_count++; ++ schedule_work(&adapter->reset_task); ++} ++ ++static void e1000_reset_task(struct work_struct *work) ++{ ++ struct e1000_adapter *adapter; ++ adapter = container_of(work, struct e1000_adapter, reset_task); ++ ++ e1000_reinit_locked(adapter); ++} ++ ++/** ++ * e1000_get_stats - Get System Network Statistics ++ * @netdev: network interface device structure ++ * ++ * Returns the address of the device statistics structure. ++ * The statistics are actually updated from the timer callback. ++ **/ ++static struct net_device_stats *e1000_get_stats(struct net_device *netdev) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ ++ /* only return the current stats */ ++ return &adapter->net_stats; ++} ++ ++/** ++ * e1000_change_mtu - Change the Maximum Transfer Unit ++ * @netdev: network interface device structure ++ * @new_mtu: new value for maximum frame size ++ * ++ * Returns 0 on success, negative on failure ++ **/ ++static int e1000_change_mtu(struct net_device *netdev, int new_mtu) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; ++ ++ if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) || ++ (max_frame > MAX_JUMBO_FRAME_SIZE)) { ++ ndev_err(netdev, "Invalid MTU setting\n"); ++ return -EINVAL; ++ } ++ ++ /* Jumbo frame size limits */ ++ if (max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) { ++ if (!(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) { ++ ndev_err(netdev, "Jumbo Frames not supported.\n"); ++ return -EINVAL; ++ } ++ if (adapter->hw.phy.type == e1000_phy_ife) { ++ ndev_err(netdev, "Jumbo Frames not supported.\n"); ++ return -EINVAL; ++ } ++ } ++ ++#define MAX_STD_JUMBO_FRAME_SIZE 9234 ++ if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { ++ ndev_err(netdev, "MTU > 9216 not supported.\n"); ++ return -EINVAL; ++ } ++ ++ while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) ++ msleep(1); ++ /* e1000_down has a dependency on max_frame_size */ ++ adapter->hw.mac.max_frame_size = max_frame; ++ if (netif_running(netdev)) ++ e1000_down(adapter); ++ ++ /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN ++ * means we reserve 2 more, this pushes us to allocate from the next ++ * larger slab size. ++ * i.e. RXBUFFER_2048 --> size-4096 slab ++ * however with the new *_jumbo* routines, jumbo receives will use ++ * fragmented skbs */ ++ ++ if (max_frame <= 256) ++ adapter->rx_buffer_len = 256; ++ else if (max_frame <= 512) ++ adapter->rx_buffer_len = 512; ++ else if (max_frame <= 1024) ++ adapter->rx_buffer_len = 1024; ++ else if (max_frame <= 2048) ++ adapter->rx_buffer_len = 2048; ++ else ++ adapter->rx_buffer_len = 4096; ++ ++ /* adjust allocation if LPE protects us, and we aren't using SBP */ ++ if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) || ++ (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN)) ++ adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN ++ + ETH_FCS_LEN ; ++ ++ ndev_info(netdev, "changing MTU from %d to %d\n", ++ netdev->mtu, new_mtu); ++ netdev->mtu = new_mtu; ++ ++ if (netif_running(netdev)) ++ e1000_up(adapter); ++ else ++ e1000_reset(adapter); ++ ++ clear_bit(__E1000_RESETTING, &adapter->state); ++ ++ return 0; ++} ++ ++static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, ++ int cmd) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ struct mii_ioctl_data *data = if_mii(ifr); ++ unsigned long irq_flags; ++ ++ if (adapter->hw.media_type != e1000_media_type_copper) ++ return -EOPNOTSUPP; ++ ++ switch (cmd) { ++ case SIOCGMIIPHY: ++ data->phy_id = adapter->hw.phy.addr; ++ break; ++ case SIOCGMIIREG: ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ spin_lock_irqsave(&adapter->stats_lock, irq_flags); ++ if (e1e_rphy(&adapter->hw, data->reg_num & 0x1F, ++ &data->val_out)) { ++ spin_unlock_irqrestore(&adapter->stats_lock, irq_flags); ++ return -EIO; ++ } ++ spin_unlock_irqrestore(&adapter->stats_lock, irq_flags); ++ break; ++ case SIOCSMIIREG: ++ default: ++ return -EOPNOTSUPP; ++ } ++ return E1000_SUCCESS; ++} ++ ++static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) ++{ ++ switch (cmd) { ++ case SIOCGMIIPHY: ++ case SIOCGMIIREG: ++ case SIOCSMIIREG: ++ return e1000_mii_ioctl(netdev, ifr, cmd); ++ default: ++ return -EOPNOTSUPP; ++ } ++} ++ ++static int e1000_suspend(struct pci_dev *pdev, pm_message_t state) ++{ ++ struct net_device *netdev = pci_get_drvdata(pdev); ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ struct e1000_hw *hw = &adapter->hw; ++ u32 ctrl, ctrl_ext, rctl, status; ++ u32 wufc = adapter->wol; ++ int retval = 0; ++ ++ netif_device_detach(netdev); ++ ++ if (netif_running(netdev)) { ++ WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); ++ e1000_down(adapter); ++ e1000_free_irq(adapter); ++ } ++ ++ retval = pci_save_state(pdev); ++ if (retval) ++ return retval; ++ ++ status = er32(STATUS); ++ if (status & E1000_STATUS_LU) ++ wufc &= ~E1000_WUFC_LNKC; ++ ++ if (wufc) { ++ e1000_setup_rctl(adapter); ++ e1000_set_multi(netdev); ++ ++ /* turn on all-multi mode if wake on multicast is enabled */ ++ if (wufc & E1000_WUFC_MC) { ++ rctl = er32(RCTL); ++ rctl |= E1000_RCTL_MPE; ++ ew32(RCTL, rctl); ++ } ++ ++ ctrl = er32(CTRL); ++ /* advertise wake from D3Cold */ ++ #define E1000_CTRL_ADVD3WUC 0x00100000 ++ /* phy power management enable */ ++ #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 ++ ctrl |= E1000_CTRL_ADVD3WUC | ++ E1000_CTRL_EN_PHY_PWR_MGMT; ++ ew32(CTRL, ctrl); ++ ++ if (adapter->hw.media_type == e1000_media_type_fiber || ++ adapter->hw.media_type == e1000_media_type_internal_serdes) { ++ /* keep the laser running in D3 */ ++ ctrl_ext = er32(CTRL_EXT); ++ ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA; ++ ew32(CTRL_EXT, ctrl_ext); ++ } ++ ++ /* Allow time for pending master requests to run */ ++ e1000_disable_pcie_master(&adapter->hw); ++ ++ ew32(WUC, E1000_WUC_PME_EN); ++ ew32(WUFC, wufc); ++ pci_enable_wake(pdev, PCI_D3hot, 1); ++ pci_enable_wake(pdev, PCI_D3cold, 1); ++ } else { ++ ew32(WUC, 0); ++ ew32(WUFC, 0); ++ pci_enable_wake(pdev, PCI_D3hot, 0); ++ pci_enable_wake(pdev, PCI_D3cold, 0); ++ } ++ ++ e1000_release_manageability(adapter); ++ ++ /* make sure adapter isn't asleep if manageability is enabled */ ++ if (adapter->flags & FLAG_MNG_PT_ENABLED) { ++ pci_enable_wake(pdev, PCI_D3hot, 1); ++ pci_enable_wake(pdev, PCI_D3cold, 1); ++ } ++ ++ if (adapter->hw.phy.type == e1000_phy_igp_3) ++ e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); ++ ++ /* Release control of h/w to f/w. If f/w is AMT enabled, this ++ * would have already happened in close and is redundant. */ ++ e1000_release_hw_control(adapter); ++ ++ pci_disable_device(pdev); ++ ++ pci_set_power_state(pdev, pci_choose_state(pdev, state)); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int e1000_resume(struct pci_dev *pdev) ++{ ++ struct net_device *netdev = pci_get_drvdata(pdev); ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ struct e1000_hw *hw = &adapter->hw; ++ u32 err; ++ ++ pci_set_power_state(pdev, PCI_D0); ++ pci_restore_state(pdev); ++ err = pci_enable_device(pdev); ++ if (err) { ++ dev_err(&pdev->dev, ++ "Cannot enable PCI device from suspend\n"); ++ return err; ++ } ++ ++ pci_set_master(pdev); ++ ++ pci_enable_wake(pdev, PCI_D3hot, 0); ++ pci_enable_wake(pdev, PCI_D3cold, 0); ++ ++ if (netif_running(netdev)) { ++ err = e1000_request_irq(adapter); ++ if (err) ++ return err; ++ } ++ ++ e1000_power_up_phy(adapter); ++ e1000_reset(adapter); ++ ew32(WUS, ~0); ++ ++ e1000_init_manageability(adapter); ++ ++ if (netif_running(netdev)) ++ e1000_up(adapter); ++ ++ netif_device_attach(netdev); ++ ++ /* If the controller has AMT, do not set DRV_LOAD until the interface ++ * is up. For all other cases, let the f/w know that the h/w is now ++ * under the control of the driver. */ ++ if (!(adapter->flags & FLAG_HAS_AMT) || !e1000_check_mng_mode(&adapter->hw)) ++ e1000_get_hw_control(adapter); ++ ++ return 0; ++} ++#endif ++ ++static void e1000_shutdown(struct pci_dev *pdev) ++{ ++ e1000_suspend(pdev, PMSG_SUSPEND); ++} ++ ++#ifdef CONFIG_NET_POLL_CONTROLLER ++/* ++ * Polling 'interrupt' - used by things like netconsole to send skbs ++ * without having to re-enable interrupts. It's not called while ++ * the interrupt routine is executing. ++ */ ++static void e1000_netpoll(struct net_device *netdev) ++{ ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ ++ disable_irq(adapter->pdev->irq); ++ e1000_intr(adapter->pdev->irq, netdev); ++ ++ e1000_clean_tx_irq(adapter); ++ ++ enable_irq(adapter->pdev->irq); ++} ++#endif ++ ++/** ++ * e1000_io_error_detected - called when PCI error is detected ++ * @pdev: Pointer to PCI device ++ * @state: The current pci connection state ++ * ++ * This function is called after a PCI bus error affecting ++ * this device has been detected. ++ */ ++static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, ++ pci_channel_state_t state) ++{ ++ struct net_device *netdev = pci_get_drvdata(pdev); ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ ++ netif_device_detach(netdev); ++ ++ if (netif_running(netdev)) ++ e1000_down(adapter); ++ pci_disable_device(pdev); ++ ++ /* Request a slot slot reset. */ ++ return PCI_ERS_RESULT_NEED_RESET; ++} ++ ++/** ++ * e1000_io_slot_reset - called after the pci bus has been reset. ++ * @pdev: Pointer to PCI device ++ * ++ * Restart the card from scratch, as if from a cold-boot. Implementation ++ * resembles the first-half of the e1000_resume routine. ++ */ ++static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev) ++{ ++ struct net_device *netdev = pci_get_drvdata(pdev); ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ struct e1000_hw *hw = &adapter->hw; ++ ++ if (pci_enable_device(pdev)) { ++ dev_err(&pdev->dev, ++ "Cannot re-enable PCI device after reset.\n"); ++ return PCI_ERS_RESULT_DISCONNECT; ++ } ++ pci_set_master(pdev); ++ ++ pci_enable_wake(pdev, PCI_D3hot, 0); ++ pci_enable_wake(pdev, PCI_D3cold, 0); ++ ++ e1000_reset(adapter); ++ ew32(WUS, ~0); ++ ++ return PCI_ERS_RESULT_RECOVERED; ++} ++ ++/** ++ * e1000_io_resume - called when traffic can start flowing again. ++ * @pdev: Pointer to PCI device ++ * ++ * This callback is called when the error recovery driver tells us that ++ * its OK to resume normal operation. Implementation resembles the ++ * second-half of the e1000_resume routine. ++ */ ++static void e1000_io_resume(struct pci_dev *pdev) ++{ ++ struct net_device *netdev = pci_get_drvdata(pdev); ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ ++ e1000_init_manageability(adapter); ++ ++ if (netif_running(netdev)) { ++ if (e1000_up(adapter)) { ++ dev_err(&pdev->dev, ++ "can't bring device back up after reset\n"); ++ return; ++ } ++ } ++ ++ netif_device_attach(netdev); ++ ++ /* If the controller has AMT, do not set DRV_LOAD until the interface ++ * is up. For all other cases, let the f/w know that the h/w is now ++ * under the control of the driver. */ ++ if (!(adapter->flags & FLAG_HAS_AMT) || ++ !e1000_check_mng_mode(&adapter->hw)) ++ e1000_get_hw_control(adapter); ++ ++} ++ ++static void e1000_print_device_info(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ struct net_device *netdev = adapter->netdev; ++ ++ /* print bus type/speed/width info */ ++ ndev_info(netdev, "(PCI Express:2.5GB/s:%s) " ++ "%02x:%02x:%02x:%02x:%02x:%02x\n", ++ /* bus width */ ++ ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : ++ "Width x1"), ++ /* MAC address */ ++ netdev->dev_addr[0], netdev->dev_addr[1], ++ netdev->dev_addr[2], netdev->dev_addr[3], ++ netdev->dev_addr[4], netdev->dev_addr[5]); ++ ndev_info(netdev, "Intel(R) PRO/%s Network Connection\n", ++ (hw->phy.type == e1000_phy_ife) ++ ? "10/100" : "1000"); ++} ++ ++/** ++ * e1000_probe - Device Initialization Routine ++ * @pdev: PCI device information struct ++ * @ent: entry in e1000_pci_tbl ++ * ++ * Returns 0 on success, negative on failure ++ * ++ * e1000_probe initializes an adapter identified by a pci_dev structure. ++ * The OS initialization, configuring of the adapter private structure, ++ * and a hardware reset occur. ++ **/ ++static int __devinit e1000_probe(struct pci_dev *pdev, ++ const struct pci_device_id *ent) ++{ ++ struct net_device *netdev; ++ struct e1000_adapter *adapter; ++ struct e1000_hw *hw; ++ const struct e1000_info *ei = e1000_info_tbl[ent->driver_data]; ++ unsigned long mmio_start, mmio_len; ++ unsigned long flash_start, flash_len; ++ ++ static int cards_found; ++ int i, err, pci_using_dac; ++ u16 eeprom_data = 0; ++ u16 eeprom_apme_mask = E1000_EEPROM_APME; ++ ++ err = pci_enable_device(pdev); ++ if (err) ++ return err; ++ ++ pci_using_dac = 0; ++ err = pci_set_dma_mask(pdev, DMA_64BIT_MASK); ++ if (!err) { ++ err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); ++ if (!err) ++ pci_using_dac = 1; ++ } else { ++ err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); ++ if (err) { ++ err = pci_set_consistent_dma_mask(pdev, ++ DMA_32BIT_MASK); ++ if (err) { ++ dev_err(&pdev->dev, "No usable DMA " ++ "configuration, aborting\n"); ++ goto err_dma; ++ } ++ } ++ } ++ ++ err = pci_request_regions(pdev, e1000_driver_name); ++ if (err) ++ goto err_pci_reg; ++ ++ pci_set_master(pdev); ++ ++ err = -ENOMEM; ++ netdev = alloc_etherdev(sizeof(struct e1000_adapter)); ++ if (!netdev) ++ goto err_alloc_etherdev; ++ ++ SET_MODULE_OWNER(netdev); ++ SET_NETDEV_DEV(netdev, &pdev->dev); ++ ++ pci_set_drvdata(pdev, netdev); ++ adapter = netdev_priv(netdev); ++ hw = &adapter->hw; ++ adapter->netdev = netdev; ++ adapter->pdev = pdev; ++ adapter->ei = ei; ++ adapter->pba = ei->pba; ++ adapter->flags = ei->flags; ++ adapter->hw.adapter = adapter; ++ adapter->hw.mac.type = ei->mac; ++ adapter->msg_enable = (1 << NETIF_MSG_DRV | NETIF_MSG_PROBE) - 1; ++ ++ mmio_start = pci_resource_start(pdev, 0); ++ mmio_len = pci_resource_len(pdev, 0); ++ ++ err = -EIO; ++ adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); ++ if (!adapter->hw.hw_addr) ++ goto err_ioremap; ++ ++ if ((adapter->flags & FLAG_HAS_FLASH) && ++ (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) { ++ flash_start = pci_resource_start(pdev, 1); ++ flash_len = pci_resource_len(pdev, 1); ++ adapter->hw.flash_address = ioremap(flash_start, flash_len); ++ if (!adapter->hw.flash_address) ++ goto err_flashmap; ++ } ++ ++ /* construct the net_device struct */ ++ netdev->open = &e1000_open; ++ netdev->stop = &e1000_close; ++ netdev->hard_start_xmit = &e1000_xmit_frame; ++ netdev->get_stats = &e1000_get_stats; ++ netdev->set_multicast_list = &e1000_set_multi; ++ netdev->set_mac_address = &e1000_set_mac; ++ netdev->change_mtu = &e1000_change_mtu; ++ netdev->do_ioctl = &e1000_ioctl; ++ e1000_set_ethtool_ops(netdev); ++ netdev->tx_timeout = &e1000_tx_timeout; ++ netdev->watchdog_timeo = 5 * HZ; ++ netdev->poll = &e1000_clean; ++ netdev->weight = 64; ++ netdev->vlan_rx_register = e1000_vlan_rx_register; ++ netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid; ++ netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid; ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ netdev->poll_controller = e1000_netpoll; ++#endif ++ strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); ++ ++ netdev->mem_start = mmio_start; ++ netdev->mem_end = mmio_start + mmio_len; ++ ++ adapter->bd_number = cards_found++; ++ ++ /* setup adapter struct */ ++ err = e1000_sw_init(adapter); ++ if (err) ++ goto err_sw_init; ++ ++ err = -EIO; ++ ++ memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); ++ memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); ++ memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); ++ ++ err = ei->get_invariants(adapter); ++ if (err) ++ goto err_hw_init; ++ ++ hw->mac.ops.get_bus_info(&adapter->hw); ++ ++ adapter->hw.phy.wait_for_link = 0; ++ ++ /* Copper options */ ++ if (adapter->hw.media_type == e1000_media_type_copper) { ++ adapter->hw.phy.mdix = AUTO_ALL_MODES; ++ adapter->hw.phy.disable_polarity_correction = 0; ++ adapter->hw.phy.ms_type = e1000_ms_hw_default; ++ } ++ ++ if (e1000_check_reset_block(&adapter->hw)) ++ ndev_info(netdev, ++ "PHY reset is blocked due to SOL/IDER session.\n"); ++ ++ netdev->features = NETIF_F_SG | ++ NETIF_F_HW_CSUM | ++ NETIF_F_HW_VLAN_TX | ++ NETIF_F_HW_VLAN_RX; ++ ++ if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) ++ netdev->features |= NETIF_F_HW_VLAN_FILTER; ++ ++ netdev->features |= NETIF_F_TSO; ++ netdev->features |= NETIF_F_TSO6; ++ ++ if (pci_using_dac) ++ netdev->features |= NETIF_F_HIGHDMA; ++ ++ /* We should not be using LLTX anymore, but we are still TX faster with ++ * it. */ ++ netdev->features |= NETIF_F_LLTX; ++ ++ if (e1000_enable_mng_pass_thru(&adapter->hw)) ++ adapter->flags |= FLAG_MNG_PT_ENABLED; ++ ++ /* before reading the NVM, reset the controller to ++ * put the device in a known good starting state */ ++ adapter->hw.mac.ops.reset_hw(&adapter->hw); ++ ++ /* ++ * systems with ASPM and others may see the checksum fail on the first ++ * attempt. Let's give it a few tries ++ */ ++ for (i = 0;; i++) { ++ if (e1000_validate_nvm_checksum(&adapter->hw) >= 0) ++ break; ++ if (i == 2) { ++ ndev_err(netdev, "The NVM Checksum Is Not Valid\n"); ++ err = -EIO; ++ goto err_eeprom; ++ } ++ } ++ ++ /* copy the MAC address out of the NVM */ ++ if (e1000_read_mac_addr(&adapter->hw)) ++ ndev_err(netdev, "NVM Read Error while reading MAC address\n"); ++ ++ memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len); ++ memcpy(netdev->perm_addr, adapter->hw.mac.addr, netdev->addr_len); ++ ++ if (!is_valid_ether_addr(netdev->perm_addr)) { ++ ndev_err(netdev, "Invalid MAC Address: " ++ "%02x:%02x:%02x:%02x:%02x:%02x\n", ++ netdev->perm_addr[0], netdev->perm_addr[1], ++ netdev->perm_addr[2], netdev->perm_addr[3], ++ netdev->perm_addr[4], netdev->perm_addr[5]); ++ err = -EIO; ++ goto err_eeprom; ++ } ++ ++ init_timer(&adapter->watchdog_timer); ++ adapter->watchdog_timer.function = &e1000_watchdog; ++ adapter->watchdog_timer.data = (unsigned long) adapter; ++ ++ init_timer(&adapter->phy_info_timer); ++ adapter->phy_info_timer.function = &e1000_update_phy_info; ++ adapter->phy_info_timer.data = (unsigned long) adapter; ++ ++ INIT_WORK(&adapter->reset_task, e1000_reset_task); ++ INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task); ++ ++ e1000_check_options(adapter); ++ ++ /* Initialize link parameters. User can change them with ethtool */ ++ adapter->hw.mac.autoneg = 1; ++ adapter->hw.mac.original_fc = e1000_fc_default; ++ adapter->hw.mac.fc = e1000_fc_default; ++ adapter->hw.phy.autoneg_advertised = 0x2f; ++ ++ /* ring size defaults */ ++ adapter->rx_ring->count = 256; ++ adapter->tx_ring->count = 256; ++ ++ /* ++ * Initial Wake on LAN setting - If APM wake is enabled in ++ * the EEPROM, enable the ACPI Magic Packet filter ++ */ ++ if (adapter->flags & FLAG_APME_IN_WUC) { ++ /* APME bit in EEPROM is mapped to WUC.APME */ ++ eeprom_data = er32(WUC); ++ eeprom_apme_mask = E1000_WUC_APME; ++ } else if (adapter->flags & FLAG_APME_IN_CTRL3) { ++ if (adapter->flags & FLAG_APME_CHECK_PORT_B && ++ (adapter->hw.bus.func == 1)) ++ e1000_read_nvm(&adapter->hw, ++ NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); ++ else ++ e1000_read_nvm(&adapter->hw, ++ NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); ++ } ++ ++ /* fetch WoL from EEPROM */ ++ if (eeprom_data & eeprom_apme_mask) ++ adapter->eeprom_wol |= E1000_WUFC_MAG; ++ ++ /* ++ * now that we have the eeprom settings, apply the special cases ++ * where the eeprom may be wrong or the board simply won't support ++ * wake on lan on a particular port ++ */ ++ if (!(adapter->flags & FLAG_HAS_WOL)) ++ adapter->eeprom_wol = 0; ++ ++ /* initialize the wol settings based on the eeprom settings */ ++ adapter->wol = adapter->eeprom_wol; ++ ++ /* reset the hardware with the new settings */ ++ e1000_reset(adapter); ++ ++ /* If the controller has AMT, do not set DRV_LOAD until the interface ++ * is up. For all other cases, let the f/w know that the h/w is now ++ * under the control of the driver. */ ++ if (!(adapter->flags & FLAG_HAS_AMT) || ++ !e1000_check_mng_mode(&adapter->hw)) ++ e1000_get_hw_control(adapter); ++ ++ /* tell the stack to leave us alone until e1000_open() is called */ ++ netif_carrier_off(netdev); ++ netif_stop_queue(netdev); ++ netif_poll_disable(netdev); ++ ++ strcpy(netdev->name, "eth%d"); ++ err = register_netdev(netdev); ++ if (err) ++ goto err_register; ++ ++ e1000_print_device_info(adapter); ++ ++ return 0; ++ ++err_register: ++err_hw_init: ++ e1000_release_hw_control(adapter); ++err_eeprom: ++ if (!e1000_check_reset_block(&adapter->hw)) ++ e1000_phy_hw_reset(&adapter->hw); ++ ++ if (adapter->hw.flash_address) ++ iounmap(adapter->hw.flash_address); ++ ++err_flashmap: ++ kfree(adapter->tx_ring); ++ kfree(adapter->rx_ring); ++err_sw_init: ++ iounmap(adapter->hw.hw_addr); ++err_ioremap: ++ free_netdev(netdev); ++err_alloc_etherdev: ++ pci_release_regions(pdev); ++err_pci_reg: ++err_dma: ++ pci_disable_device(pdev); ++ return err; ++} ++ ++/** ++ * e1000_remove - Device Removal Routine ++ * @pdev: PCI device information struct ++ * ++ * e1000_remove is called by the PCI subsystem to alert the driver ++ * that it should release a PCI device. The could be caused by a ++ * Hot-Plug event, or because the driver is going to be removed from ++ * memory. ++ **/ ++static void __devexit e1000_remove(struct pci_dev *pdev) ++{ ++ struct net_device *netdev = pci_get_drvdata(pdev); ++ struct e1000_adapter *adapter = netdev_priv(netdev); ++ ++ /* flush_scheduled work may reschedule our watchdog task, so ++ * explicitly disable watchdog tasks from being rescheduled */ ++ set_bit(__E1000_DOWN, &adapter->state); ++ del_timer_sync(&adapter->watchdog_timer); ++ del_timer_sync(&adapter->phy_info_timer); ++ ++ flush_scheduled_work(); ++ ++ e1000_release_manageability(adapter); ++ ++ /* Release control of h/w to f/w. If f/w is AMT enabled, this ++ * would have already happened in close and is redundant. */ ++ e1000_release_hw_control(adapter); ++ ++ unregister_netdev(netdev); ++ ++ if (!e1000_check_reset_block(&adapter->hw)) ++ e1000_phy_hw_reset(&adapter->hw); ++ ++ kfree(adapter->tx_ring); ++ kfree(adapter->rx_ring); ++ ++ iounmap(adapter->hw.hw_addr); ++ if (adapter->hw.flash_address) ++ iounmap(adapter->hw.flash_address); ++ pci_release_regions(pdev); ++ ++ free_netdev(netdev); ++ ++ pci_disable_device(pdev); ++} ++ ++/* PCI Error Recovery (ERS) */ ++static struct pci_error_handlers e1000_err_handler = { ++ .error_detected = e1000_io_error_detected, ++ .slot_reset = e1000_io_slot_reset, ++ .resume = e1000_io_resume, ++}; ++ ++static struct pci_device_id e1000e_pci_tbl[] = { ++ /* ++ * Support for 82571/2/3, es2lan and ich8 will be phased in ++ * stepwise. ++ ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), board_82571 }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT), ++ board_80003es2lan }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT), ++ board_80003es2lan }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT), ++ board_80003es2lan }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT), ++ board_80003es2lan }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan }, ++ */ ++ ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan }, ++ ++ { } /* terminate list */ ++}; ++MODULE_DEVICE_TABLE(pci, e1000e_pci_tbl); ++ ++/* PCI Device API Driver */ ++static struct pci_driver e1000_driver = { ++ .name = e1000_driver_name, ++ .id_table = e1000e_pci_tbl, ++ .probe = e1000_probe, ++ .remove = __devexit_p(e1000_remove), ++#ifdef CONFIG_PM ++ /* Power Managment Hooks */ ++ .suspend = e1000_suspend, ++ .resume = e1000_resume, ++#endif ++ .shutdown = e1000_shutdown, ++ .err_handler = &e1000_err_handler ++}; ++ ++/** ++ * e1000_init_module - Driver Registration Routine ++ * ++ * e1000_init_module is the first routine called when the driver is ++ * loaded. All it does is register with the PCI subsystem. ++ **/ ++static int __init e1000e_init_module(void) ++{ ++ int ret; ++ printk(KERN_INFO "Intel(R) PRO/1000 Network Driver - %s\n", ++ e1000_driver_version); ++ printk(KERN_INFO "Copyright (c) 1999-2007 Intel Corporation.\n"); ++ ret = pci_register_driver(&e1000_driver); ++ ++ return ret; ++} ++module_init(e1000e_init_module); ++ ++/** ++ * e1000_exit_module - Driver Exit Cleanup Routine ++ * ++ * e1000_exit_module is called just before the driver is removed ++ * from memory. ++ **/ ++static void __exit e1000e_exit_module(void) ++{ ++ pci_unregister_driver(&e1000_driver); ++} ++module_exit(e1000e_exit_module); ++ ++ ++MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); ++MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver"); ++MODULE_LICENSE("GPL"); ++MODULE_VERSION(DRV_VERSION); ++ ++/* e1000_main.c */ +diff --git a/drivers/net/e1000e/param.c b/drivers/net/e1000e/param.c +new file mode 100644 +index 0000000..9a70d22 +--- /dev/null ++++ b/drivers/net/e1000e/param.c +@@ -0,0 +1,382 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2007 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS <linux.nics@intel.com> ++ e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#include <linux/netdevice.h> ++ ++#include "e1000.h" ++ ++/* This is the only thing that needs to be changed to adjust the ++ * maximum number of ports that the driver can manage. ++ */ ++ ++#define E1000_MAX_NIC 32 ++ ++#define OPTION_UNSET -1 ++#define OPTION_DISABLED 0 ++#define OPTION_ENABLED 1 ++ ++#define COPYBREAK_DEFAULT 256 ++unsigned int copybreak = COPYBREAK_DEFAULT; ++module_param(copybreak, uint, 0644); ++MODULE_PARM_DESC(copybreak, ++ "Maximum size of packet that is copied to a new buffer on receive"); ++ ++/* All parameters are treated the same, as an integer array of values. ++ * This macro just reduces the need to repeat the same declaration code ++ * over and over (plus this helps to avoid typo bugs). ++ */ ++ ++#define E1000_PARAM_INIT { [0 ... E1000_MAX_NIC] = OPTION_UNSET } ++#define E1000_PARAM(X, desc) \ ++ static int __devinitdata X[E1000_MAX_NIC+1] = E1000_PARAM_INIT; \ ++ static int num_##X; \ ++ module_param_array_named(X, X, int, &num_##X, 0); \ ++ MODULE_PARM_DESC(X, desc); ++ ++ ++/* Transmit Interrupt Delay in units of 1.024 microseconds ++ * Tx interrupt delay needs to typically be set to something non zero ++ * ++ * Valid Range: 0-65535 ++ */ ++E1000_PARAM(TxIntDelay, "Transmit Interrupt Delay"); ++#define DEFAULT_TIDV 8 ++#define MAX_TXDELAY 0xFFFF ++#define MIN_TXDELAY 0 ++ ++/* Transmit Absolute Interrupt Delay in units of 1.024 microseconds ++ * ++ * Valid Range: 0-65535 ++ */ ++E1000_PARAM(TxAbsIntDelay, "Transmit Absolute Interrupt Delay"); ++#define DEFAULT_TADV 32 ++#define MAX_TXABSDELAY 0xFFFF ++#define MIN_TXABSDELAY 0 ++ ++/* Receive Interrupt Delay in units of 1.024 microseconds ++ * hardware will likely hang if you set this to anything but zero. ++ * ++ * Valid Range: 0-65535 ++ */ ++E1000_PARAM(RxIntDelay, "Receive Interrupt Delay"); ++#define DEFAULT_RDTR 0 ++#define MAX_RXDELAY 0xFFFF ++#define MIN_RXDELAY 0 ++ ++/* Receive Absolute Interrupt Delay in units of 1.024 microseconds ++ * ++ * Valid Range: 0-65535 ++ */ ++E1000_PARAM(RxAbsIntDelay, "Receive Absolute Interrupt Delay"); ++#define DEFAULT_RADV 8 ++#define MAX_RXABSDELAY 0xFFFF ++#define MIN_RXABSDELAY 0 ++ ++/* Interrupt Throttle Rate (interrupts/sec) ++ * ++ * Valid Range: 100-100000 (0=off, 1=dynamic, 3=dynamic conservative) ++ */ ++E1000_PARAM(InterruptThrottleRate, "Interrupt Throttling Rate"); ++#define DEFAULT_ITR 3 ++#define MAX_ITR 100000 ++#define MIN_ITR 100 ++ ++/* Enable Smart Power Down of the PHY ++ * ++ * Valid Range: 0, 1 ++ * ++ * Default Value: 0 (disabled) ++ */ ++E1000_PARAM(SmartPowerDownEnable, "Enable PHY smart power down"); ++ ++/* Enable Kumeran Lock Loss workaround ++ * ++ * Valid Range: 0, 1 ++ * ++ * Default Value: 1 (enabled) ++ */ ++E1000_PARAM(KumeranLockLoss, "Enable Kumeran lock loss workaround"); ++ ++struct e1000_option { ++ enum { enable_option, range_option, list_option } type; ++ char *name; ++ char *err; ++ int def; ++ union { ++ struct { /* range_option info */ ++ int min; ++ int max; ++ } r; ++ struct { /* list_option info */ ++ int nr; ++ struct e1000_opt_list { int i; char *str; } *p; ++ } l; ++ } arg; ++}; ++ ++static int __devinit e1000_validate_option(int *value, ++ struct e1000_option *opt, ++ struct e1000_adapter *adapter) ++{ ++ if (*value == OPTION_UNSET) { ++ *value = opt->def; ++ return 0; ++ } ++ ++ switch (opt->type) { ++ case enable_option: ++ switch (*value) { ++ case OPTION_ENABLED: ++ ndev_info(adapter->netdev, "%s Enabled\n", opt->name); ++ return 0; ++ case OPTION_DISABLED: ++ ndev_info(adapter->netdev, "%s Disabled\n", opt->name); ++ return 0; ++ } ++ break; ++ case range_option: ++ if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) { ++ ndev_info(adapter->netdev, ++ "%s set to %i\n", opt->name, *value); ++ return 0; ++ } ++ break; ++ case list_option: { ++ int i; ++ struct e1000_opt_list *ent; ++ ++ for (i = 0; i < opt->arg.l.nr; i++) { ++ ent = &opt->arg.l.p[i]; ++ if (*value == ent->i) { ++ if (ent->str[0] != '\0') ++ ndev_info(adapter->netdev, "%s\n", ++ ent->str); ++ return 0; ++ } ++ } ++ } ++ break; ++ default: ++ BUG(); ++ } ++ ++ ndev_info(adapter->netdev, "Invalid %s value specified (%i) %s\n", ++ opt->name, *value, opt->err); ++ *value = opt->def; ++ return -1; ++} ++ ++/** ++ * e1000_check_options - Range Checking for Command Line Parameters ++ * @adapter: board private structure ++ * ++ * This routine checks all command line parameters for valid user ++ * input. If an invalid value is given, or if no user specified ++ * value exists, a default value is used. The final value is stored ++ * in a variable in the adapter structure. ++ **/ ++void __devinit e1000_check_options(struct e1000_adapter *adapter) ++{ ++ struct e1000_hw *hw = &adapter->hw; ++ struct net_device *netdev = adapter->netdev; ++ int bd = adapter->bd_number; ++ ++ if (bd >= E1000_MAX_NIC) { ++ ndev_notice(netdev, ++ "Warning: no configuration for board #%i\n", bd); ++ ndev_notice(netdev, "Using defaults for all values\n"); ++ } ++ ++ { /* Transmit Interrupt Delay */ ++ struct e1000_option opt = { ++ .type = range_option, ++ .name = "Transmit Interrupt Delay", ++ .err = "using default of " ++ __MODULE_STRING(DEFAULT_TIDV), ++ .def = DEFAULT_TIDV, ++ .arg = { .r = { .min = MIN_TXDELAY, ++ .max = MAX_TXDELAY } } ++ }; ++ ++ if (num_TxIntDelay > bd) { ++ adapter->tx_int_delay = TxIntDelay[bd]; ++ e1000_validate_option(&adapter->tx_int_delay, &opt, ++ adapter); ++ } else { ++ adapter->tx_int_delay = opt.def; ++ } ++ } ++ { /* Transmit Absolute Interrupt Delay */ ++ struct e1000_option opt = { ++ .type = range_option, ++ .name = "Transmit Absolute Interrupt Delay", ++ .err = "using default of " ++ __MODULE_STRING(DEFAULT_TADV), ++ .def = DEFAULT_TADV, ++ .arg = { .r = { .min = MIN_TXABSDELAY, ++ .max = MAX_TXABSDELAY } } ++ }; ++ ++ if (num_TxAbsIntDelay > bd) { ++ adapter->tx_abs_int_delay = TxAbsIntDelay[bd]; ++ e1000_validate_option(&adapter->tx_abs_int_delay, &opt, ++ adapter); ++ } else { ++ adapter->tx_abs_int_delay = opt.def; ++ } ++ } ++ { /* Receive Interrupt Delay */ ++ struct e1000_option opt = { ++ .type = range_option, ++ .name = "Receive Interrupt Delay", ++ .err = "using default of " ++ __MODULE_STRING(DEFAULT_RDTR), ++ .def = DEFAULT_RDTR, ++ .arg = { .r = { .min = MIN_RXDELAY, ++ .max = MAX_RXDELAY } } ++ }; ++ ++ /* modify min and default if 82573 for slow ping w/a, ++ * a value greater than 8 needs to be set for RDTR */ ++ if (adapter->flags & FLAG_HAS_ASPM) { ++ opt.def = 32; ++ opt.arg.r.min = 8; ++ } ++ ++ if (num_RxIntDelay > bd) { ++ adapter->rx_int_delay = RxIntDelay[bd]; ++ e1000_validate_option(&adapter->rx_int_delay, &opt, ++ adapter); ++ } else { ++ adapter->rx_int_delay = opt.def; ++ } ++ } ++ { /* Receive Absolute Interrupt Delay */ ++ struct e1000_option opt = { ++ .type = range_option, ++ .name = "Receive Absolute Interrupt Delay", ++ .err = "using default of " ++ __MODULE_STRING(DEFAULT_RADV), ++ .def = DEFAULT_RADV, ++ .arg = { .r = { .min = MIN_RXABSDELAY, ++ .max = MAX_RXABSDELAY } } ++ }; ++ ++ if (num_RxAbsIntDelay > bd) { ++ adapter->rx_abs_int_delay = RxAbsIntDelay[bd]; ++ e1000_validate_option(&adapter->rx_abs_int_delay, &opt, ++ adapter); ++ } else { ++ adapter->rx_abs_int_delay = opt.def; ++ } ++ } ++ { /* Interrupt Throttling Rate */ ++ struct e1000_option opt = { ++ .type = range_option, ++ .name = "Interrupt Throttling Rate (ints/sec)", ++ .err = "using default of " ++ __MODULE_STRING(DEFAULT_ITR), ++ .def = DEFAULT_ITR, ++ .arg = { .r = { .min = MIN_ITR, ++ .max = MAX_ITR } } ++ }; ++ ++ if (num_InterruptThrottleRate > bd) { ++ adapter->itr = InterruptThrottleRate[bd]; ++ switch (adapter->itr) { ++ case 0: ++ ndev_info(netdev, "%s turned off\n", ++ opt.name); ++ break; ++ case 1: ++ ndev_info(netdev, ++ "%s set to dynamic mode\n", ++ opt.name); ++ adapter->itr_setting = adapter->itr; ++ adapter->itr = 20000; ++ break; ++ case 3: ++ ndev_info(netdev, ++ "%s set to dynamic conservative mode\n", ++ opt.name); ++ adapter->itr_setting = adapter->itr; ++ adapter->itr = 20000; ++ break; ++ default: ++ e1000_validate_option(&adapter->itr, &opt, ++ adapter); ++ /* ++ * save the setting, because the dynamic bits ++ * change itr. clear the lower two bits ++ * because they are used as control ++ */ ++ adapter->itr_setting = adapter->itr & ~3; ++ break; ++ } ++ } else { ++ adapter->itr_setting = opt.def; ++ adapter->itr = 20000; ++ } ++ } ++ { /* Smart Power Down */ ++ struct e1000_option opt = { ++ .type = enable_option, ++ .name = "PHY Smart Power Down", ++ .err = "defaulting to Disabled", ++ .def = OPTION_DISABLED ++ }; ++ ++ if (num_SmartPowerDownEnable > bd) { ++ int spd = SmartPowerDownEnable[bd]; ++ e1000_validate_option(&spd, &opt, adapter); ++ if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) ++ && spd) ++ adapter->flags |= FLAG_SMART_POWER_DOWN; ++ } ++ } ++ { /* Kumeran Lock Loss Workaround */ ++ struct e1000_option opt = { ++ .type = enable_option, ++ .name = "Kumeran Lock Loss Workaround", ++ .err = "defaulting to Enabled", ++ .def = OPTION_ENABLED ++ }; ++ ++ if (num_KumeranLockLoss > bd) { ++ int kmrn_lock_loss = KumeranLockLoss[bd]; ++ e1000_validate_option(&kmrn_lock_loss, &opt, adapter); ++ if (hw->mac.type == e1000_ich8lan) ++ e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, ++ kmrn_lock_loss); ++ } else { ++ if (hw->mac.type == e1000_ich8lan) ++ e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, ++ opt.def); ++ } ++ } ++} +diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c +new file mode 100644 +index 0000000..6fd55e7 +--- /dev/null ++++ b/drivers/net/e1000e/phy.c +@@ -0,0 +1,1821 @@ ++/******************************************************************************* ++ ++ Intel PRO/1000 Linux driver ++ Copyright(c) 1999 - 2007 Intel Corporation. ++ ++ This program is free software; you can redistribute it and/or modify it ++ under the terms and conditions of the GNU General Public License, ++ version 2, as published by the Free Software Foundation. ++ ++ This program is distributed in the hope it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ more details. ++ ++ You should have received a copy of the GNU General Public License along with ++ this program; if not, write to the Free Software Foundation, Inc., ++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ ++ The full GNU General Public License is included in this distribution in ++ the file called "COPYING". ++ ++ Contact Information: ++ Linux NICS <linux.nics@intel.com> ++ e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> ++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ++ ++*******************************************************************************/ ++ ++#include "e1000.h" ++ ++static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); ++static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); ++ ++/* Cable length tables */ ++static const u16 e1000_m88_cable_length_table[] = ++ { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; ++ ++static const u16 e1000_igp_2_cable_length_table[] = ++ { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, ++ 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22, ++ 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40, ++ 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61, ++ 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82, ++ 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95, ++ 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121, ++ 124}; ++#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ ++ (sizeof(e1000_igp_2_cable_length_table) / \ ++ sizeof(e1000_igp_2_cable_length_table[0])) ++ ++/** ++ * e1000_check_reset_block_generic - Check if PHY reset is blocked ++ * @hw: pointer to the HW structure ++ * ++ * Read the PHY management control register and check whether a PHY reset ++ * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise ++ * return E1000_BLK_PHY_RESET (12). ++ **/ ++s32 e1000_check_reset_block_generic(struct e1000_hw *hw) ++{ ++ u32 manc; ++ ++ manc = er32(MANC); ++ ++ return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? ++ E1000_BLK_PHY_RESET : E1000_SUCCESS; ++} ++ ++/** ++ * e1000_get_phy_id - Retrieve the PHY ID and revision ++ * @hw: pointer to the HW structure ++ * ++ * Reads the PHY registers and stores the PHY ID and possibly the PHY ++ * revision in the hardware structure. ++ **/ ++s32 e1000_get_phy_id(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val = E1000_SUCCESS; ++ u16 phy_id; ++ ++ ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); ++ if (ret_val) ++ goto out; ++ ++ phy->id = (u32)(phy_id << 16); ++ udelay(20); ++ ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); ++ if (ret_val) ++ goto out; ++ ++ phy->id |= (u32)(phy_id & PHY_REVISION_MASK); ++ phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_reset_dsp - Reset PHY DSP ++ * @hw: pointer to the HW structure ++ * ++ * Reset the digital signal processor. ++ **/ ++s32 e1000_phy_reset_dsp(struct e1000_hw *hw) ++{ ++ s32 ret_val; ++ ++ ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_read_phy_reg_mdic - Read MDI control register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to be read ++ * @data: pointer to the read data ++ * ++ * Reads the MDI control regsiter in the PHY at offset and stores the ++ * information read to data. ++ **/ ++static s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ u32 i, mdic = 0; ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (offset > MAX_PHY_REG_ADDRESS) { ++ hw_dbg(hw, "PHY Address %d is out of range\n", offset); ++ ret_val = -E1000_ERR_PARAM; ++ goto out; ++ } ++ ++ /* Set up Op-code, Phy Address, and register offset in the MDI ++ * Control register. The MAC will take care of interfacing with the ++ * PHY to retrieve the desired data. ++ */ ++ mdic = ((offset << E1000_MDIC_REG_SHIFT) | ++ (phy->addr << E1000_MDIC_PHY_SHIFT) | ++ (E1000_MDIC_OP_READ)); ++ ++ ew32(MDIC, mdic); ++ ++ /* Poll the ready bit to see if the MDI read completed */ ++ for (i = 0; i < 64; i++) { ++ udelay(50); ++ mdic = er32(MDIC); ++ if (mdic & E1000_MDIC_READY) ++ break; ++ } ++ if (!(mdic & E1000_MDIC_READY)) { ++ hw_dbg(hw, "MDI Read did not complete\n"); ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ if (mdic & E1000_MDIC_ERROR) { ++ hw_dbg(hw, "MDI Error\n"); ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ *data = (u16) mdic; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_write_phy_reg_mdic - Write MDI control register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to write to ++ * @data: data to write to register at offset ++ * ++ * Writes data to MDI control register in the PHY at offset. ++ **/ ++static s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ u32 i, mdic = 0; ++ s32 ret_val = E1000_SUCCESS; ++ ++ if (offset > MAX_PHY_REG_ADDRESS) { ++ hw_dbg(hw, "PHY Address %d is out of range\n", offset); ++ ret_val = -E1000_ERR_PARAM; ++ goto out; ++ } ++ ++ /* Set up Op-code, Phy Address, and register offset in the MDI ++ * Control register. The MAC will take care of interfacing with the ++ * PHY to retrieve the desired data. ++ */ ++ mdic = (((u32)data) | ++ (offset << E1000_MDIC_REG_SHIFT) | ++ (phy->addr << E1000_MDIC_PHY_SHIFT) | ++ (E1000_MDIC_OP_WRITE)); ++ ++ ew32(MDIC, mdic); ++ ++ /* Poll the ready bit to see if the MDI read completed */ ++ for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { ++ udelay(5); ++ mdic = er32(MDIC); ++ if (mdic & E1000_MDIC_READY) ++ break; ++ } ++ if (!(mdic & E1000_MDIC_READY)) { ++ hw_dbg(hw, "MDI Write did not complete\n"); ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_read_phy_reg_m88 - Read m88 PHY register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to be read ++ * @data: pointer to the read data ++ * ++ * Acquires semaphore, if necessary, then reads the PHY register at offset ++ * and storing the retrieved information in data. Release any acquired ++ * semaphores before exiting. ++ **/ ++s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) ++{ ++ s32 ret_val; ++ ++ ret_val = hw->phy.ops.acquire_phy(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000_read_phy_reg_mdic(hw, ++ MAX_PHY_REG_ADDRESS & offset, ++ data); ++ ++ hw->phy.ops.release_phy(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_write_phy_reg_m88 - Write m88 PHY register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to write to ++ * @data: data to write at register offset ++ * ++ * Acquires semaphore, if necessary, then writes the data to PHY register ++ * at the offset. Release any acquired semaphores before exiting. ++ **/ ++s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) ++{ ++ s32 ret_val; ++ ++ ret_val = hw->phy.ops.acquire_phy(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1000_write_phy_reg_mdic(hw, ++ MAX_PHY_REG_ADDRESS & offset, ++ data); ++ ++ hw->phy.ops.release_phy(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_read_phy_reg_igp - Read igp PHY register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to be read ++ * @data: pointer to the read data ++ * ++ * Acquires semaphore, if necessary, then reads the PHY register at offset ++ * and storing the retrieved information in data. Release any acquired ++ * semaphores before exiting. ++ **/ ++s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) ++{ ++ s32 ret_val; ++ ++ ret_val = hw->phy.ops.acquire_phy(hw); ++ if (ret_val) ++ goto out; ++ ++ if (offset > MAX_PHY_MULTI_PAGE_REG) { ++ ret_val = e1000_write_phy_reg_mdic(hw, ++ IGP01E1000_PHY_PAGE_SELECT, ++ (u16)offset); ++ if (ret_val) { ++ hw->phy.ops.release_phy(hw); ++ goto out; ++ } ++ } ++ ++ ret_val = e1000_read_phy_reg_mdic(hw, ++ MAX_PHY_REG_ADDRESS & offset, ++ data); ++ ++ hw->phy.ops.release_phy(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_write_phy_reg_igp - Write igp PHY register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to write to ++ * @data: data to write at register offset ++ * ++ * Acquires semaphore, if necessary, then writes the data to PHY register ++ * at the offset. Release any acquired semaphores before exiting. ++ **/ ++s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) ++{ ++ s32 ret_val; ++ ++ ret_val = hw->phy.ops.acquire_phy(hw); ++ if (ret_val) ++ goto out; ++ ++ if (offset > MAX_PHY_MULTI_PAGE_REG) { ++ ret_val = e1000_write_phy_reg_mdic(hw, ++ IGP01E1000_PHY_PAGE_SELECT, ++ (u16)offset); ++ if (ret_val) { ++ hw->phy.ops.release_phy(hw); ++ goto out; ++ } ++ } ++ ++ ret_val = e1000_write_phy_reg_mdic(hw, ++ MAX_PHY_REG_ADDRESS & offset, ++ data); ++ ++ hw->phy.ops.release_phy(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_read_kmrn_reg - Read kumeran register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to be read ++ * @data: pointer to the read data ++ * ++ * Acquires semaphore, if necessary. Then reads the PHY register at offset ++ * using the kumeran interface. The information retrieved is stored in data. ++ * Release any acquired semaphores before exiting. ++ **/ ++s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) ++{ ++ u32 kmrnctrlsta; ++ s32 ret_val; ++ ++ ret_val = hw->phy.ops.acquire_phy(hw); ++ if (ret_val) ++ goto out; ++ ++ kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & ++ E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; ++ ew32(KMRNCTRLSTA, kmrnctrlsta); ++ ++ udelay(2); ++ ++ kmrnctrlsta = er32(KMRNCTRLSTA); ++ *data = (u16)kmrnctrlsta; ++ ++ hw->phy.ops.release_phy(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_write_kmrn_reg - Write kumeran register ++ * @hw: pointer to the HW structure ++ * @offset: register offset to write to ++ * @data: data to write at register offset ++ * ++ * Acquires semaphore, if necessary. Then write the data to PHY register ++ * at the offset using the kumeran interface. Release any acquired semaphores ++ * before exiting. ++ **/ ++s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) ++{ ++ u32 kmrnctrlsta; ++ s32 ret_val; ++ ++ ret_val = hw->phy.ops.acquire_phy(hw); ++ if (ret_val) ++ goto out; ++ ++ kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & ++ E1000_KMRNCTRLSTA_OFFSET) | data; ++ ew32(KMRNCTRLSTA, kmrnctrlsta); ++ ++ udelay(2); ++ hw->phy.ops.release_phy(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link ++ * @hw: pointer to the HW structure ++ * ++ * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock ++ * and downshift values are set also. ++ **/ ++s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_data; ++ ++ /* Enable CRS on TX. This must be set for half-duplex operation. */ ++ ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; ++ ++ /* Options: ++ * MDI/MDI-X = 0 (default) ++ * 0 - Auto for all speeds ++ * 1 - MDI mode ++ * 2 - MDI-X mode ++ * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) ++ */ ++ phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; ++ ++ switch (phy->mdix) { ++ case 1: ++ phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; ++ break; ++ case 2: ++ phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; ++ break; ++ case 3: ++ phy_data |= M88E1000_PSCR_AUTO_X_1000T; ++ break; ++ case 0: ++ default: ++ phy_data |= M88E1000_PSCR_AUTO_X_MODE; ++ break; ++ } ++ ++ /* Options: ++ * disable_polarity_correction = 0 (default) ++ * Automatic Correction for Reversed Cable Polarity ++ * 0 - Disabled ++ * 1 - Enabled ++ */ ++ phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; ++ if (phy->disable_polarity_correction == 1) ++ phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; ++ ++ ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); ++ if (ret_val) ++ goto out; ++ ++ if (phy->revision < 4) { ++ /* Force TX_CLK in the Extended PHY Specific Control Register ++ * to 25MHz clock. ++ */ ++ ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy_data |= M88E1000_EPSCR_TX_CLK_25; ++ ++ if ((phy->revision == 2) && ++ (phy->id == M88E1111_I_PHY_ID)) { ++ /* 82573L PHY - set the downshift counter to 5x. */ ++ phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; ++ phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; ++ } else { ++ /* Configure Master and Slave downshift values */ ++ phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | ++ M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); ++ phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | ++ M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); ++ } ++ ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); ++ if (ret_val) ++ goto out; ++ } ++ ++ /* Commit the changes. */ ++ ret_val = e1000_commit_phy(hw); ++ if (ret_val) { ++ hw_dbg(hw, "Error committing the PHY changes\n"); ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_copper_link_setup_igp - Setup igp PHY's for copper link ++ * @hw: pointer to the HW structure ++ * ++ * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for ++ * igp PHY's. ++ **/ ++s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 data; ++ ++ ret_val = e1000_phy_hw_reset(hw); ++ if (ret_val) { ++ hw_dbg(hw, "Error resetting the PHY.\n"); ++ goto out; ++ } ++ ++ /* Wait 15ms for MAC to configure PHY from NVM settings. */ ++ msleep(15); ++ ++ /* disable lplu d0 during driver init */ ++ ret_val = e1000_set_d0_lplu_state(hw, 0); ++ if (ret_val) { ++ hw_dbg(hw, "Error Disabling LPLU D0\n"); ++ goto out; ++ } ++ /* Configure mdi-mdix settings */ ++ ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~IGP01E1000_PSCR_AUTO_MDIX; ++ ++ switch (phy->mdix) { ++ case 1: ++ data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; ++ break; ++ case 2: ++ data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; ++ break; ++ case 0: ++ default: ++ data |= IGP01E1000_PSCR_AUTO_MDIX; ++ break; ++ } ++ ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data); ++ if (ret_val) ++ goto out; ++ ++ /* set auto-master slave resolution settings */ ++ if (hw->mac.autoneg) { ++ /* when autonegotiation advertisement is only 1000Mbps then we ++ * should disable SmartSpeed and enable Auto MasterSlave ++ * resolution as hardware default. */ ++ if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { ++ /* Disable SmartSpeed */ ++ ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ if (ret_val) ++ goto out; ++ ++ /* Set auto Master/Slave resolution process */ ++ ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~CR_1000T_MS_ENABLE; ++ ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data); ++ if (ret_val) ++ goto out; ++ } ++ ++ ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data); ++ if (ret_val) ++ goto out; ++ ++ /* load defaults for future use */ ++ phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? ++ ((data & CR_1000T_MS_VALUE) ? ++ e1000_ms_force_master : ++ e1000_ms_force_slave) : ++ e1000_ms_auto; ++ ++ switch (phy->ms_type) { ++ case e1000_ms_force_master: ++ data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); ++ break; ++ case e1000_ms_force_slave: ++ data |= CR_1000T_MS_ENABLE; ++ data &= ~(CR_1000T_MS_VALUE); ++ break; ++ case e1000_ms_auto: ++ data &= ~CR_1000T_MS_ENABLE; ++ default: ++ break; ++ } ++ ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data); ++ if (ret_val) ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation ++ * @hw: pointer to the HW structure ++ * ++ * Reads the MII auto-neg advertisement register and/or the 1000T control ++ * register and if the PHY is already setup for auto-negotiation, then ++ * return successful. Otherwise, setup advertisement and flow control to ++ * the appropriate values for the wanted auto-negotiation. ++ **/ ++static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 mii_autoneg_adv_reg; ++ u16 mii_1000t_ctrl_reg = 0; ++ ++ phy->autoneg_advertised &= phy->autoneg_mask; ++ ++ /* Read the MII Auto-Neg Advertisement Register (Address 4). */ ++ ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); ++ if (ret_val) ++ goto out; ++ ++ if (phy->autoneg_mask & ADVERTISE_1000_FULL) { ++ /* Read the MII 1000Base-T Control Register (Address 9). */ ++ ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); ++ if (ret_val) ++ goto out; ++ } ++ ++ /* Need to parse both autoneg_advertised and fc and set up ++ * the appropriate PHY registers. First we will parse for ++ * autoneg_advertised software override. Since we can advertise ++ * a plethora of combinations, we need to check each bit ++ * individually. ++ */ ++ ++ /* First we clear all the 10/100 mb speed bits in the Auto-Neg ++ * Advertisement Register (Address 4) and the 1000 mb speed bits in ++ * the 1000Base-T Control Register (Address 9). ++ */ ++ mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | ++ NWAY_AR_100TX_HD_CAPS | ++ NWAY_AR_10T_FD_CAPS | ++ NWAY_AR_10T_HD_CAPS); ++ mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); ++ ++ hw_dbg(hw, "autoneg_advertised %x\n", phy->autoneg_advertised); ++ ++ /* Do we want to advertise 10 Mb Half Duplex? */ ++ if (phy->autoneg_advertised & ADVERTISE_10_HALF) { ++ hw_dbg(hw, "Advertise 10mb Half duplex\n"); ++ mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; ++ } ++ ++ /* Do we want to advertise 10 Mb Full Duplex? */ ++ if (phy->autoneg_advertised & ADVERTISE_10_FULL) { ++ hw_dbg(hw, "Advertise 10mb Full duplex\n"); ++ mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; ++ } ++ ++ /* Do we want to advertise 100 Mb Half Duplex? */ ++ if (phy->autoneg_advertised & ADVERTISE_100_HALF) { ++ hw_dbg(hw, "Advertise 100mb Half duplex\n"); ++ mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; ++ } ++ ++ /* Do we want to advertise 100 Mb Full Duplex? */ ++ if (phy->autoneg_advertised & ADVERTISE_100_FULL) { ++ hw_dbg(hw, "Advertise 100mb Full duplex\n"); ++ mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; ++ } ++ ++ /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ ++ if (phy->autoneg_advertised & ADVERTISE_1000_HALF) ++ hw_dbg(hw, "Advertise 1000mb Half duplex request denied!\n"); ++ ++ /* Do we want to advertise 1000 Mb Full Duplex? */ ++ if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { ++ hw_dbg(hw, "Advertise 1000mb Full duplex\n"); ++ mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; ++ } ++ ++ /* Check for a software override of the flow control settings, and ++ * setup the PHY advertisement registers accordingly. If ++ * auto-negotiation is enabled, then software will have to set the ++ * "PAUSE" bits to the correct value in the Auto-Negotiation ++ * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- ++ * negotiation. ++ * ++ * The possible values of the "fc" parameter are: ++ * 0: Flow control is completely disabled ++ * 1: Rx flow control is enabled (we can receive pause frames ++ * but not send pause frames). ++ * 2: Tx flow control is enabled (we can send pause frames ++ * but we do not support receiving pause frames). ++ * 3: Both Rx and TX flow control (symmetric) are enabled. ++ * other: No software override. The flow control configuration ++ * in the EEPROM is used. ++ */ ++ switch (hw->mac.fc) { ++ case e1000_fc_none: ++ /* Flow control (RX & TX) is completely disabled by a ++ * software over-ride. ++ */ ++ mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); ++ break; ++ case e1000_fc_rx_pause: ++ /* RX Flow control is enabled, and TX Flow control is ++ * disabled, by a software over-ride. ++ */ ++ /* Since there really isn't a way to advertise that we are ++ * capable of RX Pause ONLY, we will advertise that we ++ * support both symmetric and asymmetric RX PAUSE. Later ++ * (in e1000_config_fc_after_link_up) we will disable the ++ * hw's ability to send PAUSE frames. ++ */ ++ mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); ++ break; ++ case e1000_fc_tx_pause: ++ /* TX Flow control is enabled, and RX Flow control is ++ * disabled, by a software over-ride. ++ */ ++ mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; ++ mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; ++ break; ++ case e1000_fc_full: ++ /* Flow control (both RX and TX) is enabled by a software ++ * over-ride. ++ */ ++ mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); ++ break; ++ default: ++ hw_dbg(hw, "Flow control param set incorrectly\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); ++ if (ret_val) ++ goto out; ++ ++ hw_dbg(hw, "Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); ++ ++ if (phy->autoneg_mask & ADVERTISE_1000_FULL) { ++ ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); ++ if (ret_val) ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link ++ * @hw: pointer to the HW structure ++ * ++ * Performs initial bounds checking on autoneg advertisement parameter, then ++ * configure to advertise the full capability. Setup the PHY to autoneg ++ * and restart the negotiation process between the link partner. If ++ * wait_for_link, then wait for autoneg to complete before exiting. ++ **/ ++static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_ctrl; ++ ++ /* Perform some bounds checking on the autoneg advertisement ++ * parameter. ++ */ ++ phy->autoneg_advertised &= phy->autoneg_mask; ++ ++ /* If autoneg_advertised is zero, we assume it was not defaulted ++ * by the calling code so we set to advertise full capability. ++ */ ++ if (phy->autoneg_advertised == 0) ++ phy->autoneg_advertised = phy->autoneg_mask; ++ ++ hw_dbg(hw, "Reconfiguring auto-neg advertisement params\n"); ++ ret_val = e1000_phy_setup_autoneg(hw); ++ if (ret_val) { ++ hw_dbg(hw, "Error Setting up Auto-Negotiation\n"); ++ goto out; ++ } ++ hw_dbg(hw, "Restarting Auto-Neg\n"); ++ ++ /* Restart auto-negotiation by setting the Auto Neg Enable bit and ++ * the Auto Neg Restart bit in the PHY control register. ++ */ ++ ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl); ++ if (ret_val) ++ goto out; ++ ++ phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); ++ ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl); ++ if (ret_val) ++ goto out; ++ ++ /* Does the user want to wait for Auto-Neg to complete here, or ++ * check at a later time (for example, callback routine). ++ */ ++ if (phy->wait_for_link) { ++ ret_val = e1000_wait_autoneg(hw); ++ if (ret_val) { ++ hw_dbg(hw, "Error while waiting for " ++ "autoneg to complete\n"); ++ goto out; ++ } ++ } ++ ++ hw->mac.get_link_status = 1; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_setup_copper_link - Configure copper link settings ++ * @hw: pointer to the HW structure ++ * ++ * Calls the appropriate function to configure the link for auto-neg or forced ++ * speed and duplex. Then we check for link, once link is established calls ++ * to configure collision distance and flow control are called. If link is ++ * not established, we return -E1000_ERR_PHY (-2). ++ **/ ++s32 e1000_setup_copper_link(struct e1000_hw *hw) ++{ ++ s32 ret_val; ++ bool link; ++ ++ if (hw->mac.autoneg) { ++ /* Setup autoneg and flow control advertisement and perform ++ * autonegotiation. */ ++ ret_val = e1000_copper_link_autoneg(hw); ++ if (ret_val) ++ goto out; ++ } else { ++ /* PHY will be set to 10H, 10F, 100H or 100F ++ * depending on user settings. */ ++ hw_dbg(hw, "Forcing Speed and Duplex\n"); ++ ret_val = e1000_phy_force_speed_duplex(hw); ++ if (ret_val) { ++ hw_dbg(hw, "Error Forcing Speed and Duplex\n"); ++ goto out; ++ } ++ } ++ ++ /* Check link status. Wait up to 100 microseconds for link to become ++ * valid. ++ */ ++ ret_val = e1000_phy_has_link_generic(hw, ++ COPPER_LINK_UP_LIMIT, ++ 10, ++ &link); ++ if (ret_val) ++ goto out; ++ ++ if (link) { ++ hw_dbg(hw, "Valid link established!!!\n"); ++ e1000_config_collision_dist(hw); ++ ret_val = e1000_config_fc_after_link_up(hw); ++ } else { ++ hw_dbg(hw, "Unable to establish link!!!\n"); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY ++ * @hw: pointer to the HW structure ++ * ++ * Calls the PHY setup function to force speed and duplex. Clears the ++ * auto-crossover to force MDI manually. Waits for link and returns ++ * successful if link up is successful, else -E1000_ERR_PHY (-2). ++ **/ ++s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_data; ++ bool link; ++ ++ ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ e1000_phy_force_speed_duplex_setup(hw, &phy_data); ++ ++ ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); ++ if (ret_val) ++ goto out; ++ ++ /* Clear Auto-Crossover to force MDI manually. IGP requires MDI ++ * forced whenever speed and duplex are forced. ++ */ ++ ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; ++ phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; ++ ++ ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); ++ if (ret_val) ++ goto out; ++ ++ hw_dbg(hw, "IGP PSCR: %X\n", phy_data); ++ ++ udelay(1); ++ ++ if (phy->wait_for_link) { ++ hw_dbg(hw, "Waiting for forced speed/duplex link on IGP phy.\n"); ++ ++ ret_val = e1000_phy_has_link_generic(hw, ++ PHY_FORCE_LIMIT, ++ 100000, ++ &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) ++ hw_dbg(hw, "Link taking longer than expected.\n"); ++ ++ /* Try once more */ ++ ret_val = e1000_phy_has_link_generic(hw, ++ PHY_FORCE_LIMIT, ++ 100000, ++ &link); ++ if (ret_val) ++ goto out; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY ++ * @hw: pointer to the HW structure ++ * ++ * Calls the PHY setup function to force speed and duplex. Clears the ++ * auto-crossover to force MDI manually. Resets the PHY to commit the ++ * changes. If time expires while waiting for link up, we reset the DSP. ++ * After reset, TX_CLK and CRS on TX must be set. Return successful upon ++ * successful completion, else return corresponding error code. ++ **/ ++s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_data; ++ bool link; ++ ++ /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI ++ * forced whenever speed and duplex are forced. ++ */ ++ ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; ++ ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); ++ if (ret_val) ++ goto out; ++ ++ hw_dbg(hw, "M88E1000 PSCR: %X\n", phy_data); ++ ++ ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ e1000_phy_force_speed_duplex_setup(hw, &phy_data); ++ ++ /* Reset the phy to commit changes. */ ++ phy_data |= MII_CR_RESET; ++ ++ ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); ++ if (ret_val) ++ goto out; ++ ++ udelay(1); ++ ++ if (phy->wait_for_link) { ++ hw_dbg(hw, "Waiting for forced speed/duplex link on M88 phy.\n"); ++ ++ ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, ++ 100000, &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) { ++ /* We didn't get link. ++ * Reset the DSP and cross our fingers. ++ */ ++ ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT, 0x001d); ++ if (ret_val) ++ goto out; ++ ret_val = e1000_phy_reset_dsp(hw); ++ if (ret_val) ++ goto out; ++ } ++ ++ /* Try once more */ ++ ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, ++ 100000, &link); ++ if (ret_val) ++ goto out; ++ } ++ ++ ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ /* Resetting the phy means we need to re-force TX_CLK in the ++ * Extended PHY Specific Control Register to 25MHz clock from ++ * the reset value of 2.5MHz. ++ */ ++ phy_data |= M88E1000_EPSCR_TX_CLK_25; ++ ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); ++ if (ret_val) ++ goto out; ++ ++ /* In addition, we must re-enable CRS on Tx for both half and full ++ * duplex. ++ */ ++ ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; ++ ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex ++ * @hw: pointer to the HW structure ++ * @phy_ctrl: pointer to current value of PHY_CONTROL ++ * ++ * Forces speed and duplex on the PHY by doing the following: disable flow ++ * control, force speed/duplex on the MAC, disable auto speed detection, ++ * disable auto-negotiation, configure duplex, configure speed, configure ++ * the collision distance, write configuration to CTRL register. The ++ * caller must write to the PHY_CONTROL register for these settings to ++ * take affect. ++ **/ ++void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) ++{ ++ struct e1000_mac_info *mac = &hw->mac; ++ u32 ctrl; ++ ++ /* Turn off flow control when forcing speed/duplex */ ++ mac->fc = e1000_fc_none; ++ ++ /* Force speed/duplex on the mac */ ++ ctrl = er32(CTRL); ++ ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); ++ ctrl &= ~E1000_CTRL_SPD_SEL; ++ ++ /* Disable Auto Speed Detection */ ++ ctrl &= ~E1000_CTRL_ASDE; ++ ++ /* Disable autoneg on the phy */ ++ *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; ++ ++ /* Forcing Full or Half Duplex? */ ++ if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { ++ ctrl &= ~E1000_CTRL_FD; ++ *phy_ctrl &= ~MII_CR_FULL_DUPLEX; ++ hw_dbg(hw, "Half Duplex\n"); ++ } else { ++ ctrl |= E1000_CTRL_FD; ++ *phy_ctrl |= MII_CR_FULL_DUPLEX; ++ hw_dbg(hw, "Full Duplex\n"); ++ } ++ ++ /* Forcing 10mb or 100mb? */ ++ if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { ++ ctrl |= E1000_CTRL_SPD_100; ++ *phy_ctrl |= MII_CR_SPEED_100; ++ *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); ++ hw_dbg(hw, "Forcing 100mb\n"); ++ } else { ++ ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); ++ *phy_ctrl |= MII_CR_SPEED_10; ++ *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); ++ hw_dbg(hw, "Forcing 10mb\n"); ++ } ++ ++ e1000_config_collision_dist(hw); ++ ++ ew32(CTRL, ctrl); ++} ++ ++/** ++ * e1000_set_d3_lplu_state - Sets low power link up state for D3 ++ * @hw: pointer to the HW structure ++ * @active: boolean used to enable/disable lplu ++ * ++ * Success returns 0, Failure returns 1 ++ * ++ * The low power link up (lplu) state is set to the power management level D3 ++ * and SmartSpeed is disabled when active is true, else clear lplu for D3 ++ * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU ++ * is used during Dx states where the power conservation is most important. ++ * During driver activity, SmartSpeed should be enabled so performance is ++ * maintained. ++ **/ ++s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 data; ++ ++ ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); ++ if (ret_val) ++ goto out; ++ ++ if (!active) { ++ data &= ~IGP02E1000_PM_D3_LPLU; ++ ret_val = e1e_wphy(hw, ++ IGP02E1000_PHY_POWER_MGMT, ++ data); ++ if (ret_val) ++ goto out; ++ /* LPLU and SmartSpeed are mutually exclusive. LPLU is used ++ * during Dx states where the power conservation is most ++ * important. During driver activity we should enable ++ * SmartSpeed, so performance is maintained. */ ++ if (phy->smart_speed == e1000_smart_speed_on) { ++ ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data |= IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ if (ret_val) ++ goto out; ++ } else if (phy->smart_speed == e1000_smart_speed_off) { ++ ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, ++ &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, ++ data); ++ if (ret_val) ++ goto out; ++ } ++ } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || ++ (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || ++ (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { ++ data |= IGP02E1000_PM_D3_LPLU; ++ ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); ++ if (ret_val) ++ goto out; ++ ++ /* When LPLU is enabled, we should disable SmartSpeed */ ++ ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); ++ if (ret_val) ++ goto out; ++ ++ data &= ~IGP01E1000_PSCFR_SMART_SPEED; ++ ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_check_downshift - Checks whether a downshift in speed occured ++ * @hw: pointer to the HW structure ++ * ++ * Success returns 0, Failure returns 1 ++ * ++ * A downshift is detected by querying the PHY link health. ++ **/ ++s32 e1000_check_downshift(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_data, offset, mask; ++ ++ switch (phy->type) { ++ case e1000_phy_m88: ++ case e1000_phy_gg82563: ++ offset = M88E1000_PHY_SPEC_STATUS; ++ mask = M88E1000_PSSR_DOWNSHIFT; ++ break; ++ case e1000_phy_igp_2: ++ case e1000_phy_igp_3: ++ offset = IGP01E1000_PHY_LINK_HEALTH; ++ mask = IGP01E1000_PLHR_SS_DOWNGRADE; ++ break; ++ default: ++ /* speed downshift not supported */ ++ phy->speed_downgraded = 0; ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ ++ ret_val = e1e_rphy(hw, offset, &phy_data); ++ ++ if (!ret_val) ++ phy->speed_downgraded = (phy_data & mask); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_check_polarity_m88 - Checks the polarity. ++ * @hw: pointer to the HW structure ++ * ++ * Success returns 0, Failure returns -E1000_ERR_PHY (-2) ++ * ++ * Polarity is determined based on the PHY specific status register. ++ **/ ++static s32 e1000_check_polarity_m88(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 data; ++ ++ ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data); ++ ++ if (!ret_val) ++ phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) ++ ? e1000_rev_polarity_reversed ++ : e1000_rev_polarity_normal; ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_check_polarity_igp - Checks the polarity. ++ * @hw: pointer to the HW structure ++ * ++ * Success returns 0, Failure returns -E1000_ERR_PHY (-2) ++ * ++ * Polarity is determined based on the PHY port status register, and the ++ * current speed (since there is no polarity at 100Mbps). ++ **/ ++static s32 e1000_check_polarity_igp(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 data, offset, mask; ++ ++ /* Polarity is determined based on the speed of ++ * our connection. */ ++ ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); ++ if (ret_val) ++ goto out; ++ ++ if ((data & IGP01E1000_PSSR_SPEED_MASK) == ++ IGP01E1000_PSSR_SPEED_1000MBPS) { ++ offset = IGP01E1000_PHY_PCS_INIT_REG; ++ mask = IGP01E1000_PHY_POLARITY_MASK; ++ } else { ++ /* This really only applies to 10Mbps since ++ * there is no polarity for 100Mbps (always 0). ++ */ ++ offset = IGP01E1000_PHY_PORT_STATUS; ++ mask = IGP01E1000_PSSR_POLARITY_REVERSED; ++ } ++ ++ ret_val = e1e_rphy(hw, offset, &data); ++ ++ if (!ret_val) ++ phy->cable_polarity = (data & mask) ++ ? e1000_rev_polarity_reversed ++ : e1000_rev_polarity_normal; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_wait_autoneg - Wait for auto-neg compeletion ++ * @hw: pointer to the HW structure ++ * ++ * Waits for auto-negotiation to complete or for the auto-negotiation time ++ * limit to expire, which ever happens first. ++ **/ ++s32 e1000_wait_autoneg(struct e1000_hw *hw) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 i, phy_status; ++ ++ /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ ++ for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { ++ ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); ++ if (ret_val) ++ break; ++ ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); ++ if (ret_val) ++ break; ++ if (phy_status & MII_SR_AUTONEG_COMPLETE) ++ break; ++ msleep(100); ++ } ++ ++ /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation ++ * has completed. ++ */ ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_has_link_generic - Polls PHY for link ++ * @hw: pointer to the HW structure ++ * @iterations: number of times to poll for link ++ * @usec_interval: delay between polling attempts ++ * @success: pointer to whether polling was successful or not ++ * ++ * Polls the PHY status register for link, 'iterations' number of times. ++ **/ ++s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, ++ u32 usec_interval, bool *success) ++{ ++ s32 ret_val = E1000_SUCCESS; ++ u16 i, phy_status; ++ ++ for (i = 0; i < iterations; i++) { ++ /* Some PHYs require the PHY_STATUS register to be read ++ * twice due to the link bit being sticky. No harm doing ++ * it across the board. ++ */ ++ ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); ++ if (ret_val) ++ break; ++ ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); ++ if (ret_val) ++ break; ++ if (phy_status & MII_SR_LINK_STATUS) ++ break; ++ if (usec_interval >= 1000) ++ mdelay(usec_interval/1000); ++ else ++ udelay(usec_interval); ++ } ++ ++ *success = (i < iterations); ++ ++ return ret_val; ++} ++ ++/** ++ * e1000_get_cable_length_m88 - Determine cable length for m88 PHY ++ * @hw: pointer to the HW structure ++ * ++ * Reads the PHY specific status register to retrieve the cable length ++ * information. The cable length is determined by averaging the minimum and ++ * maximum values to get the "average" cable length. The m88 PHY has four ++ * possible cable length values, which are: ++ * Register Value Cable Length ++ * 0 < 50 meters ++ * 1 50 - 80 meters ++ * 2 80 - 110 meters ++ * 3 110 - 140 meters ++ * 4 > 140 meters ++ **/ ++s32 e1000_get_cable_length_m88(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_data, index; ++ ++ ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> ++ M88E1000_PSSR_CABLE_LENGTH_SHIFT; ++ phy->min_cable_length = e1000_m88_cable_length_table[index]; ++ phy->max_cable_length = e1000_m88_cable_length_table[index+1]; ++ ++ phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY ++ * @hw: pointer to the HW structure ++ * ++ * The automatic gain control (agc) normalizes the amplitude of the ++ * received signal, adjusting for the attenuation produced by the ++ * cable. By reading the AGC registers, which reperesent the ++ * cobination of course and fine gain value, the value can be put ++ * into a lookup table to obtain the approximate cable length ++ * for each channel. ++ **/ ++s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_data, i, agc_value = 0; ++ u16 cur_agc_index, max_agc_index = 0; ++ u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; ++ u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = ++ {IGP02E1000_PHY_AGC_A, ++ IGP02E1000_PHY_AGC_B, ++ IGP02E1000_PHY_AGC_C, ++ IGP02E1000_PHY_AGC_D}; ++ ++ /* Read the AGC registers for all channels */ ++ for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { ++ ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data); ++ if (ret_val) ++ goto out; ++ ++ /* Getting bits 15:9, which represent the combination of ++ * course and fine gain values. The result is a number ++ * that can be put into the lookup table to obtain the ++ * approximate cable length. */ ++ cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & ++ IGP02E1000_AGC_LENGTH_MASK; ++ ++ /* Array index bound check. */ ++ if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || ++ (cur_agc_index == 0)) { ++ ret_val = -E1000_ERR_PHY; ++ goto out; ++ } ++ ++ /* Remove min & max AGC values from calculation. */ ++ if (e1000_igp_2_cable_length_table[min_agc_index] > ++ e1000_igp_2_cable_length_table[cur_agc_index]) ++ min_agc_index = cur_agc_index; ++ if (e1000_igp_2_cable_length_table[max_agc_index] < ++ e1000_igp_2_cable_length_table[cur_agc_index]) ++ max_agc_index = cur_agc_index; ++ ++ agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; ++ } ++ ++ agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + ++ e1000_igp_2_cable_length_table[max_agc_index]); ++ agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); ++ ++ /* Calculate cable length with the error range of +/- 10 meters. */ ++ phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? ++ (agc_value - IGP02E1000_AGC_RANGE) : 0; ++ phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; ++ ++ phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_phy_info_m88 - Retrieve PHY information ++ * @hw: pointer to the HW structure ++ * ++ * Valid for only copper links. Read the PHY status register (sticky read) ++ * to verify that link is up. Read the PHY special control register to ++ * determine the polarity and 10base-T extended distance. Read the PHY ++ * special status register to determine MDI/MDIx and current speed. If ++ * speed is 1000, then determine cable length, local and remote receiver. ++ **/ ++s32 e1000_get_phy_info_m88(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 phy_data; ++ bool link; ++ ++ if (hw->media_type != e1000_media_type_copper) { ++ hw_dbg(hw, "Phy info is only valid for copper media\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) { ++ hw_dbg(hw, "Phy info is only valid if link is up\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy->polarity_correction = (phy_data & ++ M88E1000_PSCR_POLARITY_REVERSAL); ++ ++ ret_val = e1000_check_polarity_m88(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX); ++ ++ if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { ++ ret_val = e1000_get_cable_length(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data); ++ if (ret_val) ++ goto out; ++ ++ phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) ++ ? e1000_1000t_rx_status_ok ++ : e1000_1000t_rx_status_not_ok; ++ ++ phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) ++ ? e1000_1000t_rx_status_ok ++ : e1000_1000t_rx_status_not_ok; ++ } else { ++ /* Set values to "undefined" */ ++ phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; ++ phy->local_rx = e1000_1000t_rx_status_undefined; ++ phy->remote_rx = e1000_1000t_rx_status_undefined; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_phy_info_igp - Retrieve igp PHY information ++ * @hw: pointer to the HW structure ++ * ++ * Read PHY status to determine if link is up. If link is up, then ++ * set/determine 10base-T extended distance and polarity correction. Read ++ * PHY port status to determine MDI/MDIx and speed. Based on the speed, ++ * determine on the cable length, local and remote receiver. ++ **/ ++s32 e1000_get_phy_info_igp(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u16 data; ++ bool link; ++ ++ ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); ++ if (ret_val) ++ goto out; ++ ++ if (!link) { ++ hw_dbg(hw, "Phy info is only valid if link is up\n"); ++ ret_val = -E1000_ERR_CONFIG; ++ goto out; ++ } ++ ++ phy->polarity_correction = 1; ++ ++ ret_val = e1000_check_polarity_igp(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); ++ if (ret_val) ++ goto out; ++ ++ phy->is_mdix = (data & IGP01E1000_PSSR_MDIX); ++ ++ if ((data & IGP01E1000_PSSR_SPEED_MASK) == ++ IGP01E1000_PSSR_SPEED_1000MBPS) { ++ ret_val = e1000_get_cable_length(hw); ++ if (ret_val) ++ goto out; ++ ++ ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data); ++ if (ret_val) ++ goto out; ++ ++ phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) ++ ? e1000_1000t_rx_status_ok ++ : e1000_1000t_rx_status_not_ok; ++ ++ phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) ++ ? e1000_1000t_rx_status_ok ++ : e1000_1000t_rx_status_not_ok; ++ } else { ++ phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; ++ phy->local_rx = e1000_1000t_rx_status_undefined; ++ phy->remote_rx = e1000_1000t_rx_status_undefined; ++ } ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_sw_reset - PHY software reset ++ * @hw: pointer to the HW structure ++ * ++ * Does a software reset of the PHY by reading the PHY control register and ++ * setting/write the control register reset bit to the PHY. ++ **/ ++s32 e1000_phy_sw_reset(struct e1000_hw *hw) ++{ ++ s32 ret_val; ++ u16 phy_ctrl; ++ ++ ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl); ++ if (ret_val) ++ goto out; ++ ++ phy_ctrl |= MII_CR_RESET; ++ ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl); ++ if (ret_val) ++ goto out; ++ ++ udelay(1); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_phy_hw_reset_generic - PHY hardware reset ++ * @hw: pointer to the HW structure ++ * ++ * Verify the reset block is not blocking us from resetting. Acquire ++ * semaphore (if necessary) and read/set/write the device control reset ++ * bit in the PHY. Wait the appropriate delay time for the device to ++ * reset and relase the semaphore (if necessary). ++ **/ ++s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw) ++{ ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; ++ u32 ctrl; ++ ++ ret_val = e1000_check_reset_block(hw); ++ if (ret_val) { ++ ret_val = E1000_SUCCESS; ++ goto out; ++ } ++ ++ ret_val = phy->ops.acquire_phy(hw); ++ if (ret_val) ++ goto out; ++ ++ ctrl = er32(CTRL); ++ ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); ++ e1e_flush(); ++ ++ udelay(phy->reset_delay_us); ++ ++ ew32(CTRL, ctrl); ++ e1e_flush(); ++ ++ udelay(150); ++ ++ phy->ops.release_phy(hw); ++ ++ ret_val = e1000_get_phy_cfg_done(hw); ++ ++out: ++ return ret_val; ++} ++ ++/** ++ * e1000_get_cfg_done - Generic configuration done ++ * @hw: pointer to the HW structure ++ * ++ * Generic function to wait 10 milli-seconds for configuration to complete ++ * and return success. ++ **/ ++s32 e1000_get_cfg_done(struct e1000_hw *hw) ++{ ++ mdelay(10); ++ ++ return E1000_SUCCESS; ++} ++ ++/* Internal function pointers */ ++ ++/** ++ * e1000_get_phy_cfg_done - Generic PHY configuration done ++ * @hw: pointer to the HW structure ++ * ++ * Return success if silicon family did not implement a family specific ++ * get_cfg_done function. ++ **/ ++static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) ++{ ++ if (hw->phy.ops.get_cfg_done) ++ return hw->phy.ops.get_cfg_done(hw); ++ else ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex ++ * @hw: pointer to the HW structure ++ * ++ * When the silicon family has not implemented a forced speed/duplex ++ * function for the PHY, simply return E1000_SUCCESS. ++ **/ ++static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) ++{ ++ if (hw->phy.ops.force_speed_duplex) ++ return hw->phy.ops.force_speed_duplex(hw); ++ else ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_get_phy_type_from_id - Get PHY type from id ++ * @phy_id: phy_id read from the phy ++ * ++ * Returns the phy type from the id. ++ **/ ++enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id) ++{ ++ enum e1000_phy_type phy_type = e1000_phy_unknown; ++ ++ switch (phy_id) { ++ case M88E1000_I_PHY_ID: ++ case M88E1000_E_PHY_ID: ++ case M88E1111_I_PHY_ID: ++ case M88E1011_I_PHY_ID: ++ phy_type = e1000_phy_m88; ++ break; ++ case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ ++ phy_type = e1000_phy_igp_2; ++ break; ++ case GG82563_E_PHY_ID: ++ phy_type = e1000_phy_gg82563; ++ break; ++ case IGP03E1000_E_PHY_ID: ++ phy_type = e1000_phy_igp_3; ++ break; ++ case IFE_E_PHY_ID: ++ case IFE_PLUS_E_PHY_ID: ++ case IFE_C_E_PHY_ID: ++ phy_type = e1000_phy_ife; ++ break; ++ default: ++ phy_type = e1000_phy_unknown; ++ break; ++ } ++ return phy_type; ++} ++ ++/** ++ * e1000_commit_phy - Soft PHY reset ++ * @hw: pointer to the HW structure ++ * ++ * Performs a soft PHY reset on those that apply. This is a function pointer ++ * entry point called by drivers. ++ **/ ++s32 e1000_commit_phy(struct e1000_hw *hw) ++{ ++ if (hw->phy.ops.commit_phy) ++ return hw->phy.ops.commit_phy(hw); ++ else ++ return E1000_SUCCESS; ++} ++ ++/** ++ * e1000_set_d0_lplu_state - Sets low power link up state for D0 ++ * @hw: pointer to the HW structure ++ * @active: boolean used to enable/disable lplu ++ * ++ * Success returns 0, Failure returns 1 ++ * ++ * The low power link up (lplu) state is set to the power management level D0 ++ * and SmartSpeed is disabled when active is true, else clear lplu for D0 ++ * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU ++ * is used during Dx states where the power conservation is most important. ++ * During driver activity, SmartSpeed should be enabled so performance is ++ * maintained. This is a function pointer entry point called by drivers. ++ **/ ++s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) ++{ ++ if (hw->phy.ops.set_d0_lplu_state) ++ return hw->phy.ops.set_d0_lplu_state(hw, active); ++ else ++ return E1000_SUCCESS; ++} diff --git a/trunk/2.6.21/21351_linux-2.6-netdev-e1000e-02.patch b/trunk/2.6.21/21351_linux-2.6-netdev-e1000e-02.patch new file mode 100644 index 0000000..6ec22f6 --- /dev/null +++ b/trunk/2.6.21/21351_linux-2.6-netdev-e1000e-02.patch @@ -0,0 +1,4358 @@ +From: Auke Kok <auke-jan.h.kok@intel.com> +Date: Wed, 8 Aug 2007 17:21:52 +0000 (-0700) +Subject: e1000e: Remove unused or empty labels +X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fjgarzik%2Fnetdev-2.6.git;a=commitdiff_plain;h=3ee7c3bfcc0cc2048cc5d53dd792375e52fe930c + +e1000e: Remove unused or empty labels + +Remove labels with only return, remove E1000_SUCCESS code and +replace with 0. Remove most goto's. + +Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> +Signed-off-by: Jeff Garzik <jeff@garzik.org> +--- + +diff --git a/drivers/net/e1000e/82571.c b/drivers/net/e1000e/82571.c +index a1b9d16..ddf2303 100644 +--- a/drivers/net/e1000e/82571.c ++++ b/drivers/net/e1000e/82571.c +@@ -67,11 +67,11 @@ static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); + static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val; + + if (hw->media_type != e1000_media_type_copper) { + phy->type = e1000_phy_none; +- goto out; ++ return 0; + } + + phy->addr = 1; +@@ -87,8 +87,7 @@ static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) + phy->type = e1000_phy_m88; + break; + default: +- ret_val = -E1000_ERR_PHY; +- goto out; ++ return -E1000_ERR_PHY; + break; + } + +@@ -99,25 +98,19 @@ static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) + switch (hw->mac.type) { + case e1000_82571: + case e1000_82572: +- if (phy->id != IGP01E1000_I_PHY_ID) { +- ret_val = -E1000_ERR_PHY; +- goto out; +- } ++ if (phy->id != IGP01E1000_I_PHY_ID) ++ return -E1000_ERR_PHY; + break; + case e1000_82573: +- if (phy->id != M88E1111_I_PHY_ID) { +- ret_val = -E1000_ERR_PHY; +- goto out; +- } ++ if (phy->id != M88E1111_I_PHY_ID) ++ return -E1000_ERR_PHY; + break; + default: +- ret_val = -E1000_ERR_PHY; +- goto out; ++ return -E1000_ERR_PHY; + break; + } + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -174,7 +167,7 @@ static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) + break; + } + +- return E1000_SUCCESS; ++ return 0; + } + + /** +@@ -188,7 +181,6 @@ static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter) + struct e1000_hw *hw = &adapter->hw; + struct e1000_mac_info *mac = &hw->mac; + struct e1000_mac_operations *func = &mac->ops; +- s32 ret_val = E1000_SUCCESS; + + /* Set media type */ + switch (adapter->pdev->device) { +@@ -232,13 +224,11 @@ static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter) + func->get_link_up_info = e1000_get_speed_and_duplex_fiber_serdes; + break; + default: +- ret_val = -E1000_ERR_CONFIG; +- goto out; ++ return -E1000_ERR_CONFIG; + break; + } + +-out: +- return ret_val; ++ return 0; + } + + static s32 e1000_get_invariants_82571(struct e1000_adapter *adapter) +@@ -306,7 +296,7 @@ static s32 e1000_get_invariants_82571(struct e1000_adapter *adapter) + break; + } + +- return E1000_SUCCESS; ++ return 0; + } + + /** +@@ -319,7 +309,6 @@ static s32 e1000_get_invariants_82571(struct e1000_adapter *adapter) + static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; +- s32 ret_val = E1000_SUCCESS; + + switch (hw->mac.type) { + case e1000_82571: +@@ -331,14 +320,14 @@ static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) + phy->id = IGP01E1000_I_PHY_ID; + break; + case e1000_82573: +- ret_val = e1000_get_phy_id(hw); ++ return e1000_get_phy_id(hw); + break; + default: +- ret_val = -E1000_ERR_PHY; ++ return -E1000_ERR_PHY; + break; + } + +- return ret_val; ++ return 0; + } + + /** +@@ -350,7 +339,6 @@ static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) + static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) + { + u32 swsm; +- s32 ret_val = E1000_SUCCESS; + s32 timeout = hw->nvm.word_size + 1; + s32 i = 0; + +@@ -370,12 +358,10 @@ static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) + /* Release semaphores */ + e1000_put_hw_semaphore(hw); + hw_dbg(hw, "Driver can't access the NVM\n"); +- ret_val = -E1000_ERR_NVM; +- goto out; ++ return -E1000_ERR_NVM; + } + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -410,7 +396,7 @@ static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) + + ret_val = e1000_get_hw_semaphore_82571(hw); + if (ret_val) +- goto out; ++ return ret_val; + + if (hw->mac.type != e1000_82573) + ret_val = e1000_acquire_nvm(hw); +@@ -418,7 +404,6 @@ static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) + if (ret_val) + e1000_put_hw_semaphore_82571(hw); + +-out: + return ret_val; + } + +@@ -449,7 +434,7 @@ static void e1000_release_nvm_82571(struct e1000_hw *hw) + static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, + u16 *data) + { +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val; + + switch (hw->mac.type) { + case e1000_82573: +@@ -483,12 +468,12 @@ static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) + + ret_val = e1000_update_nvm_checksum_generic(hw); + if (ret_val) +- goto out; ++ return ret_val; + + /* If our nvm is an EEPROM, then we're done + * otherwise, commit the checksum to the flash NVM. */ + if (hw->nvm.type != e1000_nvm_flash_hw) +- goto out; ++ return ret_val; + + /* Check for pending operations. */ + for (i = 0; i < E1000_FLASH_UPDATES; i++) { +@@ -497,10 +482,8 @@ static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) + break; + } + +- if (i == E1000_FLASH_UPDATES) { +- ret_val = -E1000_ERR_NVM; +- goto out; +- } ++ if (i == E1000_FLASH_UPDATES) ++ return -E1000_ERR_NVM; + + /* Reset the firmware if using STM opcode. */ + if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) { +@@ -522,13 +505,10 @@ static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) + break; + } + +- if (i == E1000_FLASH_UPDATES) { +- ret_val = -E1000_ERR_NVM; +- goto out; +- } ++ if (i == E1000_FLASH_UPDATES) ++ return -E1000_ERR_NVM; + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -573,8 +553,7 @@ static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, + if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || + (words == 0)) { + hw_dbg(hw, "nvm parameter(s) out of bounds\n"); +- ret_val = -E1000_ERR_NVM; +- goto out; ++ return -E1000_ERR_NVM; + } + + for (i = 0; i < words; i++) { +@@ -593,7 +572,6 @@ static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, + break; + } + +-out: + return ret_val; + } + +@@ -606,7 +584,6 @@ out: + static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) + { + s32 timeout = PHY_CFG_TIMEOUT; +- s32 ret_val = E1000_SUCCESS; + + while (timeout) { + if (er32(EEMNGCTL) & +@@ -617,12 +594,10 @@ static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) + } + if (!timeout) { + hw_dbg(hw, "MNG configuration cycle has not completed.\n"); +- ret_val = -E1000_ERR_RESET; +- goto out; ++ return -E1000_ERR_RESET; + } + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -644,20 +619,20 @@ static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) + + ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); + if (ret_val) +- goto out; ++ return ret_val; + + if (active) { + data |= IGP02E1000_PM_D0_LPLU; + ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); + if (ret_val) +- goto out; ++ return ret_val; + + /* When LPLU is enabled, we should disable SmartSpeed */ + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); + data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); + if (ret_val) +- goto out; ++ return ret_val; + } else { + data &= ~IGP02E1000_PM_D0_LPLU; + ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); +@@ -669,29 +644,28 @@ static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, + &data); + if (ret_val) +- goto out; ++ return ret_val; + + data |= IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, + data); + if (ret_val) +- goto out; ++ return ret_val; + } else if (phy->smart_speed == e1000_smart_speed_off) { + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, + &data); + if (ret_val) +- goto out; ++ return ret_val; + + data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, + data); + if (ret_val) +- goto out; ++ return ret_val; + } + } + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -762,7 +736,7 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw) + ret_val = e1000_get_auto_rd_done(hw); + if (ret_val) + /* We don't want to continue accessing MAC registers. */ +- goto out; ++ return ret_val; + + /* Phy configuration from NVM just starts after EECD_AUTO_RD is set. + * Need to wait for Phy configuration completion before accessing +@@ -775,8 +749,7 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw) + ew32(IMC, 0xffffffff); + icr = er32(ICR); + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -799,7 +772,7 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw) + ret_val = e1000_id_led_init(hw); + if (ret_val) { + hw_dbg(hw, "Error initializing identification LED\n"); +- goto out; ++ return ret_val; + } + + /* Disabling VLAN filtering */ +@@ -851,7 +824,6 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw) + */ + e1000_clear_hw_cntrs_82571(hw); + +-out: + return ret_val; + } + +@@ -1041,16 +1013,15 @@ static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) + ew32(LEDCTL, led_ctrl); + break; + default: +- ret_val = -E1000_ERR_PHY; ++ return -E1000_ERR_PHY; + break; + } + + if (ret_val) +- goto out; ++ return ret_val; + + ret_val = e1000_setup_copper_link(hw); + +-out: + return ret_val; + } + +@@ -1097,7 +1068,7 @@ static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) + ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); + if (ret_val) { + hw_dbg(hw, "NVM Read Error\n"); +- goto out; ++ return ret_val; + } + + if (hw->mac.type == e1000_82573 && +@@ -1107,8 +1078,7 @@ static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) + *data == ID_LED_RESERVED_FFFF) + *data = ID_LED_DEFAULT; + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -1135,7 +1105,7 @@ bool e1000_get_laa_state_82571(struct e1000_hw *hw) + void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) + { + if (hw->mac.type != e1000_82571) +- goto out; ++ return; + + hw->dev_spec.e82571.laa_is_present = state; + +@@ -1148,9 +1118,6 @@ void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) + * Eventually the LAA will be in RAR[0] and RAR[14]. + */ + e1000_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1); +- +-out: +- return; + } + + /** +@@ -1166,18 +1133,18 @@ out: + static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) + { + struct e1000_nvm_info *nvm = &hw->nvm; +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val; + u16 data; + + if (nvm->type != e1000_nvm_flash_hw) +- goto out; ++ return 0; + + /* Check bit 4 of word 10h. If it is 0, firmware is done updating + * 10h-12h. Checksum may need to be fixed. + */ + ret_val = e1000_read_nvm(hw, 0x10, 1, &data); + if (ret_val) +- goto out; ++ return ret_val; + + if (!(data & 0x10)) { + /* Read 0x23 and check bit 15. This bit is a 1 +@@ -1189,19 +1156,18 @@ static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) + */ + ret_val = e1000_read_nvm(hw, 0x23, 1, &data); + if (ret_val) +- goto out; ++ return ret_val; + + if (!(data & 0x8000)) { + data |= 0x8000; + ret_val = e1000_write_nvm(hw, 0x23, 1, &data); + if (ret_val) +- goto out; ++ return ret_val; + ret_val = e1000_update_nvm_checksum(hw); + } + } + +-out: +- return ret_val; ++ return 0; + } + + /** +diff --git a/drivers/net/e1000e/defines.h b/drivers/net/e1000e/defines.h +index e0a36f1..ca80fde 100644 +--- a/drivers/net/e1000e/defines.h ++++ b/drivers/net/e1000e/defines.h +@@ -413,7 +413,6 @@ + #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ + + /* Error Codes */ +-#define E1000_SUCCESS 0 + #define E1000_ERR_NVM 1 + #define E1000_ERR_PHY 2 + #define E1000_ERR_CONFIG 3 +diff --git a/drivers/net/e1000e/es2lan.c b/drivers/net/e1000e/es2lan.c +index b5143e9..5604c50 100644 +--- a/drivers/net/e1000e/es2lan.c ++++ b/drivers/net/e1000e/es2lan.c +@@ -111,11 +111,11 @@ static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex); + static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val; + + if (hw->media_type != e1000_media_type_copper) { + phy->type = e1000_phy_none; +- goto out; ++ return 0; + } + + phy->addr = 1; +@@ -127,12 +127,9 @@ static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) + ret_val = e1000_get_phy_id(hw); + + /* Verify phy id */ +- if (phy->id != GG82563_E_PHY_ID) { +- ret_val = -E1000_ERR_PHY; +- goto out; +- } ++ if (phy->id != GG82563_E_PHY_ID) ++ return -E1000_ERR_PHY; + +-out: + return ret_val; + } + +@@ -176,7 +173,7 @@ static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) + size += NVM_WORD_SIZE_BASE_SHIFT; + nvm->word_size = 1 << size; + +- return E1000_SUCCESS; ++ return 0; + } + + /** +@@ -190,7 +187,6 @@ static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter) + struct e1000_hw *hw = &adapter->hw; + struct e1000_mac_info *mac = &hw->mac; + struct e1000_mac_operations *func = &mac->ops; +- s32 ret_val = E1000_SUCCESS; + + /* Set media type */ + switch (adapter->pdev->device) { +@@ -225,13 +221,11 @@ static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter) + func->check_for_link = e1000_check_for_serdes_link; + break; + default: +- ret_val = -E1000_ERR_CONFIG; +- goto out; ++ return -E1000_ERR_CONFIG; + break; + } + +-out: +- return ret_val; ++ return 0; + } + + static s32 e1000_get_invariants_80003es2lan(struct e1000_adapter *adapter) +@@ -251,7 +245,7 @@ static s32 e1000_get_invariants_80003es2lan(struct e1000_adapter *adapter) + if (rc) + return rc; + +- return E1000_SUCCESS; ++ return 0; + } + + /** +@@ -298,14 +292,13 @@ static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) + + ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); + if (ret_val) +- goto out; ++ return ret_val; + + ret_val = e1000_acquire_nvm(hw); + + if (ret_val) + e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); + +-out: + return ret_val; + } + +@@ -335,15 +328,12 @@ static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) + u32 swfw_sync; + u32 swmask = mask; + u32 fwmask = mask << 16; +- s32 ret_val = E1000_SUCCESS; + s32 i = 0; + s32 timeout = 200; + + while (i < timeout) { +- if (e1000_get_hw_semaphore(hw)) { +- ret_val = -E1000_ERR_SWFW_SYNC; +- goto out; +- } ++ if (e1000_get_hw_semaphore(hw)) ++ return -E1000_ERR_SWFW_SYNC; + + swfw_sync = er32(SW_FW_SYNC); + if (!(swfw_sync & (fwmask | swmask))) +@@ -359,8 +349,7 @@ static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) + if (i == timeout) { + hw_dbg(hw, + "Driver can't access resource, SW_FW_SYNC timeout.\n"); +- ret_val = -E1000_ERR_SWFW_SYNC; +- goto out; ++ return -E1000_ERR_SWFW_SYNC; + } + + swfw_sync |= swmask; +@@ -368,8 +357,7 @@ static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) + + e1000_put_hw_semaphore(hw); + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -384,7 +372,7 @@ static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) + { + u32 swfw_sync; + +- while (e1000_get_hw_semaphore(hw) != E1000_SUCCESS); ++ while (e1000_get_hw_semaphore(hw) != 0); + /* Empty */ + + swfw_sync = er32(SW_FW_SYNC); +@@ -422,7 +410,7 @@ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, + temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); + ret_val = e1000_write_phy_reg_m88(hw, page_select, temp); + if (ret_val) +- goto out; ++ return ret_val; + + /* The "ready" bit in the MDIC register may be incorrectly set + * before the device has completed the "Page Select" MDI +@@ -435,7 +423,7 @@ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, + + if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { + ret_val = -E1000_ERR_PHY; +- goto out; ++ return ret_val; + } + + udelay(200); +@@ -446,7 +434,6 @@ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, + + udelay(200); + +-out: + return ret_val; + } + +@@ -478,7 +465,7 @@ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, + temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); + ret_val = e1000_write_phy_reg_m88(hw, page_select, temp); + if (ret_val) +- goto out; ++ return ret_val; + + + /* The "ready" bit in the MDIC register may be incorrectly set +@@ -490,10 +477,8 @@ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, + /* ...and verify the command was successful. */ + ret_val = e1000_read_phy_reg_m88(hw, page_select, &temp); + +- if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { +- ret_val = -E1000_ERR_PHY; +- goto out; +- } ++ if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) ++ return -E1000_ERR_PHY; + + udelay(200); + +@@ -503,7 +488,6 @@ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, + + udelay(200); + +-out: + return ret_val; + } + +@@ -533,7 +517,6 @@ static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, + static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) + { + s32 timeout = PHY_CFG_TIMEOUT; +- s32 ret_val = E1000_SUCCESS; + u32 mask = E1000_NVM_CFG_DONE_PORT_0; + + if (hw->bus.func == 1) +@@ -547,12 +530,10 @@ static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) + } + if (!timeout) { + hw_dbg(hw, "MNG configuration cycle has not completed.\n"); +- ret_val = -E1000_ERR_RESET; +- goto out; ++ return -E1000_ERR_RESET; + } + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -573,18 +554,18 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) + */ + ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); + if (ret_val) +- goto out; ++ return ret_val; + + phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; + ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data); + if (ret_val) +- goto out; ++ return ret_val; + + hw_dbg(hw, "GG82563 PSCR: %X\n", phy_data); + + ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); + if (ret_val) +- goto out; ++ return ret_val; + + e1000_phy_force_speed_duplex_setup(hw, &phy_data); + +@@ -593,7 +574,7 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) + + ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); + if (ret_val) +- goto out; ++ return ret_val; + + udelay(1); + +@@ -604,7 +585,7 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) + ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, + 100000, &link); + if (ret_val) +- goto out; ++ return ret_val; + + if (!link) { + /* We didn't get link. +@@ -612,19 +593,19 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) + */ + ret_val = e1000_phy_reset_dsp(hw); + if (ret_val) +- goto out; ++ return ret_val; + } + + /* Try once more */ + ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, + 100000, &link); + if (ret_val) +- goto out; ++ return ret_val; + } + + ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); + if (ret_val) +- goto out; ++ return ret_val; + + /* Resetting the phy means we need to verify the TX_CLK corresponds + * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. +@@ -641,7 +622,6 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) + phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; + ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); + +-out: + return ret_val; + } + +@@ -661,7 +641,7 @@ static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) + + ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); + if (ret_val) +- goto out; ++ return ret_val; + + index = phy_data & GG82563_DSPD_CABLE_LENGTH; + phy->min_cable_length = e1000_gg82563_cable_length_table[index]; +@@ -669,8 +649,7 @@ static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) + + phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -692,7 +671,7 @@ static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, + speed, + duplex); + if (ret_val) +- goto out; ++ return ret_val; + if (*speed == SPEED_1000) + ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); + else +@@ -704,7 +683,6 @@ static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, + duplex); + } + +-out: + return ret_val; + } + +@@ -745,14 +723,13 @@ static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) + ret_val = e1000_get_auto_rd_done(hw); + if (ret_val) + /* We don't want to continue accessing MAC registers. */ +- goto out; ++ return ret_val; + + /* Clear any pending interrupt events. */ + ew32(IMC, 0xffffffff); + icr = er32(ICR); + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -775,7 +752,7 @@ static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) + ret_val = e1000_id_led_init(hw); + if (ret_val) { + hw_dbg(hw, "Error initializing identification LED\n"); +- goto out; ++ return ret_val; + } + + /* Disabling VLAN filtering */ +@@ -833,7 +810,6 @@ static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) + */ + e1000_clear_hw_cntrs_80003es2lan(hw); + +-out: + return ret_val; + } + +@@ -881,15 +857,15 @@ static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) + **/ + static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) + { +- struct e1000_phy_info *phy = &hw->phy; +- s32 ret_val; ++ struct e1000_phy_info *phy = &hw->phy; ++ s32 ret_val; + u32 ctrl_ext; + u16 data; + + ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, + &data); + if (ret_val) +- goto out; ++ return ret_val; + + data |= GG82563_MSCR_ASSERT_CRS_ON_TX; + /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ +@@ -898,7 +874,7 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) + ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, + data); + if (ret_val) +- goto out; ++ return ret_val; + + /* Options: + * MDI/MDI-X = 0 (default) +@@ -909,7 +885,7 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) + */ + ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data); + if (ret_val) +- goto out; ++ return ret_val; + + data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; + +@@ -938,13 +914,13 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) + + ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data); + if (ret_val) +- goto out; ++ return ret_val; + + /* SW Reset the PHY so all changes take effect */ + ret_val = e1000_commit_phy(hw); + if (ret_val) { + hw_dbg(hw, "Error Resetting the PHY\n"); +- goto out; ++ return ret_val; + } + + /* Bypass RX and TX FIFO's */ +@@ -953,16 +929,16 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) + E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | + E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); + if (ret_val) +- goto out; ++ return ret_val; + + ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data); + if (ret_val) +- goto out; ++ return ret_val; + + data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; + ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data); + if (ret_val) +- goto out; ++ return ret_val; + + ctrl_ext = er32(CTRL_EXT); + ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); +@@ -970,7 +946,7 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) + + ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); + if (ret_val) +- goto out; ++ return ret_val; + + /* Do not init these registers when the HW is in IAMT mode, since the + * firmware will have already initialized them. We only initialize +@@ -981,16 +957,16 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) + data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; + ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data); + if (ret_val) +- goto out; ++ return ret_val; + + ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data); + if (ret_val) +- goto out; ++ return ret_val; + + data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; + ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data); + if (ret_val) +- goto out; ++ return ret_val; + } + + /* Workaround: Disable padding in Kumeran interface in the MAC +@@ -998,15 +974,14 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) + */ + ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data); + if (ret_val) +- goto out; ++ return ret_val; + + data |= GG82563_ICR_DIS_PADDING; + ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data); + if (ret_val) +- goto out; ++ return ret_val; + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -1019,7 +994,7 @@ out: + static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) + { + u32 ctrl; +- s32 ret_val; ++ s32 ret_val; + u16 reg_data; + + ctrl = er32(CTRL); +@@ -1032,34 +1007,33 @@ static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) + * polling the phy; this fixes erroneous timeouts at 10Mbps. */ + ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); + if (ret_val) +- goto out; ++ return ret_val; + ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); + if (ret_val) +- goto out; ++ return ret_val; + reg_data |= 0x3F; + ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); + if (ret_val) +- goto out; ++ return ret_val; + ret_val = e1000_read_kmrn_reg(hw, + E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, + ®_data); + if (ret_val) +- goto out; ++ return ret_val; + reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; + ret_val = e1000_write_kmrn_reg(hw, + E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, + reg_data); + if (ret_val) +- goto out; ++ return ret_val; + + ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); + if (ret_val) +- goto out; ++ return ret_val; + + ret_val = e1000_setup_copper_link(hw); + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -1072,7 +1046,7 @@ out: + **/ + static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) + { +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val; + u32 tipg; + u16 reg_data; + +@@ -1081,7 +1055,7 @@ static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) + E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, + reg_data); + if (ret_val) +- goto out; ++ return ret_val; + + /* Configure Transmit Inter-Packet Gap */ + tipg = er32(TIPG); +@@ -1091,7 +1065,7 @@ static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) + + ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); + if (ret_val) +- goto out; ++ return ret_val; + + if (duplex == HALF_DUPLEX) + reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; +@@ -1100,8 +1074,7 @@ static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) + + ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -1113,7 +1086,7 @@ out: + **/ + static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) + { +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val; + u16 reg_data; + u32 tipg; + +@@ -1122,7 +1095,7 @@ static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) + E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, + reg_data); + if (ret_val) +- goto out; ++ return ret_val; + + /* Configure Transmit Inter-Packet Gap */ + tipg = er32(TIPG); +@@ -1132,12 +1105,11 @@ static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) + + ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); + if (ret_val) +- goto out; ++ return ret_val; + + reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; + ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); + +-out: + return ret_val; + } + +diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c +index 5967139..042abd4 100644 +--- a/drivers/net/e1000e/ich8lan.c ++++ b/drivers/net/e1000e/ich8lan.c +@@ -187,7 +187,7 @@ static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) + static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val; + u16 i = 0; + + phy->addr = 1; +@@ -199,7 +199,7 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) + msleep(1); + ret_val = e1000_get_phy_id(hw); + if (ret_val) +- goto out; ++ return ret_val; + } + + /* Verify phy id */ +@@ -215,12 +215,11 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) + phy->autoneg_mask = E1000_ALL_NOT_GIG; + break; + default: +- ret_val = -E1000_ERR_PHY; +- goto out; ++ return -E1000_ERR_PHY; ++ break; + } + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -237,15 +236,13 @@ static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) + u32 gfpreg; + u32 sector_base_addr; + u32 sector_end_addr; +- s32 ret_val = E1000_SUCCESS; + u16 i; + + /* Can't read flash registers if the register set isn't mapped. + */ + if (!hw->flash_address) { + hw_dbg(hw, "ERROR: Flash registers not mapped\n"); +- ret_val = -E1000_ERR_CONFIG; +- goto out; ++ return -E1000_ERR_CONFIG; + } + + nvm->type = e1000_nvm_flash_sw; +@@ -277,8 +274,7 @@ static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) + dev_spec->shadow_ram[i].value = 0xFFFF; + } + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -309,7 +305,7 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter) + if (mac->type == e1000_ich8lan) + e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, 1); + +- return E1000_SUCCESS; ++ return 0; + } + + static s32 e1000_get_invariants_ich8lan(struct e1000_adapter *adapter) +@@ -333,7 +329,7 @@ static s32 e1000_get_invariants_ich8lan(struct e1000_adapter *adapter) + (adapter->hw.phy.type == e1000_phy_igp_3)) + adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; + +- return E1000_SUCCESS; ++ return 0; + } + + /** +@@ -348,7 +344,6 @@ static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) + { + u32 extcnf_ctrl; + u32 timeout = PHY_CFG_TIMEOUT; +- s32 ret_val = E1000_SUCCESS; + + while (timeout) { + extcnf_ctrl = er32(EXTCNF_CTRL); +@@ -364,12 +359,10 @@ static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) + + if (!timeout) { + hw_dbg(hw, "FW or HW has locked the resource for too long.\n"); +- ret_val = -E1000_ERR_CONFIG; +- goto out; ++ return -E1000_ERR_CONFIG; + } + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -403,8 +396,7 @@ static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) + + fwsm = er32(FWSM); + +- return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS +- : E1000_BLK_PHY_RESET; ++ return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET; + } + + /** +@@ -424,30 +416,30 @@ static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw) + + if (phy->type != e1000_phy_ife) { + ret_val = e1000_phy_force_speed_duplex_igp(hw); +- goto out; ++ return ret_val; + } + + ret_val = e1e_rphy(hw, PHY_CONTROL, &data); + if (ret_val) +- goto out; ++ return ret_val; + + e1000_phy_force_speed_duplex_setup(hw, &data); + + ret_val = e1e_wphy(hw, PHY_CONTROL, data); + if (ret_val) +- goto out; ++ return ret_val; + + /* Disable MDI-X support for 10/100 */ + ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); + if (ret_val) +- goto out; ++ return ret_val; + + data &= ~IFE_PMC_AUTO_MDIX; + data &= ~IFE_PMC_FORCE_MDIX; + + ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data); + if (ret_val) +- goto out; ++ return ret_val; + + hw_dbg(hw, "IFE PMC: %X\n", data); + +@@ -461,7 +453,7 @@ static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw) + 100000, + &link); + if (ret_val) +- goto out; ++ return ret_val; + + if (!link) + hw_dbg(hw, "Link taking longer than expected.\n"); +@@ -472,11 +464,10 @@ static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw) + 100000, + &link); + if (ret_val) +- goto out; ++ return ret_val; + } + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -498,7 +489,7 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) + + ret_val = e1000_phy_hw_reset_generic(hw); + if (ret_val) +- goto out; ++ return ret_val; + + /* Initialize the PHY from the NVM on ICH platforms. This + * is needed due to an issue where the NVM configuration is +@@ -518,7 +509,7 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) + + data = er32(FEXTNVM); + if (!(data & sw_cfg_mask)) +- goto out; ++ return 0; + + /* Wait for basic configuration completes before proceeding*/ + do { +@@ -544,13 +535,13 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) + * extended configuration before SW configuration */ + data = er32(EXTCNF_CTRL); + if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) +- goto out; ++ return 0; + + cnf_size = er32(EXTCNF_SIZE); + cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; + cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; + if (!cnf_size) +- goto out; ++ return 0; + + cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; + cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; +@@ -567,14 +558,14 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) + 1, + ®_data); + if (ret_val) +- goto out; ++ return ret_val; + + ret_val = e1000_read_nvm(hw, + (word_addr + i * 2 + 1), + 1, + ®_addr); + if (ret_val) +- goto out; ++ return ret_val; + + /* Save off the PHY page for future writes. */ + if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { +@@ -586,12 +577,11 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) + + ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data); + if (ret_val) +- goto out; ++ return ret_val; + } + } + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -611,23 +601,22 @@ static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw) + + ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); + if (ret_val) +- goto out; ++ return ret_val; + + if (!link) { + hw_dbg(hw, "Phy info is only valid if link is up\n"); +- ret_val = -E1000_ERR_CONFIG; +- goto out; ++ return -E1000_ERR_CONFIG; + } + + ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data); + if (ret_val) +- goto out; ++ return ret_val; + phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE)); + + if (phy->polarity_correction) { + ret_val = e1000_check_polarity_ife_ich8lan(hw); + if (ret_val) +- goto out; ++ return ret_val; + } else { + /* Polarity is forced */ + phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) +@@ -637,7 +626,7 @@ static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw) + + ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); + if (ret_val) +- goto out; ++ return ret_val; + + phy->is_mdix = (data & IFE_PMC_MDIX_STATUS); + +@@ -646,8 +635,7 @@ static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw) + phy->local_rx = e1000_1000t_rx_status_undefined; + phy->remote_rx = e1000_1000t_rx_status_undefined; + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -660,20 +648,18 @@ out: + **/ + static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw) + { +- s32 ret_val = -E1000_ERR_PHY_TYPE; +- + switch (hw->phy.type) { + case e1000_phy_ife: +- ret_val = e1000_get_phy_info_ife_ich8lan(hw); ++ return e1000_get_phy_info_ife_ich8lan(hw); + break; + case e1000_phy_igp_3: +- ret_val = e1000_get_phy_info_igp(hw); ++ return e1000_get_phy_info_igp(hw); + break; + default: + break; + } + +- return ret_val; ++ return -E1000_ERR_PHY_TYPE; + } + + /** +@@ -728,11 +714,11 @@ static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) + { + struct e1000_phy_info *phy = &hw->phy; + u32 phy_ctrl; +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val = 0; + u16 data; + + if (phy->type != e1000_phy_igp_3) +- goto out; ++ return ret_val; + + phy_ctrl = er32(PHY_CTRL); + +@@ -751,7 +737,7 @@ static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) + data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); + if (ret_val) +- goto out; ++ return ret_val; + } else { + phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; + ew32(PHY_CTRL, phy_ctrl); +@@ -764,29 +750,28 @@ static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, + &data); + if (ret_val) +- goto out; ++ return ret_val; + + data |= IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, + data); + if (ret_val) +- goto out; ++ return ret_val; + } else if (phy->smart_speed == e1000_smart_speed_off) { + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, + &data); + if (ret_val) +- goto out; ++ return ret_val; + + data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, + data); + if (ret_val) +- goto out; ++ return ret_val; + } + } + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -806,7 +791,7 @@ static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) + { + struct e1000_phy_info *phy = &hw->phy; + u32 phy_ctrl; +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val; + u16 data; + + phy_ctrl = er32(PHY_CTRL); +@@ -823,27 +808,27 @@ static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) + IGP01E1000_PHY_PORT_CONFIG, + &data); + if (ret_val) +- goto out; ++ return ret_val; + + data |= IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1e_wphy(hw, + IGP01E1000_PHY_PORT_CONFIG, + data); + if (ret_val) +- goto out; ++ return ret_val; + } else if (phy->smart_speed == e1000_smart_speed_off) { + ret_val = e1e_rphy(hw, + IGP01E1000_PHY_PORT_CONFIG, + &data); + if (ret_val) +- goto out; ++ return ret_val; + + data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1e_wphy(hw, + IGP01E1000_PHY_PORT_CONFIG, + data); + if (ret_val) +- goto out; ++ return ret_val; + } + } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || + (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || +@@ -862,7 +847,7 @@ static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) + IGP01E1000_PHY_PORT_CONFIG, + &data); + if (ret_val) +- goto out; ++ return ret_val; + + data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1e_wphy(hw, +@@ -870,8 +855,7 @@ static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) + data); + } + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -889,19 +873,18 @@ static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, + struct e1000_nvm_info *nvm = &hw->nvm; + struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; + u32 act_offset; +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val; + u16 i, word; + + if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || + (words == 0)) { + hw_dbg(hw, "nvm parameter(s) out of bounds\n"); +- ret_val = -E1000_ERR_NVM; +- goto out; ++ return -E1000_ERR_NVM; + } + + ret_val = e1000_acquire_swflag_ich8lan(hw); + if (ret_val) +- goto out; ++ return ret_val; + + /* Start with the bank offset, then add the relative offset. */ + act_offset = (er32(EECD) & E1000_EECD_SEC1VAL) +@@ -925,7 +908,6 @@ static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, + + e1000_release_swflag_ich8lan(hw); + +-out: + return ret_val; + } + +@@ -948,7 +930,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) + if (hsfsts.hsf_status.fldesvalid == 0) { + hw_dbg(hw, "Flash descriptor invalid. " + "SW Sequencing must be used."); +- goto out; ++ return -E1000_ERR_NVM; + } + + /* Clear FCERR and DAEL in hw status by writing 1 */ +@@ -971,19 +953,19 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) + /* Begin by setting Flash Cycle Done. */ + hsfsts.hsf_status.flcdone = 1; + ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); +- ret_val = E1000_SUCCESS; ++ ret_val = 0; + } else { + /* otherwise poll for sometime so the current + * cycle has a chance to end before giving up. */ + for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { + hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS); + if (hsfsts.hsf_status.flcinprog == 0) { +- ret_val = E1000_SUCCESS; ++ ret_val = 0; + break; + } + udelay(1); + } +- if (ret_val == E1000_SUCCESS) { ++ if (ret_val == 0) { + /* Successful in waiting for previous cycle to timeout, + * now set the Flash Cycle Done. */ + hsfsts.hsf_status.flcdone = 1; +@@ -993,7 +975,6 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) + } + } + +-out: + return ret_val; + } + +@@ -1025,7 +1006,7 @@ static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) + } while (i++ < timeout); + + if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) +- ret_val = E1000_SUCCESS; ++ return 0; + + return ret_val; + } +@@ -1042,20 +1023,10 @@ static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) + static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, + u16 *data) + { +- s32 ret_val; +- +- if (!data) { +- ret_val = -E1000_ERR_NVM; +- goto out; +- } +- + /* Must convert offset into bytes. */ + offset <<= 1; + +- ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data); +- +-out: +- return ret_val; ++ return e1000_read_flash_data_ich8lan(hw, offset, 2, data); + } + + /** +@@ -1078,7 +1049,7 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, + u8 count = 0; + + if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) +- goto out; ++ return -E1000_ERR_NVM; + + flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + + hw->nvm.flash_base_addr; +@@ -1087,7 +1058,7 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, + udelay(1); + /* Steps */ + ret_val = e1000_flash_cycle_init_ich8lan(hw); +- if (ret_val != E1000_SUCCESS) ++ if (ret_val != 0) + break; + + hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); +@@ -1105,7 +1076,7 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, + * and try the whole sequence a few more times, else + * read in (shift in) the Flash Data0, the order is + * least significant byte first msb to lsb */ +- if (ret_val == E1000_SUCCESS) { ++ if (ret_val == 0) { + flash_data = er32flash(ICH_FLASH_FDATA0); + if (size == 1) { + *data = (u8)(flash_data & 0x000000FF); +@@ -1131,7 +1102,6 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, + } + } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); + +-out: + return ret_val; + } + +@@ -1149,19 +1119,18 @@ static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, + { + struct e1000_nvm_info *nvm = &hw->nvm; + struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val; + u16 i; + + if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || + (words == 0)) { + hw_dbg(hw, "nvm parameter(s) out of bounds\n"); +- ret_val = -E1000_ERR_NVM; +- goto out; ++ return -E1000_ERR_NVM; + } + + ret_val = e1000_acquire_swflag_ich8lan(hw); + if (ret_val) +- goto out; ++ return ret_val; + + for (i = 0; i < words; i++) { + dev_spec->shadow_ram[offset+i].modified = 1; +@@ -1170,8 +1139,7 @@ static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, + + e1000_release_swflag_ich8lan(hw); + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -1195,14 +1163,14 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) + + ret_val = e1000_update_nvm_checksum_generic(hw); + if (ret_val) +- goto out; ++ return ret_val;; + + if (nvm->type != e1000_nvm_flash_sw) +- goto out; ++ return ret_val;; + + ret_val = e1000_acquire_swflag_ich8lan(hw); + if (ret_val) +- goto out; ++ return ret_val;; + + /* We're writing to the opposite bank so if we're on bank 1, + * write to bank 0 etc. We also need to erase the segment that +@@ -1262,7 +1230,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) + if (ret_val) { + hw_dbg(hw, "Flash commit failed.\n"); + e1000_release_swflag_ich8lan(hw); +- goto out; ++ return ret_val; + } + + /* Finally validate the new segment by setting bit 15:14 +@@ -1277,7 +1245,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) + (u8)(data >> 8)); + if (ret_val) { + e1000_release_swflag_ich8lan(hw); +- goto out; ++ return ret_val; + } + + /* And invalidate the previously valid segment by setting +@@ -1288,7 +1256,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) + ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); + if (ret_val) { + e1000_release_swflag_ich8lan(hw); +- goto out; ++ return ret_val; + } + + /* Great! Everything worked, we can now clear the cached entries. */ +@@ -1305,7 +1273,6 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) + e1000_reload_nvm(hw); + msleep(10); + +-out: + return ret_val; + } + +@@ -1319,7 +1286,7 @@ out: + **/ + static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) + { +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val; + u16 data; + + /* Read 0x19 and check bit 6. If this bit is 0, the checksum +@@ -1329,22 +1296,19 @@ static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) + */ + ret_val = e1000_read_nvm(hw, 0x19, 1, &data); + if (ret_val) +- goto out; ++ return ret_val; + + if ((data & 0x40) == 0) { + data |= 0x40; + ret_val = e1000_write_nvm(hw, 0x19, 1, &data); + if (ret_val) +- goto out; ++ return ret_val; + ret_val = e1000_update_nvm_checksum(hw); + if (ret_val) +- goto out; ++ return ret_val; + } + +- ret_val = e1000_validate_nvm_checksum_generic(hw); +- +-out: +- return ret_val; ++ return e1000_validate_nvm_checksum_generic(hw); + } + + /** +@@ -1363,12 +1327,12 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, + union ich8_hws_flash_ctrl hsflctl; + u32 flash_linear_addr; + u32 flash_data = 0; +- s32 ret_val = -E1000_ERR_NVM; ++ s32 ret_val; + u8 count = 0; + + if (size < 1 || size > 2 || data > size * 0xff || + offset > ICH_FLASH_LINEAR_ADDR_MASK) +- goto out; ++ return -E1000_ERR_NVM; + + flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + + hw->nvm.flash_base_addr; +@@ -1377,7 +1341,7 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, + udelay(1); + /* Steps */ + ret_val = e1000_flash_cycle_init_ich8lan(hw); +- if (ret_val != E1000_SUCCESS) ++ if (ret_val) + break; + + hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); +@@ -1399,27 +1363,25 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, + * and try the whole sequence a few more times else done */ + ret_val = e1000_flash_cycle_ich8lan(hw, + ICH_FLASH_WRITE_COMMAND_TIMEOUT); +- if (ret_val == E1000_SUCCESS) { ++ if (!ret_val) ++ break; ++ ++ /* If we're here, then things are most likely ++ * completely hosed, but if the error condition ++ * is detected, it won't hurt to give it another ++ * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. ++ */ ++ hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); ++ if (hsfsts.hsf_status.flcerr == 1) ++ /* Repeat for some time before giving up. */ ++ continue; ++ if (hsfsts.hsf_status.flcdone == 0) { ++ hw_dbg(hw, "Timeout error - flash cycle " ++ "did not complete."); + break; +- } else { +- /* If we're here, then things are most likely +- * completely hosed, but if the error condition +- * is detected, it won't hurt to give it another +- * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. +- */ +- hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); +- if (hsfsts.hsf_status.flcerr == 1) { +- /* Repeat for some time before giving up. */ +- continue; +- } else if (hsfsts.hsf_status.flcdone == 0) { +- hw_dbg(hw, "Timeout error - flash cycle " +- "did not complete."); +- break; +- } + } + } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); + +-out: + return ret_val; + } + +@@ -1455,23 +1417,20 @@ static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, + u16 program_retries; + + ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); +- if (ret_val == E1000_SUCCESS) +- goto out; ++ if (!ret_val) ++ return ret_val; + + for (program_retries = 0; program_retries < 100; program_retries++) { + hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset); + udelay(100); + ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); +- if (ret_val == E1000_SUCCESS) ++ if (!ret_val) + break; + } +- if (program_retries == 100) { +- ret_val = -E1000_ERR_NVM; +- goto out; +- } ++ if (program_retries == 100) ++ return -E1000_ERR_NVM; + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -1490,9 +1449,11 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) + u32 flash_linear_addr; + /* bank size is in 16bit words - adjust to bytes */ + u32 flash_bank_size = nvm->flash_bank_size * 2; +- s32 ret_val = E1000_SUCCESS; +- s32 count = 0; +- s32 j, iteration, sector_size; ++ s32 ret_val; ++ s32 count = 0; ++ s32 iteration; ++ s32 sector_size; ++ s32 j; + + hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); + +@@ -1523,8 +1484,7 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) + sector_size = ICH_FLASH_SEG_SIZE_8K; + iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K; + } else { +- ret_val = -E1000_ERR_NVM; +- goto out; ++ return -E1000_ERR_NVM; + } + break; + case 3: +@@ -1532,8 +1492,7 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) + iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K; + break; + default: +- ret_val = -E1000_ERR_NVM; +- goto out; ++ return -E1000_ERR_NVM; + } + + /* Start with the base address, then add the sector offset. */ +@@ -1545,7 +1504,7 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) + /* Steps */ + ret_val = e1000_flash_cycle_init_ich8lan(hw); + if (ret_val) +- goto out; ++ return ret_val; + + /* Write a value 11 (block Erase) in Flash + * Cycle field in hw flash control */ +@@ -1562,25 +1521,23 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) + + ret_val = e1000_flash_cycle_ich8lan(hw, + ICH_FLASH_ERASE_COMMAND_TIMEOUT); +- if (ret_val == E1000_SUCCESS) { ++ if (ret_val == 0) + break; +- } else { +- /* Check if FCERR is set to 1. If 1, +- * clear it and try the whole sequence +- * a few more times else Done */ +- hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); +- if (hsfsts.hsf_status.flcerr == 1) { +- /* repeat for some time before +- * giving up */ +- continue; +- } else if (hsfsts.hsf_status.flcdone == 0) +- goto out; +- } ++ ++ /* Check if FCERR is set to 1. If 1, ++ * clear it and try the whole sequence ++ * a few more times else Done */ ++ hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); ++ if (hsfsts.hsf_status.flcerr == 1) ++ /* repeat for some time before ++ * giving up */ ++ continue; ++ else if (hsfsts.hsf_status.flcdone == 0) ++ return ret_val; + } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); + } + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -1599,15 +1556,14 @@ static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) + ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); + if (ret_val) { + hw_dbg(hw, "NVM Read Error\n"); +- goto out; ++ return ret_val; + } + + if (*data == ID_LED_RESERVED_0000 || + *data == ID_LED_RESERVED_FFFF) + *data = ID_LED_DEFAULT_ICH8LAN; + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -1735,7 +1691,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) + ret_val = e1000_id_led_init(hw); + if (ret_val) { + hw_dbg(hw, "Error initializing identification LED\n"); +- goto out; ++ return ret_val; + } + + /* Setup the receive address. */ +@@ -1782,8 +1738,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) + */ + e1000_clear_hw_cntrs_ich8lan(hw); + +-out: +- return ret_val; ++ return 0; + } + /** + * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits +@@ -1848,10 +1803,10 @@ static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) + static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) + { + struct e1000_mac_info *mac = &hw->mac; +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val; + + if (e1000_check_reset_block(hw)) +- goto out; ++ return 0; + + /* ICH parts do not have a word in the NVM to determine + * the default flow control setting, so we explicitly +@@ -1867,14 +1822,11 @@ static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) + /* Continue to configure the copper link. */ + ret_val = e1000_setup_copper_link_ich8lan(hw); + if (ret_val) +- goto out; ++ return ret_val; + + ew32(FCTTV, mac->fc_pause_time); + +- ret_val = e1000_set_fc_watermarks(hw); +- +-out: +- return ret_val; ++ return e1000_set_fc_watermarks(hw); + } + + /** +@@ -1901,25 +1853,22 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) + * this fixes erroneous timeouts at 10Mbps. */ + ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); + if (ret_val) +- goto out; ++ return ret_val; + ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); + if (ret_val) +- goto out; ++ return ret_val; + reg_data |= 0x3F; + ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); + if (ret_val) +- goto out; ++ return ret_val; + + if (hw->phy.type == e1000_phy_igp_3) { + ret_val = e1000_copper_link_setup_igp(hw); + if (ret_val) +- goto out; ++ return ret_val; + } + +- ret_val = e1000_setup_copper_link(hw); +- +-out: +- return ret_val; ++ return e1000_setup_copper_link(hw); + } + + /** +@@ -1939,7 +1888,7 @@ static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, + + ret_val = e1000_get_speed_and_duplex_copper(hw, speed, duplex); + if (ret_val) +- goto out; ++ return ret_val; + + if ((hw->mac.type == e1000_ich8lan) && + (hw->phy.type == e1000_phy_igp_3) && +@@ -1947,7 +1896,6 @@ static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, + ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); + } + +-out: + return ret_val; + } + +@@ -1970,37 +1918,33 @@ static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) + { + struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; + u32 phy_ctrl; +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val; + u16 i, data; + bool link; + + if (!dev_spec->kmrn_lock_loss_workaround_enabled) +- goto out; ++ return 0; + + /* Make sure link is up before proceeding. If not just return. + * Attempting this while link is negotiating fouled up link + * stability */ + ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); +- if (!link) { +- ret_val = E1000_SUCCESS; +- goto out; +- } ++ if (!link) ++ return 0; + + for (i = 0; i < 10; i++) { + /* read once to clear */ + ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); + if (ret_val) +- goto out; ++ return ret_val; + /* and again to get new status */ + ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); + if (ret_val) +- goto out; ++ return ret_val; + + /* check for PCS lock */ +- if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) { +- ret_val = E1000_SUCCESS; +- goto out; +- } ++ if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) ++ return 0; + + /* Issue PHY reset */ + e1000_phy_hw_reset(hw); +@@ -2017,10 +1961,7 @@ static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) + e1000_gig_downshift_workaround_ich8lan(hw); + + /* unable to acquire PCS lock */ +- ret_val = -E1000_ERR_PHY; +- +-out: +- return ret_val; ++ return -E1000_ERR_PHY; + } + + /** +@@ -2038,13 +1979,10 @@ void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, + + if (hw->mac.type != e1000_ich8lan) { + hw_dbg(hw, "Workaround applies to ICH8 only.\n"); +- goto out; ++ return; + } + + dev_spec->kmrn_lock_loss_workaround_enabled = state; +- +-out: +- return; + } + + /** +@@ -2064,7 +2002,7 @@ void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) + u8 retry = 0; + + if (hw->phy.type != e1000_phy_igp_3) +- goto out; ++ return; + + /* Try the workaround twice (if needed) */ + do { +@@ -2095,9 +2033,6 @@ void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) + ew32(CTRL, reg | E1000_CTRL_PHY_RST); + retry++; + } while (retry); +- +-out: +- return; + } + + /** +@@ -2112,27 +2047,25 @@ out: + **/ + void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) + { +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val; + u16 reg_data; + + if ((hw->mac.type != e1000_ich8lan) || + (hw->phy.type != e1000_phy_igp_3)) +- goto out; ++ return; + + ret_val = e1000_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, + ®_data); + if (ret_val) +- goto out; ++ return; + reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; + ret_val = e1000_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, + reg_data); + if (ret_val) +- goto out; ++ return; + reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; + ret_val = e1000_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, + reg_data); +-out: +- return; + } + + /** +@@ -2143,14 +2076,11 @@ out: + **/ + static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) + { +- s32 ret_val = E1000_SUCCESS; +- + if (hw->phy.type == e1000_phy_ife) +- ret_val = e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); +- else +- ew32(LEDCTL, hw->mac.ledctl_default); ++ return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); + +- return ret_val; ++ ew32(LEDCTL, hw->mac.ledctl_default); ++ return 0; + } + + /** +@@ -2161,15 +2091,12 @@ static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) + **/ + static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) + { +- s32 ret_val = E1000_SUCCESS; +- + if (hw->phy.type == e1000_phy_ife) +- ret_val = e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, ++ return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, + (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); +- else +- ew32(LEDCTL, hw->mac.ledctl_mode2); + +- return ret_val; ++ ew32(LEDCTL, hw->mac.ledctl_mode2); ++ return 0; + } + + /** +@@ -2180,16 +2107,12 @@ static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) + **/ + static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) + { +- s32 ret_val = E1000_SUCCESS; +- + if (hw->phy.type == e1000_phy_ife) +- ret_val = e1e_wphy(hw, +- IFE_PHY_SPECIAL_CONTROL_LED, ++ return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, + (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); +- else +- ew32(LEDCTL, hw->mac.ledctl_mode1); + +- return ret_val; ++ ew32(LEDCTL, hw->mac.ledctl_mode1); ++ return 0; + } + + /** +diff --git a/drivers/net/e1000e/lib.c b/drivers/net/e1000e/lib.c +index 21c16e0..d11b518 100644 +--- a/drivers/net/e1000e/lib.c ++++ b/drivers/net/e1000e/lib.c +@@ -81,7 +81,7 @@ s32 e1000_get_bus_info_pcie(struct e1000_hw *hw) + bus->func = 0; + } + +- return E1000_SUCCESS; ++ return 0; + } + + /** +@@ -378,10 +378,8 @@ s32 e1000_check_for_copper_link(struct e1000_hw *hw) + * get_link_status flag is set upon receiving a Link Status + * Change or Rx Sequence Error interrupt. + */ +- if (!mac->get_link_status) { +- ret_val = E1000_SUCCESS; +- goto out; +- } ++ if (!mac->get_link_status) ++ return 0; + + /* First we want to see if the MII Status Register reports + * link. If so, then we want to get the current speed/duplex +@@ -389,10 +387,10 @@ s32 e1000_check_for_copper_link(struct e1000_hw *hw) + */ + ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); + if (ret_val) +- goto out; ++ return ret_val; + + if (!link) +- goto out; /* No link detected */ ++ return ret_val; /* No link detected */ + + mac->get_link_status = 0; + +@@ -405,7 +403,7 @@ s32 e1000_check_for_copper_link(struct e1000_hw *hw) + */ + if (!mac->autoneg) { + ret_val = -E1000_ERR_CONFIG; +- goto out; ++ return ret_val; + } + + /* Auto-Neg is enabled. Auto Speed Detection takes care +@@ -424,7 +422,6 @@ s32 e1000_check_for_copper_link(struct e1000_hw *hw) + hw_dbg(hw, "Error configuring flow control\n"); + } + +-out: + return ret_val; + } + +@@ -441,7 +438,7 @@ s32 e1000_check_for_fiber_link(struct e1000_hw *hw) + u32 rxcw; + u32 ctrl; + u32 status; +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val; + + ctrl = er32(CTRL); + status = er32(STATUS); +@@ -459,7 +456,7 @@ s32 e1000_check_for_fiber_link(struct e1000_hw *hw) + (!(rxcw & E1000_RXCW_C))) { + if (mac->autoneg_failed == 0) { + mac->autoneg_failed = 1; +- goto out; ++ return 0; + } + hw_dbg(hw, "NOT RXing /C/, disable AutoNeg and force link.\n"); + +@@ -475,7 +472,7 @@ s32 e1000_check_for_fiber_link(struct e1000_hw *hw) + ret_val = e1000_config_fc_after_link_up(hw); + if (ret_val) { + hw_dbg(hw, "Error configuring flow control\n"); +- goto out; ++ return ret_val; + } + } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { + /* If we are forcing link and we are receiving /C/ ordered +@@ -490,8 +487,7 @@ s32 e1000_check_for_fiber_link(struct e1000_hw *hw) + mac->serdes_has_link = 1; + } + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -507,7 +503,7 @@ s32 e1000_check_for_serdes_link(struct e1000_hw *hw) + u32 rxcw; + u32 ctrl; + u32 status; +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val; + + ctrl = er32(CTRL); + status = er32(STATUS); +@@ -523,7 +519,7 @@ s32 e1000_check_for_serdes_link(struct e1000_hw *hw) + if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { + if (mac->autoneg_failed == 0) { + mac->autoneg_failed = 1; +- goto out; ++ return 0; + } + hw_dbg(hw, "NOT RXing /C/, disable AutoNeg and force link.\n"); + +@@ -539,7 +535,7 @@ s32 e1000_check_for_serdes_link(struct e1000_hw *hw) + ret_val = e1000_config_fc_after_link_up(hw); + if (ret_val) { + hw_dbg(hw, "Error configuring flow control\n"); +- goto out; ++ return ret_val; + } + } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { + /* If we are forcing link and we are receiving /C/ ordered +@@ -575,8 +571,7 @@ s32 e1000_check_for_serdes_link(struct e1000_hw *hw) + mac->serdes_has_link = (status & E1000_STATUS_LU); + } + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -589,11 +584,11 @@ out: + static s32 e1000_set_default_fc_generic(struct e1000_hw *hw) + { + struct e1000_mac_info *mac = &hw->mac; +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val; + u16 nvm_data; + + if (mac->fc != e1000_fc_default) +- goto out; ++ return 0; + + /* Read and store word 0x0F of the EEPROM. This word contains bits + * that determine the hardware's default PAUSE (flow control) mode, +@@ -607,7 +602,7 @@ static s32 e1000_set_default_fc_generic(struct e1000_hw *hw) + + if (ret_val) { + hw_dbg(hw, "NVM Read Error\n"); +- goto out; ++ return ret_val; + } + + if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) +@@ -618,8 +613,7 @@ static s32 e1000_set_default_fc_generic(struct e1000_hw *hw) + else + mac->fc = e1000_fc_full; + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -635,17 +629,17 @@ out: + s32 e1000_setup_link(struct e1000_hw *hw) + { + struct e1000_mac_info *mac = &hw->mac; +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val; + + /* In the case of the phy reset being blocked, we already have a link. + * We do not need to set it up again. + */ + if (e1000_check_reset_block(hw)) +- goto out; ++ return 0; + + ret_val = e1000_set_default_fc_generic(hw); + if (ret_val) +- goto out; ++ return ret_val; + + /* We want to save off the original Flow Control configuration just + * in case we get disconnected and then reconnected into a different +@@ -658,7 +652,7 @@ s32 e1000_setup_link(struct e1000_hw *hw) + /* Call the necessary media_type subroutine to configure the link. */ + ret_val = mac->ops.setup_physical_interface(hw); + if (ret_val) +- goto out; ++ return ret_val; + + /* Initialize the flow control address, type, and PAUSE timer + * registers to their default values. This is done even if flow +@@ -672,10 +666,7 @@ s32 e1000_setup_link(struct e1000_hw *hw) + + ew32(FCTTV, mac->fc_pause_time); + +- ret_val = e1000_set_fc_watermarks(hw); +- +-out: +- return ret_val; ++ return e1000_set_fc_watermarks(hw); + } + + /** +@@ -689,7 +680,6 @@ static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) + { + struct e1000_mac_info *mac = &hw->mac; + u32 txcw; +- s32 ret_val = E1000_SUCCESS; + + /* Check for a software override of the flow control settings, and + * setup the device accordingly. If auto-negotiation is enabled, then +@@ -736,16 +726,14 @@ static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) + break; + default: + hw_dbg(hw, "Flow control param set incorrectly\n"); +- ret_val = -E1000_ERR_CONFIG; +- goto out; ++ return -E1000_ERR_CONFIG; + break; + } + + ew32(TXCW, txcw); + mac->txcw = txcw; + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -759,7 +747,7 @@ static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) + { + struct e1000_mac_info *mac = &hw->mac; + u32 i, status; +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val; + + /* If we have a signal (the cable is plugged in, or assumed true for + * serdes media) then poll for a "Link-Up" indication in the Device +@@ -784,7 +772,7 @@ static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) + ret_val = mac->ops.check_for_link(hw); + if (ret_val) { + hw_dbg(hw, "Error while checking for link\n"); +- goto out; ++ return ret_val; + } + mac->autoneg_failed = 0; + } else { +@@ -792,8 +780,7 @@ static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) + hw_dbg(hw, "Valid Link Found\n"); + } + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -806,7 +793,7 @@ out: + s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw) + { + u32 ctrl; +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val; + + ctrl = er32(CTRL); + +@@ -817,7 +804,7 @@ s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw) + + ret_val = e1000_commit_fc_settings_generic(hw); + if (ret_val) +- goto out; ++ return ret_val; + + /* Since auto-negotiation is enabled, take the link out of reset (the + * link will be in reset, because we previously reset the chip). This +@@ -842,8 +829,7 @@ s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw) + hw_dbg(hw, "No signal detected\n"); + } + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -878,7 +864,6 @@ void e1000_config_collision_dist(struct e1000_hw *hw) + s32 e1000_set_fc_watermarks(struct e1000_hw *hw) + { + struct e1000_mac_info *mac = &hw->mac; +- s32 ret_val = E1000_SUCCESS; + u32 fcrtl = 0, fcrth = 0; + + /* Set the flow control receive threshold registers. Normally, +@@ -894,13 +879,12 @@ s32 e1000_set_fc_watermarks(struct e1000_hw *hw) + */ + fcrtl = mac->fc_low_water; + fcrtl |= E1000_FCRTL_XONE; +- + fcrth = mac->fc_high_water; + } + ew32(FCRTL, fcrtl); + ew32(FCRTH, fcrth); + +- return ret_val; ++ return 0; + } + + /** +@@ -917,7 +901,6 @@ s32 e1000_force_mac_fc(struct e1000_hw *hw) + { + struct e1000_mac_info *mac = &hw->mac; + u32 ctrl; +- s32 ret_val = E1000_SUCCESS; + + ctrl = er32(CTRL); + +@@ -957,14 +940,12 @@ s32 e1000_force_mac_fc(struct e1000_hw *hw) + break; + default: + hw_dbg(hw, "Flow control param set incorrectly\n"); +- ret_val = -E1000_ERR_CONFIG; +- goto out; ++ return -E1000_ERR_CONFIG; + } + + ew32(CTRL, ctrl); + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -980,7 +961,7 @@ out: + s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) + { + struct e1000_mac_info *mac = &hw->mac; +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val = 0; + u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; + u16 speed, duplex; + +@@ -999,7 +980,7 @@ s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) + + if (ret_val) { + hw_dbg(hw, "Error forcing flow control settings\n"); +- goto out; ++ return ret_val; + } + + /* Check for the case where we have copper media and auto-neg is +@@ -1014,15 +995,15 @@ s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) + */ + ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg); + if (ret_val) +- goto out; ++ return ret_val; + ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg); + if (ret_val) +- goto out; ++ return ret_val; + + if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { + hw_dbg(hw, "Copper PHY and Auto Neg " + "has not completed.\n"); +- goto out; ++ return ret_val; + } + + /* The AutoNeg process has completed, so we now need to +@@ -1033,10 +1014,10 @@ s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) + */ + ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg); + if (ret_val) +- goto out; ++ return ret_val; + ret_val = e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg); + if (ret_val) +- goto out; ++ return ret_val; + + /* Two bits in the Auto Negotiation Advertisement Register + * (Address 4) and two bits in the Auto Negotiation Base +@@ -1155,7 +1136,7 @@ s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) + ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); + if (ret_val) { + hw_dbg(hw, "Error getting link speed and duplex\n"); +- goto out; ++ return ret_val; + } + + if (duplex == HALF_DUPLEX) +@@ -1167,12 +1148,11 @@ s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) + ret_val = e1000_force_mac_fc(hw); + if (ret_val) { + hw_dbg(hw, "Error forcing flow control settings\n"); +- goto out; ++ return ret_val; + } + } + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -1208,7 +1188,7 @@ s32 e1000_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *dupl + hw_dbg(hw, "Half Duplex\n"); + } + +- return E1000_SUCCESS; ++ return 0; + } + + /** +@@ -1225,7 +1205,7 @@ s32 e1000_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 + *speed = SPEED_1000; + *duplex = FULL_DUPLEX; + +- return E1000_SUCCESS; ++ return 0; + } + + /** +@@ -1237,7 +1217,6 @@ s32 e1000_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 + s32 e1000_get_hw_semaphore(struct e1000_hw *hw) + { + u32 swsm; +- s32 ret_val = E1000_SUCCESS; + s32 timeout = hw->nvm.word_size + 1; + s32 i = 0; + +@@ -1253,8 +1232,7 @@ s32 e1000_get_hw_semaphore(struct e1000_hw *hw) + + if (i == timeout) { + hw_dbg(hw, "Driver can't access device - SMBI bit is set.\n"); +- ret_val = -E1000_ERR_NVM; +- goto out; ++ return -E1000_ERR_NVM; + } + + /* Get the FW semaphore. */ +@@ -1273,12 +1251,10 @@ s32 e1000_get_hw_semaphore(struct e1000_hw *hw) + /* Release semaphores */ + e1000_put_hw_semaphore(hw); + hw_dbg(hw, "Driver can't access the NVM\n"); +- ret_val = -E1000_ERR_NVM; +- goto out; ++ return -E1000_ERR_NVM; + } + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -1292,9 +1268,7 @@ void e1000_put_hw_semaphore(struct e1000_hw *hw) + u32 swsm; + + swsm = er32(SWSM); +- + swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); +- + ew32(SWSM, swsm); + } + +@@ -1307,7 +1281,6 @@ void e1000_put_hw_semaphore(struct e1000_hw *hw) + s32 e1000_get_auto_rd_done(struct e1000_hw *hw) + { + s32 i = 0; +- s32 ret_val = E1000_SUCCESS; + + while (i < AUTO_READ_DONE_TIMEOUT) { + if (er32(EECD) & E1000_EECD_AUTO_RD) +@@ -1318,12 +1291,10 @@ s32 e1000_get_auto_rd_done(struct e1000_hw *hw) + + if (i == AUTO_READ_DONE_TIMEOUT) { + hw_dbg(hw, "Auto read by HW from NVM has not completed.\n"); +- ret_val = -E1000_ERR_RESET; +- goto out; ++ return -E1000_ERR_RESET; + } + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -1341,14 +1312,13 @@ s32 e1000_valid_led_default(struct e1000_hw *hw, u16 *data) + ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); + if (ret_val) { + hw_dbg(hw, "NVM Read Error\n"); +- goto out; ++ return ret_val; + } + + if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) + *data = ID_LED_DEFAULT; + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -1368,7 +1338,7 @@ s32 e1000_id_led_init(struct e1000_hw *hw) + + ret_val = hw->nvm.ops.valid_led_default(hw, &data); + if (ret_val) +- goto out; ++ return ret_val; + + mac->ledctl_default = er32(LEDCTL); + mac->ledctl_mode1 = mac->ledctl_default; +@@ -1412,8 +1382,7 @@ s32 e1000_id_led_init(struct e1000_hw *hw) + } + } + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -1426,8 +1395,7 @@ out: + s32 e1000_cleanup_led_generic(struct e1000_hw *hw) + { + ew32(LEDCTL, hw->mac.ledctl_default); +- +- return E1000_SUCCESS; ++ return 0; + } + + /** +@@ -1458,7 +1426,7 @@ s32 e1000_blink_led(struct e1000_hw *hw) + + ew32(LEDCTL, ledctl_blink); + +- return E1000_SUCCESS; ++ return 0; + } + + /** +@@ -1485,7 +1453,7 @@ s32 e1000_led_on_generic(struct e1000_hw *hw) + break; + } + +- return E1000_SUCCESS; ++ return 0; + } + + /** +@@ -1512,7 +1480,7 @@ s32 e1000_led_off_generic(struct e1000_hw *hw) + break; + } + +- return E1000_SUCCESS; ++ return 0; + } + + /** +@@ -1538,7 +1506,7 @@ void e1000_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop) + * e1000_disable_pcie_master - Disables PCI-express master access + * @hw: pointer to the HW structure + * +- * Returns 0 (E1000_SUCCESS) if successful, else returns -10 ++ * Returns 0 if successful, else returns -10 + * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not casued + * the master requests to be disabled. + * +@@ -1549,7 +1517,6 @@ s32 e1000_disable_pcie_master(struct e1000_hw *hw) + { + u32 ctrl; + s32 timeout = MASTER_DISABLE_TIMEOUT; +- s32 ret_val = E1000_SUCCESS; + + ctrl = er32(CTRL); + ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; +@@ -1565,12 +1532,10 @@ s32 e1000_disable_pcie_master(struct e1000_hw *hw) + + if (!timeout) { + hw_dbg(hw, "Master requests are pending.\n"); +- ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; +- goto out; ++ return -E1000_ERR_MASTER_REQUESTS_PENDING; + } + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -1748,7 +1713,6 @@ s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) + { + u32 attempts = 100000; + u32 i, reg = 0; +- s32 ret_val = -E1000_ERR_NVM; + + for (i = 0; i < attempts; i++) { + if (ee_reg == E1000_NVM_POLL_READ) +@@ -1756,15 +1720,13 @@ s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) + else + reg = er32(EEWR); + +- if (reg & E1000_NVM_RW_REG_DONE) { +- ret_val = E1000_SUCCESS; +- break; +- } ++ if (reg & E1000_NVM_RW_REG_DONE) ++ return 0; + + udelay(5); + } + +- return ret_val; ++ return -E1000_ERR_NVM; + } + + /** +@@ -1779,7 +1741,6 @@ s32 e1000_acquire_nvm(struct e1000_hw *hw) + { + u32 eecd = er32(EECD); + s32 timeout = E1000_NVM_GRANT_ATTEMPTS; +- s32 ret_val = E1000_SUCCESS; + + ew32(EECD, eecd | E1000_EECD_REQ); + eecd = er32(EECD); +@@ -1796,10 +1757,10 @@ s32 e1000_acquire_nvm(struct e1000_hw *hw) + eecd &= ~E1000_EECD_REQ; + ew32(EECD, eecd); + hw_dbg(hw, "Could not acquire NVM grant\n"); +- ret_val = -E1000_ERR_NVM; ++ return -E1000_ERR_NVM; + } + +- return ret_val; ++ return 0; + } + + /** +@@ -1871,7 +1832,6 @@ static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) + { + struct e1000_nvm_info *nvm = &hw->nvm; + u32 eecd = er32(EECD); +- s32 ret_val = E1000_SUCCESS; + u16 timeout = 0; + u8 spi_stat_reg; + +@@ -1900,13 +1860,11 @@ static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) + + if (!timeout) { + hw_dbg(hw, "SPI NVM Status error\n"); +- ret_val = -E1000_ERR_NVM; +- goto out; ++ return -E1000_ERR_NVM; + } + } + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -1931,17 +1889,18 @@ s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) + if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || + (words == 0)) { + hw_dbg(hw, "nvm parameter(s) out of bounds\n"); +- ret_val = -E1000_ERR_NVM; +- goto out; ++ return -E1000_ERR_NVM; + } + + ret_val = nvm->ops.acquire_nvm(hw); + if (ret_val) +- goto out; ++ return ret_val; + + ret_val = e1000_ready_nvm_eeprom(hw); +- if (ret_val) +- goto release; ++ if (ret_val) { ++ nvm->ops.release_nvm(hw); ++ return ret_val; ++ } + + e1000_standby_nvm(hw); + +@@ -1960,11 +1919,8 @@ s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) + data[i] = (word_in >> 8) | (word_in << 8); + } + +-release: + nvm->ops.release_nvm(hw); +- +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -1980,15 +1936,14 @@ s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) + { + struct e1000_nvm_info *nvm = &hw->nvm; + u32 i, eerd = 0; +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val; + + /* A check for invalid values: offset too large, too many words, + * and not enough words. */ + if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || + (words == 0)) { + hw_dbg(hw, "nvm parameter(s) out of bounds\n"); +- ret_val = -E1000_ERR_NVM; +- goto out; ++ return -E1000_ERR_NVM; + } + + for (i = 0; i < words; i++) { +@@ -2004,7 +1959,6 @@ s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) + E1000_NVM_RW_REG_DATA); + } + +-out: + return ret_val; + } + +@@ -2031,13 +1985,12 @@ s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) + if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || + (words == 0)) { + hw_dbg(hw, "nvm parameter(s) out of bounds\n"); +- ret_val = -E1000_ERR_NVM; +- goto out; ++ return -E1000_ERR_NVM; + } + + ret_val = nvm->ops.acquire_nvm(hw); + if (ret_val) +- goto out; ++ return ret_val; + + msleep(10); + +@@ -2045,8 +1998,10 @@ s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) + u8 write_opcode = NVM_WRITE_OPCODE_SPI; + + ret_val = e1000_ready_nvm_eeprom(hw); +- if (ret_val) +- goto release; ++ if (ret_val) { ++ nvm->ops.release_nvm(hw); ++ return ret_val; ++ } + + e1000_standby_nvm(hw); + +@@ -2081,11 +2036,7 @@ s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) + } + + msleep(10); +-release: +- nvm->ops.release_nvm(hw); +- +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -2098,7 +2049,7 @@ out: + **/ + s32 e1000_read_mac_addr(struct e1000_hw *hw) + { +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val; + u16 offset, nvm_data, i; + + for (i = 0; i < ETH_ALEN; i += 2) { +@@ -2106,7 +2057,7 @@ s32 e1000_read_mac_addr(struct e1000_hw *hw) + ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data); + if (ret_val) { + hw_dbg(hw, "NVM Read Error\n"); +- goto out; ++ return ret_val; + } + hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); + hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8); +@@ -2119,8 +2070,7 @@ s32 e1000_read_mac_addr(struct e1000_hw *hw) + for (i = 0; i < ETH_ALEN; i++) + hw->mac.addr[i] = hw->mac.perm_addr[i]; + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -2132,7 +2082,7 @@ out: + **/ + s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw) + { +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val; + u16 checksum = 0; + u16 i, nvm_data; + +@@ -2140,19 +2090,17 @@ s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw) + ret_val = e1000_read_nvm(hw, i, 1, &nvm_data); + if (ret_val) { + hw_dbg(hw, "NVM Read Error\n"); +- goto out; ++ return ret_val; + } + checksum += nvm_data; + } + + if (checksum != (u16) NVM_SUM) { + hw_dbg(hw, "NVM Checksum Invalid\n"); +- ret_val = -E1000_ERR_NVM; +- goto out; ++ return -E1000_ERR_NVM; + } + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -2165,7 +2113,7 @@ out: + **/ + s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw) + { +- s32 ret_val; ++ s32 ret_val; + u16 checksum = 0; + u16 i, nvm_data; + +@@ -2173,17 +2121,15 @@ s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw) + ret_val = e1000_read_nvm(hw, i, 1, &nvm_data); + if (ret_val) { + hw_dbg(hw, "NVM Read Error while updating checksum.\n"); +- goto out; ++ return ret_val; + } + checksum += nvm_data; + } + checksum = (u16) NVM_SUM - checksum; + ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum); +- if (ret_val) { ++ if (ret_val) + hw_dbg(hw, "NVM Write Error while updating checksum.\n"); +- } + +-out: + return ret_val; + } + +@@ -2240,15 +2186,13 @@ static u8 e1000_calculate_checksum(u8 *buffer, u32 length) + static s32 e1000_mng_enable_host_if(struct e1000_hw *hw) + { + u32 hicr; +- s32 ret_val = E1000_SUCCESS; +- u8 i; ++ u8 i; + + /* Check that the host interface is enabled. */ + hicr = er32(HICR); + if ((hicr & E1000_HICR_EN) == 0) { + hw_dbg(hw, "E1000_HOST_EN bit disabled.\n"); +- ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND; +- goto out; ++ return -E1000_ERR_HOST_INTERFACE_COMMAND; + } + /* check the previous command is completed */ + for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { +@@ -2260,12 +2204,10 @@ static s32 e1000_mng_enable_host_if(struct e1000_hw *hw) + + if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { + hw_dbg(hw, "Previous command timeout failed .\n"); +- ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND; +- goto out; ++ return -E1000_ERR_HOST_INTERFACE_COMMAND; + } + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -2296,21 +2238,20 @@ bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) + u32 offset; + s32 ret_val, hdr_csum, csum; + u8 i, len; +- bool tx_filter = 1; + + /* No manageability, no filtering */ + if (!e1000_check_mng_mode(hw)) { +- tx_filter = 0; +- goto out; ++ hw->mac.tx_pkt_filtering = 0; ++ return 0; + } + + /* If we can't read from the host interface for whatever + * reason, disable filtering. + */ + ret_val = e1000_mng_enable_host_if(hw); +- if (ret_val != E1000_SUCCESS) { +- tx_filter = 0; +- goto out; ++ if (ret_val != 0) { ++ hw->mac.tx_pkt_filtering = 0; ++ return ret_val; + } + + /* Read in the header. Length and offset are in dwords. */ +@@ -2326,18 +2267,19 @@ bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) + * the cookie area isn't considered valid, in which case we + * take the safe route of assuming Tx filtering is enabled. + */ +- if (hdr_csum != csum) +- goto out; +- if (hdr->signature != E1000_IAMT_SIGNATURE) +- goto out; ++ if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) { ++ hw->mac.tx_pkt_filtering = 1; ++ return 1; ++ } + + /* Cookie area is valid, make the final check for filtering. */ +- if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) +- tx_filter = 0; ++ if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) { ++ hw->mac.tx_pkt_filtering = 0; ++ return 0; ++ } + +-out: +- hw->mac.tx_pkt_filtering = tx_filter; +- return tx_filter; ++ hw->mac.tx_pkt_filtering = 1; ++ return 1; + } + + /** +@@ -2364,7 +2306,7 @@ s32 e1000_mng_write_cmd_header(struct e1000_hw *hw, + e1e_flush(); + } + +- return E1000_SUCCESS; ++ return 0; + } + + /** +@@ -2385,15 +2327,12 @@ static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, + u8 *tmp; + u8 *bufptr = buffer; + u32 data = 0; +- s32 ret_val = E1000_SUCCESS; + u16 remaining, i, j, prev_bytes; + + /* sum = only sum of the data and it is not checksum */ + +- if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) { +- ret_val = -E1000_ERR_PARAM; +- goto out; +- } ++ if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) ++ return -E1000_ERR_PARAM; + + tmp = (u8 *)&data; + prev_bytes = offset & 0x3; +@@ -2438,8 +2377,7 @@ static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, + E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data); + } + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -2465,25 +2403,24 @@ s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length) + /* Enable the host interface */ + ret_val = e1000_mng_enable_host_if(hw); + if (ret_val) +- goto out; ++ return ret_val; + + /* Populate the host interface with the contents of "buffer". */ + ret_val = e1000_mng_host_if_write(hw, buffer, length, + sizeof(hdr), &(hdr.checksum)); + if (ret_val) +- goto out; ++ return ret_val; + + /* Write the manageability command header */ + ret_val = e1000_mng_write_cmd_header(hw, &hdr); + if (ret_val) +- goto out; ++ return ret_val; + + /* Tell the ARC a new command is pending. */ + hicr = er32(HICR); + ew32(HICR, hicr | E1000_HICR_C); + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -2502,7 +2439,7 @@ bool e1000_enable_mng_pass_thru(struct e1000_hw *hw) + + if (!(manc & E1000_MANC_RCV_TCO_EN) || + !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) +- goto out; ++ return ret_val; + + if (hw->mac.arc_subsystem_valid) { + fwsm = er32(FWSM); +@@ -2512,17 +2449,16 @@ bool e1000_enable_mng_pass_thru(struct e1000_hw *hw) + ((fwsm & E1000_FWSM_MODE_MASK) == + (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) { + ret_val = 1; +- goto out; ++ return ret_val; + } + } else { + if ((manc & E1000_MANC_SMBUS_EN) && + !(manc & E1000_MANC_ASF_EN)) { + ret_val = 1; +- goto out; ++ return ret_val; + } + } + +-out: + return ret_val; + } + +diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c +index 2d0e78c..c8d50cc 100644 +--- a/drivers/net/e1000e/netdev.c ++++ b/drivers/net/e1000e/netdev.c +@@ -2584,7 +2584,7 @@ static int e1000_open(struct net_device *netdev) + /* fire a link status change interrupt to start the watchdog */ + ew32(ICS, E1000_ICS_LSC); + +- return E1000_SUCCESS; ++ return 0; + + err_req_irq: + e1000_release_hw_control(adapter); +@@ -3667,7 +3667,7 @@ static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, + default: + return -EOPNOTSUPP; + } +- return E1000_SUCCESS; ++ return 0; + } + + static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) +diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c +index 6fd55e7..d7947b0 100644 +--- a/drivers/net/e1000e/phy.c ++++ b/drivers/net/e1000e/phy.c +@@ -53,7 +53,7 @@ static const u16 e1000_igp_2_cable_length_table[] = + * @hw: pointer to the HW structure + * + * Read the PHY management control register and check whether a PHY reset +- * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise ++ * is blocked. If a reset is not blocked return 0, otherwise + * return E1000_BLK_PHY_RESET (12). + **/ + s32 e1000_check_reset_block_generic(struct e1000_hw *hw) +@@ -63,7 +63,7 @@ s32 e1000_check_reset_block_generic(struct e1000_hw *hw) + manc = er32(MANC); + + return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? +- E1000_BLK_PHY_RESET : E1000_SUCCESS; ++ E1000_BLK_PHY_RESET : 0; + } + + /** +@@ -76,24 +76,23 @@ s32 e1000_check_reset_block_generic(struct e1000_hw *hw) + s32 e1000_get_phy_id(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val; + u16 phy_id; + + ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); + if (ret_val) +- goto out; ++ return ret_val; + + phy->id = (u32)(phy_id << 16); + udelay(20); + ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); + if (ret_val) +- goto out; ++ return ret_val; + + phy->id |= (u32)(phy_id & PHY_REVISION_MASK); + phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -108,12 +107,9 @@ s32 e1000_phy_reset_dsp(struct e1000_hw *hw) + + ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); + if (ret_val) +- goto out; ++ return ret_val; + +- ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0); +- +-out: +- return ret_val; ++ return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0); + } + + /** +@@ -129,12 +125,10 @@ static s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) + { + struct e1000_phy_info *phy = &hw->phy; + u32 i, mdic = 0; +- s32 ret_val = E1000_SUCCESS; + + if (offset > MAX_PHY_REG_ADDRESS) { + hw_dbg(hw, "PHY Address %d is out of range\n", offset); +- ret_val = -E1000_ERR_PARAM; +- goto out; ++ return -E1000_ERR_PARAM; + } + + /* Set up Op-code, Phy Address, and register offset in the MDI +@@ -156,18 +150,15 @@ static s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) + } + if (!(mdic & E1000_MDIC_READY)) { + hw_dbg(hw, "MDI Read did not complete\n"); +- ret_val = -E1000_ERR_PHY; +- goto out; ++ return -E1000_ERR_PHY; + } + if (mdic & E1000_MDIC_ERROR) { + hw_dbg(hw, "MDI Error\n"); +- ret_val = -E1000_ERR_PHY; +- goto out; ++ return -E1000_ERR_PHY; + } + *data = (u16) mdic; + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -182,12 +173,10 @@ static s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) + { + struct e1000_phy_info *phy = &hw->phy; + u32 i, mdic = 0; +- s32 ret_val = E1000_SUCCESS; + + if (offset > MAX_PHY_REG_ADDRESS) { + hw_dbg(hw, "PHY Address %d is out of range\n", offset); +- ret_val = -E1000_ERR_PARAM; +- goto out; ++ return -E1000_ERR_PARAM; + } + + /* Set up Op-code, Phy Address, and register offset in the MDI +@@ -210,12 +199,10 @@ static s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) + } + if (!(mdic & E1000_MDIC_READY)) { + hw_dbg(hw, "MDI Write did not complete\n"); +- ret_val = -E1000_ERR_PHY; +- goto out; ++ return -E1000_ERR_PHY; + } + +-out: +- return ret_val; ++ return 0; + } + + /** +@@ -234,7 +221,7 @@ s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) + + ret_val = hw->phy.ops.acquire_phy(hw); + if (ret_val) +- goto out; ++ return ret_val; + + ret_val = e1000_read_phy_reg_mdic(hw, + MAX_PHY_REG_ADDRESS & offset, +@@ -242,7 +229,6 @@ s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) + + hw->phy.ops.release_phy(hw); + +-out: + return ret_val; + } + +@@ -261,7 +247,7 @@ s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) + + ret_val = hw->phy.ops.acquire_phy(hw); + if (ret_val) +- goto out; ++ return ret_val; + + ret_val = e1000_write_phy_reg_mdic(hw, + MAX_PHY_REG_ADDRESS & offset, +@@ -269,7 +255,6 @@ s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) + + hw->phy.ops.release_phy(hw); + +-out: + return ret_val; + } + +@@ -289,7 +274,7 @@ s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) + + ret_val = hw->phy.ops.acquire_phy(hw); + if (ret_val) +- goto out; ++ return ret_val; + + if (offset > MAX_PHY_MULTI_PAGE_REG) { + ret_val = e1000_write_phy_reg_mdic(hw, +@@ -297,7 +282,7 @@ s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) + (u16)offset); + if (ret_val) { + hw->phy.ops.release_phy(hw); +- goto out; ++ return ret_val; + } + } + +@@ -307,7 +292,6 @@ s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) + + hw->phy.ops.release_phy(hw); + +-out: + return ret_val; + } + +@@ -326,7 +310,7 @@ s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) + + ret_val = hw->phy.ops.acquire_phy(hw); + if (ret_val) +- goto out; ++ return ret_val; + + if (offset > MAX_PHY_MULTI_PAGE_REG) { + ret_val = e1000_write_phy_reg_mdic(hw, +@@ -334,7 +318,7 @@ s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) + (u16)offset); + if (ret_val) { + hw->phy.ops.release_phy(hw); +- goto out; ++ return ret_val; + } + } + +@@ -344,7 +328,6 @@ s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) + + hw->phy.ops.release_phy(hw); + +-out: + return ret_val; + } + +@@ -365,7 +348,7 @@ s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) + + ret_val = hw->phy.ops.acquire_phy(hw); + if (ret_val) +- goto out; ++ return ret_val; + + kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & + E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; +@@ -378,7 +361,6 @@ s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) + + hw->phy.ops.release_phy(hw); + +-out: + return ret_val; + } + +@@ -399,7 +381,7 @@ s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) + + ret_val = hw->phy.ops.acquire_phy(hw); + if (ret_val) +- goto out; ++ return ret_val; + + kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & + E1000_KMRNCTRLSTA_OFFSET) | data; +@@ -408,7 +390,6 @@ s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) + udelay(2); + hw->phy.ops.release_phy(hw); + +-out: + return ret_val; + } + +@@ -428,7 +409,7 @@ s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) + /* Enable CRS on TX. This must be set for half-duplex operation. */ + ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); + if (ret_val) +- goto out; ++ return ret_val; + + phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; + +@@ -469,7 +450,7 @@ s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) + + ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); + if (ret_val) +- goto out; ++ return ret_val; + + if (phy->revision < 4) { + /* Force TX_CLK in the Extended PHY Specific Control Register +@@ -477,7 +458,7 @@ s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) + */ + ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); + if (ret_val) +- goto out; ++ return ret_val; + + phy_data |= M88E1000_EPSCR_TX_CLK_25; + +@@ -495,17 +476,14 @@ s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) + } + ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); + if (ret_val) +- goto out; ++ return ret_val; + } + + /* Commit the changes. */ + ret_val = e1000_commit_phy(hw); +- if (ret_val) { ++ if (ret_val) + hw_dbg(hw, "Error committing the PHY changes\n"); +- goto out; +- } + +-out: + return ret_val; + } + +@@ -525,7 +503,7 @@ s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) + ret_val = e1000_phy_hw_reset(hw); + if (ret_val) { + hw_dbg(hw, "Error resetting the PHY.\n"); +- goto out; ++ return ret_val; + } + + /* Wait 15ms for MAC to configure PHY from NVM settings. */ +@@ -535,12 +513,12 @@ s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) + ret_val = e1000_set_d0_lplu_state(hw, 0); + if (ret_val) { + hw_dbg(hw, "Error Disabling LPLU D0\n"); +- goto out; ++ return ret_val; + } + /* Configure mdi-mdix settings */ + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data); + if (ret_val) +- goto out; ++ return ret_val; + + data &= ~IGP01E1000_PSCR_AUTO_MDIX; + +@@ -558,7 +536,7 @@ s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) + } + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data); + if (ret_val) +- goto out; ++ return ret_val; + + /* set auto-master slave resolution settings */ + if (hw->mac.autoneg) { +@@ -570,28 +548,28 @@ s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, + &data); + if (ret_val) +- goto out; ++ return ret_val; + + data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, + data); + if (ret_val) +- goto out; ++ return ret_val; + + /* Set auto Master/Slave resolution process */ + ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data); + if (ret_val) +- goto out; ++ return ret_val; + + data &= ~CR_1000T_MS_ENABLE; + ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data); + if (ret_val) +- goto out; ++ return ret_val; + } + + ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data); + if (ret_val) +- goto out; ++ return ret_val; + + /* load defaults for future use */ + phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? +@@ -614,11 +592,8 @@ s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) + break; + } + ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data); +- if (ret_val) +- goto out; + } + +-out: + return ret_val; + } + +@@ -643,13 +618,13 @@ static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) + /* Read the MII Auto-Neg Advertisement Register (Address 4). */ + ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); + if (ret_val) +- goto out; ++ return ret_val; + + if (phy->autoneg_mask & ADVERTISE_1000_FULL) { + /* Read the MII 1000Base-T Control Register (Address 9). */ + ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); + if (ret_val) +- goto out; ++ return ret_val; + } + + /* Need to parse both autoneg_advertised and fc and set up +@@ -757,22 +732,19 @@ static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) + default: + hw_dbg(hw, "Flow control param set incorrectly\n"); + ret_val = -E1000_ERR_CONFIG; +- goto out; ++ return ret_val; + } + + ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); + if (ret_val) +- goto out; ++ return ret_val; + + hw_dbg(hw, "Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); + + if (phy->autoneg_mask & ADVERTISE_1000_FULL) { + ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); +- if (ret_val) +- goto out; + } + +-out: + return ret_val; + } + +@@ -806,7 +778,7 @@ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) + ret_val = e1000_phy_setup_autoneg(hw); + if (ret_val) { + hw_dbg(hw, "Error Setting up Auto-Negotiation\n"); +- goto out; ++ return ret_val; + } + hw_dbg(hw, "Restarting Auto-Neg\n"); + +@@ -815,12 +787,12 @@ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) + */ + ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl); + if (ret_val) +- goto out; ++ return ret_val; + + phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); + ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl); + if (ret_val) +- goto out; ++ return ret_val; + + /* Does the user want to wait for Auto-Neg to complete here, or + * check at a later time (for example, callback routine). +@@ -830,13 +802,12 @@ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) + if (ret_val) { + hw_dbg(hw, "Error while waiting for " + "autoneg to complete\n"); +- goto out; ++ return ret_val; + } + } + + hw->mac.get_link_status = 1; + +-out: + return ret_val; + } + +@@ -859,7 +830,7 @@ s32 e1000_setup_copper_link(struct e1000_hw *hw) + * autonegotiation. */ + ret_val = e1000_copper_link_autoneg(hw); + if (ret_val) +- goto out; ++ return ret_val; + } else { + /* PHY will be set to 10H, 10F, 100H or 100F + * depending on user settings. */ +@@ -867,7 +838,7 @@ s32 e1000_setup_copper_link(struct e1000_hw *hw) + ret_val = e1000_phy_force_speed_duplex(hw); + if (ret_val) { + hw_dbg(hw, "Error Forcing Speed and Duplex\n"); +- goto out; ++ return ret_val; + } + } + +@@ -879,7 +850,7 @@ s32 e1000_setup_copper_link(struct e1000_hw *hw) + 10, + &link); + if (ret_val) +- goto out; ++ return ret_val; + + if (link) { + hw_dbg(hw, "Valid link established!!!\n"); +@@ -889,7 +860,6 @@ s32 e1000_setup_copper_link(struct e1000_hw *hw) + hw_dbg(hw, "Unable to establish link!!!\n"); + } + +-out: + return ret_val; + } + +@@ -910,27 +880,27 @@ s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) + + ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); + if (ret_val) +- goto out; ++ return ret_val; + + e1000_phy_force_speed_duplex_setup(hw, &phy_data); + + ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); + if (ret_val) +- goto out; ++ return ret_val; + + /* Clear Auto-Crossover to force MDI manually. IGP requires MDI + * forced whenever speed and duplex are forced. + */ + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); + if (ret_val) +- goto out; ++ return ret_val; + + phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; + phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; + + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); + if (ret_val) +- goto out; ++ return ret_val; + + hw_dbg(hw, "IGP PSCR: %X\n", phy_data); + +@@ -944,7 +914,7 @@ s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) + 100000, + &link); + if (ret_val) +- goto out; ++ return ret_val; + + if (!link) + hw_dbg(hw, "Link taking longer than expected.\n"); +@@ -955,10 +925,9 @@ s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) + 100000, + &link); + if (ret_val) +- goto out; ++ return ret_val; + } + +-out: + return ret_val; + } + +@@ -984,18 +953,18 @@ s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) + */ + ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); + if (ret_val) +- goto out; ++ return ret_val; + + phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; + ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); + if (ret_val) +- goto out; ++ return ret_val; + + hw_dbg(hw, "M88E1000 PSCR: %X\n", phy_data); + + ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); + if (ret_val) +- goto out; ++ return ret_val; + + e1000_phy_force_speed_duplex_setup(hw, &phy_data); + +@@ -1004,7 +973,7 @@ s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) + + ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); + if (ret_val) +- goto out; ++ return ret_val; + + udelay(1); + +@@ -1014,7 +983,7 @@ s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) + ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, + 100000, &link); + if (ret_val) +- goto out; ++ return ret_val; + + if (!link) { + /* We didn't get link. +@@ -1022,22 +991,22 @@ s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) + */ + ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT, 0x001d); + if (ret_val) +- goto out; ++ return ret_val; + ret_val = e1000_phy_reset_dsp(hw); + if (ret_val) +- goto out; ++ return ret_val; + } + + /* Try once more */ + ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, + 100000, &link); + if (ret_val) +- goto out; ++ return ret_val; + } + + ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); + if (ret_val) +- goto out; ++ return ret_val; + + /* Resetting the phy means we need to re-force TX_CLK in the + * Extended PHY Specific Control Register to 25MHz clock from +@@ -1046,19 +1015,18 @@ s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) + phy_data |= M88E1000_EPSCR_TX_CLK_25; + ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); + if (ret_val) +- goto out; ++ return ret_val; + + /* In addition, we must re-enable CRS on Tx for both half and full + * duplex. + */ + ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); + if (ret_val) +- goto out; ++ return ret_val; + + phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; + ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); + +-out: + return ret_val; + } + +@@ -1144,7 +1112,7 @@ s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) + + ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); + if (ret_val) +- goto out; ++ return ret_val; + + if (!active) { + data &= ~IGP02E1000_PM_D3_LPLU; +@@ -1152,7 +1120,7 @@ s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) + IGP02E1000_PHY_POWER_MGMT, + data); + if (ret_val) +- goto out; ++ return ret_val; + /* LPLU and SmartSpeed are mutually exclusive. LPLU is used + * during Dx states where the power conservation is most + * important. During driver activity we should enable +@@ -1161,24 +1129,24 @@ s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, + &data); + if (ret_val) +- goto out; ++ return ret_val; + + data |= IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, + data); + if (ret_val) +- goto out; ++ return ret_val; + } else if (phy->smart_speed == e1000_smart_speed_off) { + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, + &data); + if (ret_val) +- goto out; ++ return ret_val; + + data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, + data); + if (ret_val) +- goto out; ++ return ret_val; + } + } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || + (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || +@@ -1186,18 +1154,17 @@ s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) + data |= IGP02E1000_PM_D3_LPLU; + ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); + if (ret_val) +- goto out; ++ return ret_val; + + /* When LPLU is enabled, we should disable SmartSpeed */ + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); + if (ret_val) +- goto out; ++ return ret_val; + + data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); + } + +-out: + return ret_val; + } + +@@ -1229,8 +1196,7 @@ s32 e1000_check_downshift(struct e1000_hw *hw) + default: + /* speed downshift not supported */ + phy->speed_downgraded = 0; +- ret_val = E1000_SUCCESS; +- goto out; ++ return 0; + } + + ret_val = e1e_rphy(hw, offset, &phy_data); +@@ -1238,7 +1204,6 @@ s32 e1000_check_downshift(struct e1000_hw *hw) + if (!ret_val) + phy->speed_downgraded = (phy_data & mask); + +-out: + return ret_val; + } + +@@ -1275,7 +1240,7 @@ static s32 e1000_check_polarity_m88(struct e1000_hw *hw) + * Polarity is determined based on the PHY port status register, and the + * current speed (since there is no polarity at 100Mbps). + **/ +-static s32 e1000_check_polarity_igp(struct e1000_hw *hw) ++static s32 e1000_check_polarity_igp(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; +@@ -1285,7 +1250,7 @@ static s32 e1000_check_polarity_igp(struct e1000_hw *hw) + * our connection. */ + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); + if (ret_val) +- goto out; ++ return ret_val; + + if ((data & IGP01E1000_PSSR_SPEED_MASK) == + IGP01E1000_PSSR_SPEED_1000MBPS) { +@@ -1306,7 +1271,6 @@ static s32 e1000_check_polarity_igp(struct e1000_hw *hw) + ? e1000_rev_polarity_reversed + : e1000_rev_polarity_normal; + +-out: + return ret_val; + } + +@@ -1319,7 +1283,7 @@ out: + **/ + s32 e1000_wait_autoneg(struct e1000_hw *hw) + { +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val = 0; + u16 i, phy_status; + + /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ +@@ -1353,7 +1317,7 @@ s32 e1000_wait_autoneg(struct e1000_hw *hw) + s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, + u32 usec_interval, bool *success) + { +- s32 ret_val = E1000_SUCCESS; ++ s32 ret_val; + u16 i, phy_status; + + for (i = 0; i < iterations; i++) { +@@ -1403,7 +1367,7 @@ s32 e1000_get_cable_length_m88(struct e1000_hw *hw) + + ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); + if (ret_val) +- goto out; ++ return ret_val; + + index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> + M88E1000_PSSR_CABLE_LENGTH_SHIFT; +@@ -1412,7 +1376,6 @@ s32 e1000_get_cable_length_m88(struct e1000_hw *hw) + + phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; + +-out: + return ret_val; + } + +@@ -1444,7 +1407,7 @@ s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw) + for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { + ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data); + if (ret_val) +- goto out; ++ return ret_val; + + /* Getting bits 15:9, which represent the combination of + * course and fine gain values. The result is a number +@@ -1455,10 +1418,8 @@ s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw) + + /* Array index bound check. */ + if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || +- (cur_agc_index == 0)) { +- ret_val = -E1000_ERR_PHY; +- goto out; +- } ++ (cur_agc_index == 0)) ++ return -E1000_ERR_PHY; + + /* Remove min & max AGC values from calculation. */ + if (e1000_igp_2_cable_length_table[min_agc_index] > +@@ -1482,7 +1443,6 @@ s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw) + + phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; + +-out: + return ret_val; + } + +@@ -1505,45 +1465,43 @@ s32 e1000_get_phy_info_m88(struct e1000_hw *hw) + + if (hw->media_type != e1000_media_type_copper) { + hw_dbg(hw, "Phy info is only valid for copper media\n"); +- ret_val = -E1000_ERR_CONFIG; +- goto out; ++ return -E1000_ERR_CONFIG; + } + + ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); + if (ret_val) +- goto out; ++ return ret_val; + + if (!link) { + hw_dbg(hw, "Phy info is only valid if link is up\n"); +- ret_val = -E1000_ERR_CONFIG; +- goto out; ++ return -E1000_ERR_CONFIG; + } + + ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); + if (ret_val) +- goto out; ++ return ret_val; + + phy->polarity_correction = (phy_data & + M88E1000_PSCR_POLARITY_REVERSAL); + + ret_val = e1000_check_polarity_m88(hw); + if (ret_val) +- goto out; ++ return ret_val; + + ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); + if (ret_val) +- goto out; ++ return ret_val; + + phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX); + + if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { + ret_val = e1000_get_cable_length(hw); + if (ret_val) +- goto out; ++ return ret_val; + + ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data); + if (ret_val) +- goto out; ++ return ret_val; + + phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) + ? e1000_1000t_rx_status_ok +@@ -1559,7 +1517,6 @@ s32 e1000_get_phy_info_m88(struct e1000_hw *hw) + phy->remote_rx = e1000_1000t_rx_status_undefined; + } + +-out: + return ret_val; + } + +@@ -1581,23 +1538,22 @@ s32 e1000_get_phy_info_igp(struct e1000_hw *hw) + + ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); + if (ret_val) +- goto out; ++ return ret_val; + + if (!link) { + hw_dbg(hw, "Phy info is only valid if link is up\n"); +- ret_val = -E1000_ERR_CONFIG; +- goto out; ++ return -E1000_ERR_CONFIG; + } + + phy->polarity_correction = 1; + + ret_val = e1000_check_polarity_igp(hw); + if (ret_val) +- goto out; ++ return ret_val; + + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); + if (ret_val) +- goto out; ++ return ret_val; + + phy->is_mdix = (data & IGP01E1000_PSSR_MDIX); + +@@ -1605,11 +1561,11 @@ s32 e1000_get_phy_info_igp(struct e1000_hw *hw) + IGP01E1000_PSSR_SPEED_1000MBPS) { + ret_val = e1000_get_cable_length(hw); + if (ret_val) +- goto out; ++ return ret_val; + + ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data); + if (ret_val) +- goto out; ++ return ret_val; + + phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) + ? e1000_1000t_rx_status_ok +@@ -1624,7 +1580,6 @@ s32 e1000_get_phy_info_igp(struct e1000_hw *hw) + phy->remote_rx = e1000_1000t_rx_status_undefined; + } + +-out: + return ret_val; + } + +@@ -1642,16 +1597,15 @@ s32 e1000_phy_sw_reset(struct e1000_hw *hw) + + ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl); + if (ret_val) +- goto out; ++ return ret_val; + + phy_ctrl |= MII_CR_RESET; + ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl); + if (ret_val) +- goto out; ++ return ret_val; + + udelay(1); + +-out: + return ret_val; + } + +@@ -1667,18 +1621,16 @@ out: + s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; +- s32 ret_val; ++ s32 ret_val; + u32 ctrl; + + ret_val = e1000_check_reset_block(hw); +- if (ret_val) { +- ret_val = E1000_SUCCESS; +- goto out; +- } ++ if (ret_val) ++ return 0; + + ret_val = phy->ops.acquire_phy(hw); + if (ret_val) +- goto out; ++ return ret_val; + + ctrl = er32(CTRL); + ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); +@@ -1693,10 +1645,7 @@ s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw) + + phy->ops.release_phy(hw); + +- ret_val = e1000_get_phy_cfg_done(hw); +- +-out: +- return ret_val; ++ return e1000_get_phy_cfg_done(hw); + } + + /** +@@ -1709,8 +1658,7 @@ out: + s32 e1000_get_cfg_done(struct e1000_hw *hw) + { + mdelay(10); +- +- return E1000_SUCCESS; ++ return 0; + } + + /* Internal function pointers */ +@@ -1726,8 +1674,8 @@ static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) + { + if (hw->phy.ops.get_cfg_done) + return hw->phy.ops.get_cfg_done(hw); +- else +- return E1000_SUCCESS; ++ ++ return 0; + } + + /** +@@ -1735,14 +1683,14 @@ static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) + * @hw: pointer to the HW structure + * + * When the silicon family has not implemented a forced speed/duplex +- * function for the PHY, simply return E1000_SUCCESS. ++ * function for the PHY, simply return 0. + **/ + static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) + { + if (hw->phy.ops.force_speed_duplex) + return hw->phy.ops.force_speed_duplex(hw); +- else +- return E1000_SUCCESS; ++ ++ return 0; + } + + /** +@@ -1794,8 +1742,8 @@ s32 e1000_commit_phy(struct e1000_hw *hw) + { + if (hw->phy.ops.commit_phy) + return hw->phy.ops.commit_phy(hw); +- else +- return E1000_SUCCESS; ++ ++ return 0; + } + + /** +@@ -1816,6 +1764,6 @@ s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) + { + if (hw->phy.ops.set_d0_lplu_state) + return hw->phy.ops.set_d0_lplu_state(hw, active); +- else +- return E1000_SUCCESS; ++ ++ return 0; + } diff --git a/trunk/2.6.21/21352_linux-2.6-netdev-e1000e-03.patch b/trunk/2.6.21/21352_linux-2.6-netdev-e1000e-03.patch new file mode 100644 index 0000000..f23306a --- /dev/null +++ b/trunk/2.6.21/21352_linux-2.6-netdev-e1000e-03.patch @@ -0,0 +1,95 @@ +From: Auke Kok <auke-jan.h.kok@intel.com> +Date: Wed, 8 Aug 2007 17:22:11 +0000 (-0700) +Subject: e1000e: Make a few functions static +X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fjgarzik%2Fnetdev-2.6.git;a=commitdiff_plain;h=604694f8c19065ee960887d97716d57107ca9a34 + +e1000e: Make a few functions static + +After moving code around we can reduce namespace usage +by making a few functions static. + +Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> +Signed-off-by: Jeff Garzik <jeff@garzik.org> +--- + +diff --git a/drivers/net/e1000e/e1000.h b/drivers/net/e1000e/e1000.h +index 65c31d3..a1394d6 100644 +--- a/drivers/net/e1000e/e1000.h ++++ b/drivers/net/e1000e/e1000.h +@@ -365,7 +365,6 @@ extern struct e1000_info e1000_ich9_info; + extern struct e1000_info e1000_es2_info; + + extern s32 e1000_commit_phy(struct e1000_hw *hw); +-extern s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active); + + extern bool e1000_enable_mng_pass_thru(struct e1000_hw *hw); + +@@ -438,7 +437,6 @@ extern s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, + u32 usec_interval, bool *success); + extern s32 e1000_phy_reset_dsp(struct e1000_hw *hw); + extern s32 e1000_check_downshift(struct e1000_hw *hw); +-extern s32 e1000_wait_autoneg(struct e1000_hw *hw); + + static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw) + { +diff --git a/drivers/net/e1000e/lib.c b/drivers/net/e1000e/lib.c +index d11b518..3bbe63e 100644 +--- a/drivers/net/e1000e/lib.c ++++ b/drivers/net/e1000e/lib.c +@@ -2289,7 +2289,7 @@ bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) + * + * Writes the command header after does the checksum calculation. + **/ +-s32 e1000_mng_write_cmd_header(struct e1000_hw *hw, ++static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw, + struct e1000_host_mng_command_header *hdr) + { + u16 i, length = sizeof(struct e1000_host_mng_command_header); +diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c +index c8d50cc..dd4eca6 100644 +--- a/drivers/net/e1000e/netdev.c ++++ b/drivers/net/e1000e/netdev.c +@@ -48,7 +48,7 @@ + char e1000_driver_name[] = "e1000e"; + const char e1000_driver_version[] = DRV_VERSION; + +-const struct e1000_info * e1000_info_tbl[] = { ++static const struct e1000_info *e1000_info_tbl[] = { + [board_82571] = &e1000_82571_info, + [board_82572] = &e1000_82572_info, + [board_82573] = &e1000_82573_info, +diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c +index d7947b0..1ccbad7 100644 +--- a/drivers/net/e1000e/phy.c ++++ b/drivers/net/e1000e/phy.c +@@ -28,8 +28,10 @@ + + #include "e1000.h" + +-static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); +-static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); ++static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); ++static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); ++static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active); ++static s32 e1000_wait_autoneg(struct e1000_hw *hw); + + /* Cable length tables */ + static const u16 e1000_m88_cable_length_table[] = +@@ -1281,7 +1283,7 @@ static s32 e1000_check_polarity_igp(struct e1000_hw *hw) + * Waits for auto-negotiation to complete or for the auto-negotiation time + * limit to expire, which ever happens first. + **/ +-s32 e1000_wait_autoneg(struct e1000_hw *hw) ++static s32 e1000_wait_autoneg(struct e1000_hw *hw) + { + s32 ret_val = 0; + u16 i, phy_status; +@@ -1760,7 +1762,7 @@ s32 e1000_commit_phy(struct e1000_hw *hw) + * During driver activity, SmartSpeed should be enabled so performance is + * maintained. This is a function pointer entry point called by drivers. + **/ +-s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) ++static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) + { + if (hw->phy.ops.set_d0_lplu_state) + return hw->phy.ops.set_d0_lplu_state(hw, active); diff --git a/trunk/2.6.21/21353_linux-2.6-netdev-e1000e-04.patch b/trunk/2.6.21/21353_linux-2.6-netdev-e1000e-04.patch new file mode 100644 index 0000000..36f7c6d --- /dev/null +++ b/trunk/2.6.21/21353_linux-2.6-netdev-e1000e-04.patch @@ -0,0 +1,23 @@ +From: Auke Kok <auke-jan.h.kok@intel.com> +Date: Wed, 8 Aug 2007 17:22:21 +0000 (-0700) +Subject: e1000e: remove duplicate shadowing reference to adapter->hw +X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fjgarzik%2Fnetdev-2.6.git;a=commitdiff_plain;h=5b8fe1c4280c9424a5fc03d8e8e13c1b4cde22f0 + +e1000e: remove duplicate shadowing reference to adapter->hw + +Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> +Signed-off-by: Jeff Garzik <jeff@garzik.org> +--- + +diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c +index dd4eca6..741965d 100644 +--- a/drivers/net/e1000e/netdev.c ++++ b/drivers/net/e1000e/netdev.c +@@ -2981,7 +2981,6 @@ static void e1000_watchdog_task(struct work_struct *work) + } else { + /* make sure the receive unit is started */ + if (adapter->flags & FLAG_RX_NEEDS_RESTART) { +- struct e1000_hw *hw = &adapter->hw; + u32 rctl = er32(RCTL); + ew32(RCTL, rctl | + E1000_RCTL_EN); diff --git a/trunk/2.6.21/21354_linux-2.6-netdev-e1000e-05.patch b/trunk/2.6.21/21354_linux-2.6-netdev-e1000e-05.patch new file mode 100644 index 0000000..cde8bad --- /dev/null +++ b/trunk/2.6.21/21354_linux-2.6-netdev-e1000e-05.patch @@ -0,0 +1,146 @@ +From: Auke Kok <auke-jan.h.kok@intel.com> +Date: Fri, 10 Aug 2007 20:00:38 +0000 (-0700) +Subject: e1000e: Fix header includes [v2] +X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fjgarzik%2Fnetdev-2.6.git;a=commitdiff_plain;h=867dbd1bea13a265f10a0685488e486836fb3910 + +e1000e: Fix header includes [v2] + +Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> +Signed-off-by: Jeff Garzik <jeff@garzik.org> +--- + +diff --git a/drivers/net/e1000e/82571.c b/drivers/net/e1000e/82571.c +index ddf2303..0f8f0ac 100644 +--- a/drivers/net/e1000e/82571.c ++++ b/drivers/net/e1000e/82571.c +@@ -37,6 +37,10 @@ + * 82573L Gigabit Ethernet Controller + */ + ++#include <linux/netdevice.h> ++#include <linux/delay.h> ++#include <linux/pci.h> ++ + #include "e1000.h" + + #define ID_LED_RESERVED_F746 0xF746 +diff --git a/drivers/net/e1000e/e1000.h b/drivers/net/e1000e/e1000.h +index a1394d6..de17537 100644 +--- a/drivers/net/e1000e/e1000.h ++++ b/drivers/net/e1000e/e1000.h +@@ -31,10 +31,11 @@ + #ifndef _E1000_H_ + #define _E1000_H_ + ++#include <linux/types.h> ++#include <linux/timer.h> ++#include <linux/workqueue.h> ++#include <linux/io.h> + #include <linux/netdevice.h> +-#include <linux/ethtool.h> +-#include <linux/pci.h> +-#include <asm/io.h> + + #include "hw.h" + +diff --git a/drivers/net/e1000e/es2lan.c b/drivers/net/e1000e/es2lan.c +index 5604c50..8100d03 100644 +--- a/drivers/net/e1000e/es2lan.c ++++ b/drivers/net/e1000e/es2lan.c +@@ -31,6 +31,11 @@ + * 80003ES2LAN Gigabit Ethernet Controller (Serdes) + */ + ++#include <linux/netdevice.h> ++#include <linux/ethtool.h> ++#include <linux/delay.h> ++#include <linux/pci.h> ++ + #include "e1000.h" + + #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00 +diff --git a/drivers/net/e1000e/ethtool.c b/drivers/net/e1000e/ethtool.c +index 6c417ea..a8fa1db 100644 +--- a/drivers/net/e1000e/ethtool.c ++++ b/drivers/net/e1000e/ethtool.c +@@ -29,8 +29,9 @@ + /* ethtool support for e1000 */ + + #include <linux/netdevice.h> +- + #include <linux/ethtool.h> ++#include <linux/pci.h> ++#include <linux/delay.h> + + #include "e1000.h" + +diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h +index 4d562c4..848217a 100644 +--- a/drivers/net/e1000e/hw.h ++++ b/drivers/net/e1000e/hw.h +@@ -29,6 +29,8 @@ + #ifndef _E1000_HW_H_ + #define _E1000_HW_H_ + ++#include <linux/types.h> ++ + struct e1000_hw; + struct e1000_adapter; + +diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c +index 042abd4..85095af 100644 +--- a/drivers/net/e1000e/ich8lan.c ++++ b/drivers/net/e1000e/ich8lan.c +@@ -40,6 +40,11 @@ + * 82566MM Gigabit Network Connection + */ + ++#include <linux/netdevice.h> ++#include <linux/ethtool.h> ++#include <linux/delay.h> ++#include <linux/pci.h> ++ + #include "e1000.h" + + #define ICH_FLASH_GFPREG 0x0000 +diff --git a/drivers/net/e1000e/lib.c b/drivers/net/e1000e/lib.c +index 3bbe63e..c92ea77 100644 +--- a/drivers/net/e1000e/lib.c ++++ b/drivers/net/e1000e/lib.c +@@ -27,6 +27,8 @@ + *******************************************************************************/ + + #include <linux/netdevice.h> ++#include <linux/ethtool.h> ++#include <linux/delay.h> + #include <linux/pci.h> + + #include "e1000.h" +diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c +index 741965d..01a9a4f 100644 +--- a/drivers/net/e1000e/netdev.c ++++ b/drivers/net/e1000e/netdev.c +@@ -29,8 +29,10 @@ + #include <linux/module.h> + #include <linux/types.h> + #include <linux/init.h> ++#include <linux/pci.h> + #include <linux/vmalloc.h> + #include <linux/pagemap.h> ++#include <linux/delay.h> + #include <linux/netdevice.h> + #include <linux/tcp.h> + #include <linux/ipv6.h> +diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c +index 1ccbad7..c9304d8 100644 +--- a/drivers/net/e1000e/phy.c ++++ b/drivers/net/e1000e/phy.c +@@ -26,6 +26,8 @@ + + *******************************************************************************/ + ++#include <linux/delay.h> ++ + #include "e1000.h" + + static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); diff --git a/trunk/2.6.21/21355_linux-2.6-netdev-e1000e-06.patch b/trunk/2.6.21/21355_linux-2.6-netdev-e1000e-06.patch new file mode 100644 index 0000000..e8ae5a8 --- /dev/null +++ b/trunk/2.6.21/21355_linux-2.6-netdev-e1000e-06.patch @@ -0,0 +1,3777 @@ +From: Auke Kok <auke-jan.h.kok@intel.com> +Date: Fri, 10 Aug 2007 20:00:47 +0000 (-0700) +Subject: e1000e: remove namespace collisions with e1000 +X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fjgarzik%2Fnetdev-2.6.git;a=commitdiff_plain;h=9c1a53eb0d1c4d8039a74e6408b39c9c0690d3af + +e1000e: remove namespace collisions with e1000 + +To prevent future collisions we rename all extern's from e1000_ +to e1000e_*. The list of changed symbols was taken from e1000.h +Compile tested with CONFIG_E1000=y and CONFIG_E1000E=y. + +Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> +Signed-off-by: Jeff Garzik <jeff@garzik.org> +--- + +diff --git a/drivers/net/e1000e/82571.c b/drivers/net/e1000e/82571.c +index 0f8f0ac..cf70522 100644 +--- a/drivers/net/e1000e/82571.c ++++ b/drivers/net/e1000e/82571.c +@@ -54,7 +54,6 @@ + static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); + static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); + static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); +-static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); + static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, + u16 words, u16 *data); + static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); +@@ -214,18 +213,18 @@ static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter) + switch (hw->media_type) { + case e1000_media_type_copper: + func->setup_physical_interface = e1000_setup_copper_link_82571; +- func->check_for_link = e1000_check_for_copper_link; +- func->get_link_up_info = e1000_get_speed_and_duplex_copper; ++ func->check_for_link = e1000e_check_for_copper_link; ++ func->get_link_up_info = e1000e_get_speed_and_duplex_copper; + break; + case e1000_media_type_fiber: + func->setup_physical_interface = e1000_setup_fiber_serdes_link_82571; +- func->check_for_link = e1000_check_for_fiber_link; +- func->get_link_up_info = e1000_get_speed_and_duplex_fiber_serdes; ++ func->check_for_link = e1000e_check_for_fiber_link; ++ func->get_link_up_info = e1000e_get_speed_and_duplex_fiber_serdes; + break; + case e1000_media_type_internal_serdes: + func->setup_physical_interface = e1000_setup_fiber_serdes_link_82571; +- func->check_for_link = e1000_check_for_serdes_link; +- func->get_link_up_info = e1000_get_speed_and_duplex_fiber_serdes; ++ func->check_for_link = e1000e_check_for_serdes_link; ++ func->get_link_up_info = e1000e_get_speed_and_duplex_fiber_serdes; + break; + default: + return -E1000_ERR_CONFIG; +@@ -324,7 +323,7 @@ static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) + phy->id = IGP01E1000_I_PHY_ID; + break; + case e1000_82573: +- return e1000_get_phy_id(hw); ++ return e1000e_get_phy_id(hw); + break; + default: + return -E1000_ERR_PHY; +@@ -360,7 +359,7 @@ static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) + + if (i == timeout) { + /* Release semaphores */ +- e1000_put_hw_semaphore(hw); ++ e1000e_put_hw_semaphore(hw); + hw_dbg(hw, "Driver can't access the NVM\n"); + return -E1000_ERR_NVM; + } +@@ -403,7 +402,7 @@ static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) + return ret_val; + + if (hw->mac.type != e1000_82573) +- ret_val = e1000_acquire_nvm(hw); ++ ret_val = e1000e_acquire_nvm(hw); + + if (ret_val) + e1000_put_hw_semaphore_82571(hw); +@@ -419,7 +418,7 @@ static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) + **/ + static void e1000_release_nvm_82571(struct e1000_hw *hw) + { +- e1000_release_nvm(hw); ++ e1000e_release_nvm(hw); + e1000_put_hw_semaphore_82571(hw); + } + +@@ -432,7 +431,7 @@ static void e1000_release_nvm_82571(struct e1000_hw *hw) + * + * For non-82573 silicon, write data to EEPROM at offset using SPI interface. + * +- * If e1000_update_nvm_checksum is not called after this function, the ++ * If e1000e_update_nvm_checksum is not called after this function, the + * EEPROM will most likley contain an invalid checksum. + **/ + static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, +@@ -446,7 +445,7 @@ static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, + break; + case e1000_82571: + case e1000_82572: +- ret_val = e1000_write_nvm_spi(hw, offset, words, data); ++ ret_val = e1000e_write_nvm_spi(hw, offset, words, data); + break; + default: + ret_val = -E1000_ERR_NVM; +@@ -470,7 +469,7 @@ static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) + s32 ret_val; + u16 i; + +- ret_val = e1000_update_nvm_checksum_generic(hw); ++ ret_val = e1000e_update_nvm_checksum_generic(hw); + if (ret_val) + return ret_val; + +@@ -527,7 +526,7 @@ static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) + if (hw->nvm.type == e1000_nvm_flash_hw) + e1000_fix_nvm_checksum_82571(hw); + +- return e1000_validate_nvm_checksum_generic(hw); ++ return e1000e_validate_nvm_checksum_generic(hw); + } + + /** +@@ -541,7 +540,7 @@ static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) + * command has completed before trying to write the next word. After write + * poll for completion. + * +- * If e1000_update_nvm_checksum is not called after this function, the ++ * If e1000e_update_nvm_checksum is not called after this function, the + * EEPROM will most likley contain an invalid checksum. + **/ + static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, +@@ -565,13 +564,13 @@ static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, + ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | + E1000_NVM_RW_REG_START; + +- ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); ++ ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); + if (ret_val) + break; + + ew32(EEWR, eewr); + +- ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); ++ ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); + if (ret_val) + break; + } +@@ -691,7 +690,7 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw) + /* Prevent the PCI-E bus from sticking if there is no TLP connection + * on the last TLP read/write transaction when MAC is reset. + */ +- ret_val = e1000_disable_pcie_master(hw); ++ ret_val = e1000e_disable_pcie_master(hw); + if (ret_val) + hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); + +@@ -737,7 +736,7 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw) + e1e_flush(); + } + +- ret_val = e1000_get_auto_rd_done(hw); ++ ret_val = e1000e_get_auto_rd_done(hw); + if (ret_val) + /* We don't want to continue accessing MAC registers. */ + return ret_val; +@@ -773,7 +772,7 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw) + e1000_initialize_hw_bits_82571(hw); + + /* Initialize identification LED */ +- ret_val = e1000_id_led_init(hw); ++ ret_val = e1000e_id_led_init(hw); + if (ret_val) { + hw_dbg(hw, "Error initializing identification LED\n"); + return ret_val; +@@ -781,16 +780,16 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw) + + /* Disabling VLAN filtering */ + hw_dbg(hw, "Initializing the IEEE VLAN\n"); +- e1000_clear_vfta(hw); ++ e1000e_clear_vfta(hw); + + /* Setup the receive address. */ + /* If, however, a locally administered address was assigned to the + * 82571, we must reserve a RAR for it to work around an issue where + * resetting one port will reload the MAC on the other port. + */ +- if (e1000_get_laa_state_82571(hw)) ++ if (e1000e_get_laa_state_82571(hw)) + rar_count--; +- e1000_init_rx_addrs(hw, rar_count); ++ e1000e_init_rx_addrs(hw, rar_count); + + /* Zero out the Multicast HASH table */ + hw_dbg(hw, "Zeroing the MTA\n"); +@@ -815,7 +814,7 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw) + E1000_TXDCTL_COUNT_DESC; + ew32(TXDCTL1, reg_data); + } else { +- e1000_enable_tx_pkt_filtering(hw); ++ e1000e_enable_tx_pkt_filtering(hw); + reg_data = er32(GCR); + reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; + ew32(GCR, reg_data); +@@ -898,13 +897,13 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) + } + + /** +- * e1000_clear_vfta - Clear VLAN filter table ++ * e1000e_clear_vfta - Clear VLAN filter table + * @hw: pointer to the HW structure + * + * Clears the register array which contains the VLAN filter table by + * setting all the values to 0. + **/ +-void e1000_clear_vfta(struct e1000_hw *hw) ++void e1000e_clear_vfta(struct e1000_hw *hw) + { + u32 offset; + u32 vfta_value = 0; +@@ -956,10 +955,10 @@ static void e1000_mc_addr_list_update_82571(struct e1000_hw *hw, + u32 rar_used_count, + u32 rar_count) + { +- if (e1000_get_laa_state_82571(hw)) ++ if (e1000e_get_laa_state_82571(hw)) + rar_count--; + +- e1000_mc_addr_list_update_generic(hw, mc_addr_list, mc_addr_count, ++ e1000e_mc_addr_list_update_generic(hw, mc_addr_list, mc_addr_count, + rar_used_count, rar_count); + } + +@@ -982,7 +981,7 @@ static s32 e1000_setup_link_82571(struct e1000_hw *hw) + if (hw->mac.type == e1000_82573) + hw->mac.fc = e1000_fc_full; + +- return e1000_setup_link(hw); ++ return e1000e_setup_link(hw); + } + + /** +@@ -1006,10 +1005,10 @@ static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) + + switch (hw->phy.type) { + case e1000_phy_m88: +- ret_val = e1000_copper_link_setup_m88(hw); ++ ret_val = e1000e_copper_link_setup_m88(hw); + break; + case e1000_phy_igp_2: +- ret_val = e1000_copper_link_setup_igp(hw); ++ ret_val = e1000e_copper_link_setup_igp(hw); + /* Setup activity LED */ + led_ctrl = er32(LEDCTL); + led_ctrl &= IGP_ACTIVITY_LED_MASK; +@@ -1024,7 +1023,7 @@ static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) + if (ret_val) + return ret_val; + +- ret_val = e1000_setup_copper_link(hw); ++ ret_val = e1000e_setup_copper_link(hw); + + return ret_val; + } +@@ -1054,7 +1053,7 @@ static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) + break; + } + +- return e1000_setup_fiber_serdes_link(hw); ++ return e1000e_setup_fiber_serdes_link(hw); + } + + /** +@@ -1086,12 +1085,12 @@ static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) + } + + /** +- * e1000_get_laa_state_82571 - Get locally administered address state ++ * e1000e_get_laa_state_82571 - Get locally administered address state + * @hw: pointer to the HW structure + * + * Retrieve and return the current locally administed address state. + **/ +-bool e1000_get_laa_state_82571(struct e1000_hw *hw) ++bool e1000e_get_laa_state_82571(struct e1000_hw *hw) + { + if (hw->mac.type != e1000_82571) + return 0; +@@ -1100,13 +1099,13 @@ bool e1000_get_laa_state_82571(struct e1000_hw *hw) + } + + /** +- * e1000_set_laa_state_82571 - Set locally administered address state ++ * e1000e_set_laa_state_82571 - Set locally administered address state + * @hw: pointer to the HW structure + * @state: enable/disable locally administered address + * + * Enable/Disable the current locally administed address state. + **/ +-void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) ++void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state) + { + if (hw->mac.type != e1000_82571) + return; +@@ -1121,7 +1120,7 @@ void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) + * incoming packets directed to this port are dropped. + * Eventually the LAA will be in RAR[0] and RAR[14]. + */ +- e1000_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1); ++ e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1); + } + + /** +@@ -1167,7 +1166,7 @@ static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) + ret_val = e1000_write_nvm(hw, 0x23, 1, &data); + if (ret_val) + return ret_val; +- ret_val = e1000_update_nvm_checksum(hw); ++ ret_val = e1000e_update_nvm_checksum(hw); + } + } + +@@ -1184,7 +1183,7 @@ static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) + { + u32 temp; + +- e1000_clear_hw_cntrs_base(hw); ++ e1000e_clear_hw_cntrs_base(hw); + + temp = er32(PRC64); + temp = er32(PRC127); +@@ -1225,12 +1224,12 @@ static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) + static struct e1000_mac_operations e82571_mac_ops = { + .mng_mode_enab = E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT, + /* .check_for_link: media type dependent */ +- .cleanup_led = e1000_cleanup_led_generic, ++ .cleanup_led = e1000e_cleanup_led_generic, + .clear_hw_cntrs = e1000_clear_hw_cntrs_82571, +- .get_bus_info = e1000_get_bus_info_pcie, ++ .get_bus_info = e1000e_get_bus_info_pcie, + /* .get_link_up_info: media type dependent */ +- .led_on = e1000_led_on_generic, +- .led_off = e1000_led_off_generic, ++ .led_on = e1000e_led_on_generic, ++ .led_off = e1000e_led_off_generic, + .mc_addr_list_update = e1000_mc_addr_list_update_82571, + .reset_hw = e1000_reset_hw_82571, + .init_hw = e1000_init_hw_82571, +@@ -1240,39 +1239,39 @@ static struct e1000_mac_operations e82571_mac_ops = { + + static struct e1000_phy_operations e82_phy_ops_igp = { + .acquire_phy = e1000_get_hw_semaphore_82571, +- .check_reset_block = e1000_check_reset_block_generic, ++ .check_reset_block = e1000e_check_reset_block_generic, + .commit_phy = NULL, +- .force_speed_duplex = e1000_phy_force_speed_duplex_igp, ++ .force_speed_duplex = e1000e_phy_force_speed_duplex_igp, + .get_cfg_done = e1000_get_cfg_done_82571, +- .get_cable_length = e1000_get_cable_length_igp_2, +- .get_phy_info = e1000_get_phy_info_igp, +- .read_phy_reg = e1000_read_phy_reg_igp, ++ .get_cable_length = e1000e_get_cable_length_igp_2, ++ .get_phy_info = e1000e_get_phy_info_igp, ++ .read_phy_reg = e1000e_read_phy_reg_igp, + .release_phy = e1000_put_hw_semaphore_82571, +- .reset_phy = e1000_phy_hw_reset_generic, ++ .reset_phy = e1000e_phy_hw_reset_generic, + .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, +- .set_d3_lplu_state = e1000_set_d3_lplu_state, +- .write_phy_reg = e1000_write_phy_reg_igp, ++ .set_d3_lplu_state = e1000e_set_d3_lplu_state, ++ .write_phy_reg = e1000e_write_phy_reg_igp, + }; + + static struct e1000_phy_operations e82_phy_ops_m88 = { + .acquire_phy = e1000_get_hw_semaphore_82571, +- .check_reset_block = e1000_check_reset_block_generic, +- .commit_phy = e1000_phy_sw_reset, +- .force_speed_duplex = e1000_phy_force_speed_duplex_m88, +- .get_cfg_done = e1000_get_cfg_done, +- .get_cable_length = e1000_get_cable_length_m88, +- .get_phy_info = e1000_get_phy_info_m88, +- .read_phy_reg = e1000_read_phy_reg_m88, ++ .check_reset_block = e1000e_check_reset_block_generic, ++ .commit_phy = e1000e_phy_sw_reset, ++ .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, ++ .get_cfg_done = e1000e_get_cfg_done, ++ .get_cable_length = e1000e_get_cable_length_m88, ++ .get_phy_info = e1000e_get_phy_info_m88, ++ .read_phy_reg = e1000e_read_phy_reg_m88, + .release_phy = e1000_put_hw_semaphore_82571, +- .reset_phy = e1000_phy_hw_reset_generic, ++ .reset_phy = e1000e_phy_hw_reset_generic, + .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, +- .set_d3_lplu_state = e1000_set_d3_lplu_state, +- .write_phy_reg = e1000_write_phy_reg_m88, ++ .set_d3_lplu_state = e1000e_set_d3_lplu_state, ++ .write_phy_reg = e1000e_write_phy_reg_m88, + }; + + static struct e1000_nvm_operations e82571_nvm_ops = { + .acquire_nvm = e1000_acquire_nvm_82571, +- .read_nvm = e1000_read_nvm_spi, ++ .read_nvm = e1000e_read_nvm_spi, + .release_nvm = e1000_release_nvm_82571, + .update_nvm = e1000_update_nvm_checksum_82571, + .valid_led_default = e1000_valid_led_default_82571, +@@ -1282,7 +1281,7 @@ static struct e1000_nvm_operations e82571_nvm_ops = { + + static struct e1000_nvm_operations e82573_nvm_ops = { + .acquire_nvm = e1000_acquire_nvm_82571, +- .read_nvm = e1000_read_nvm_eerd, ++ .read_nvm = e1000e_read_nvm_eerd, + .release_nvm = e1000_release_nvm_82571, + .update_nvm = e1000_update_nvm_checksum_82571, + .valid_led_default = e1000_valid_led_default_82571, +diff --git a/drivers/net/e1000e/e1000.h b/drivers/net/e1000e/e1000.h +index de17537..3475e48 100644 +--- a/drivers/net/e1000e/e1000.h ++++ b/drivers/net/e1000e/e1000.h +@@ -337,26 +337,26 @@ enum latency_range { + latency_invalid = 255 + }; + +-extern char e1000_driver_name[]; +-extern const char e1000_driver_version[]; +- +-extern void e1000_check_options(struct e1000_adapter *adapter); +-extern void e1000_set_ethtool_ops(struct net_device *netdev); +- +-extern int e1000_up(struct e1000_adapter *adapter); +-extern void e1000_down(struct e1000_adapter *adapter); +-extern void e1000_reinit_locked(struct e1000_adapter *adapter); +-extern void e1000_reset(struct e1000_adapter *adapter); +-extern void e1000_power_up_phy(struct e1000_adapter *adapter); +-extern int e1000_setup_rx_resources(struct e1000_adapter *adapter); +-extern int e1000_setup_tx_resources(struct e1000_adapter *adapter); +-extern void e1000_free_rx_resources(struct e1000_adapter *adapter); +-extern void e1000_free_tx_resources(struct e1000_adapter *adapter); +-extern void e1000_update_stats(struct e1000_adapter *adapter); ++extern char e1000e_driver_name[]; ++extern const char e1000e_driver_version[]; ++ ++extern void e1000e_check_options(struct e1000_adapter *adapter); ++extern void e1000e_set_ethtool_ops(struct net_device *netdev); ++ ++extern int e1000e_up(struct e1000_adapter *adapter); ++extern void e1000e_down(struct e1000_adapter *adapter); ++extern void e1000e_reinit_locked(struct e1000_adapter *adapter); ++extern void e1000e_reset(struct e1000_adapter *adapter); ++extern void e1000e_power_up_phy(struct e1000_adapter *adapter); ++extern int e1000e_setup_rx_resources(struct e1000_adapter *adapter); ++extern int e1000e_setup_tx_resources(struct e1000_adapter *adapter); ++extern void e1000e_free_rx_resources(struct e1000_adapter *adapter); ++extern void e1000e_free_tx_resources(struct e1000_adapter *adapter); ++extern void e1000e_update_stats(struct e1000_adapter *adapter); + + extern unsigned int copybreak; + +-extern char *e1000_get_hw_dev_name(struct e1000_hw *hw); ++extern char *e1000e_get_hw_dev_name(struct e1000_hw *hw); + + extern struct e1000_info e1000_82571_info; + extern struct e1000_info e1000_82572_info; +@@ -365,79 +365,79 @@ extern struct e1000_info e1000_ich8_info; + extern struct e1000_info e1000_ich9_info; + extern struct e1000_info e1000_es2_info; + +-extern s32 e1000_commit_phy(struct e1000_hw *hw); ++extern s32 e1000e_commit_phy(struct e1000_hw *hw); + +-extern bool e1000_enable_mng_pass_thru(struct e1000_hw *hw); ++extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw); + +-extern bool e1000_get_laa_state_82571(struct e1000_hw *hw); +-extern void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state); ++extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw); ++extern void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state); + +-extern void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, ++extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, + bool state); +-extern void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); +-extern void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw); +- +-extern s32 e1000_check_for_copper_link(struct e1000_hw *hw); +-extern s32 e1000_check_for_fiber_link(struct e1000_hw *hw); +-extern s32 e1000_check_for_serdes_link(struct e1000_hw *hw); +-extern s32 e1000_cleanup_led_generic(struct e1000_hw *hw); +-extern s32 e1000_led_on_generic(struct e1000_hw *hw); +-extern s32 e1000_led_off_generic(struct e1000_hw *hw); +-extern s32 e1000_get_bus_info_pcie(struct e1000_hw *hw); +-extern s32 e1000_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex); +-extern s32 e1000_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex); +-extern s32 e1000_disable_pcie_master(struct e1000_hw *hw); +-extern s32 e1000_get_auto_rd_done(struct e1000_hw *hw); +-extern s32 e1000_id_led_init(struct e1000_hw *hw); +-extern void e1000_clear_hw_cntrs_base(struct e1000_hw *hw); +-extern s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw); +-extern s32 e1000_copper_link_setup_m88(struct e1000_hw *hw); +-extern s32 e1000_copper_link_setup_igp(struct e1000_hw *hw); +-extern s32 e1000_setup_link(struct e1000_hw *hw); +-extern void e1000_clear_vfta(struct e1000_hw *hw); +-extern void e1000_init_rx_addrs(struct e1000_hw *hw, u16 rar_count); +-extern void e1000_mc_addr_list_update_generic(struct e1000_hw *hw, ++extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); ++extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw); ++ ++extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw); ++extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw); ++extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw); ++extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw); ++extern s32 e1000e_led_on_generic(struct e1000_hw *hw); ++extern s32 e1000e_led_off_generic(struct e1000_hw *hw); ++extern s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw); ++extern s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex); ++extern s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex); ++extern s32 e1000e_disable_pcie_master(struct e1000_hw *hw); ++extern s32 e1000e_get_auto_rd_done(struct e1000_hw *hw); ++extern s32 e1000e_id_led_init(struct e1000_hw *hw); ++extern void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw); ++extern s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw); ++extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw); ++extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw); ++extern s32 e1000e_setup_link(struct e1000_hw *hw); ++extern void e1000e_clear_vfta(struct e1000_hw *hw); ++extern void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count); ++extern void e1000e_mc_addr_list_update_generic(struct e1000_hw *hw, + u8 *mc_addr_list, u32 mc_addr_count, + u32 rar_used_count, u32 rar_count); +-extern void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index); +-extern s32 e1000_set_fc_watermarks(struct e1000_hw *hw); +-extern void e1000_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop); +-extern s32 e1000_get_hw_semaphore(struct e1000_hw *hw); +-extern s32 e1000_valid_led_default(struct e1000_hw *hw, u16 *data); +-extern void e1000_config_collision_dist(struct e1000_hw *hw); +-extern s32 e1000_config_fc_after_link_up(struct e1000_hw *hw); +-extern s32 e1000_force_mac_fc(struct e1000_hw *hw); +-extern s32 e1000_blink_led(struct e1000_hw *hw); +-extern void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value); +-extern void e1000_reset_adaptive(struct e1000_hw *hw); +-extern void e1000_update_adaptive(struct e1000_hw *hw); +- +-extern s32 e1000_setup_copper_link(struct e1000_hw *hw); +-extern s32 e1000_get_phy_id(struct e1000_hw *hw); +-extern void e1000_put_hw_semaphore(struct e1000_hw *hw); +-extern s32 e1000_check_reset_block_generic(struct e1000_hw *hw); +-extern s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw); +-extern s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw); +-extern s32 e1000_get_phy_info_igp(struct e1000_hw *hw); +-extern s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); +-extern s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw); +-extern s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active); +-extern s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); +-extern s32 e1000_phy_sw_reset(struct e1000_hw *hw); +-extern s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw); +-extern s32 e1000_get_cfg_done(struct e1000_hw *hw); +-extern s32 e1000_get_cable_length_m88(struct e1000_hw *hw); +-extern s32 e1000_get_phy_info_m88(struct e1000_hw *hw); +-extern s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); +-extern s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); +-extern enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id); +-extern void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); +-extern s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data); +-extern s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data); +-extern s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, ++extern void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index); ++extern s32 e1000e_set_fc_watermarks(struct e1000_hw *hw); ++extern void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop); ++extern s32 e1000e_get_hw_semaphore(struct e1000_hw *hw); ++extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data); ++extern void e1000e_config_collision_dist(struct e1000_hw *hw); ++extern s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw); ++extern s32 e1000e_force_mac_fc(struct e1000_hw *hw); ++extern s32 e1000e_blink_led(struct e1000_hw *hw); ++extern void e1000e_write_vfta(struct e1000_hw *hw, u32 offset, u32 value); ++extern void e1000e_reset_adaptive(struct e1000_hw *hw); ++extern void e1000e_update_adaptive(struct e1000_hw *hw); ++ ++extern s32 e1000e_setup_copper_link(struct e1000_hw *hw); ++extern s32 e1000e_get_phy_id(struct e1000_hw *hw); ++extern void e1000e_put_hw_semaphore(struct e1000_hw *hw); ++extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw); ++extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw); ++extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw); ++extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw); ++extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); ++extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw); ++extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active); ++extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); ++extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw); ++extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw); ++extern s32 e1000e_get_cfg_done(struct e1000_hw *hw); ++extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw); ++extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw); ++extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); ++extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); ++extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id); ++extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); ++extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data); ++extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data); ++extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, + u32 usec_interval, bool *success); +-extern s32 e1000_phy_reset_dsp(struct e1000_hw *hw); +-extern s32 e1000_check_downshift(struct e1000_hw *hw); ++extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw); ++extern s32 e1000e_check_downshift(struct e1000_hw *hw); + + static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw) + { +@@ -464,23 +464,23 @@ static inline s32 e1000_get_cable_length(struct e1000_hw *hw) + return hw->phy.ops.get_cable_length(hw); + } + +-extern s32 e1000_acquire_nvm(struct e1000_hw *hw); +-extern s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); +-extern s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw); +-extern s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg); +-extern s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); +-extern s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); +-extern s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw); +-extern void e1000_release_nvm(struct e1000_hw *hw); +-extern void e1000_reload_nvm(struct e1000_hw *hw); +-extern s32 e1000_read_mac_addr(struct e1000_hw *hw); ++extern s32 e1000e_acquire_nvm(struct e1000_hw *hw); ++extern s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); ++extern s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw); ++extern s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg); ++extern s32 e1000e_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); ++extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); ++extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw); ++extern void e1000e_release_nvm(struct e1000_hw *hw); ++extern void e1000e_reload_nvm(struct e1000_hw *hw); ++extern s32 e1000e_read_mac_addr(struct e1000_hw *hw); + + static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw) + { + return hw->nvm.ops.validate_nvm(hw); + } + +-static inline s32 e1000_update_nvm_checksum(struct e1000_hw *hw) ++static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw) + { + return hw->nvm.ops.update_nvm(hw); + } +@@ -500,9 +500,9 @@ static inline s32 e1000_get_phy_info(struct e1000_hw *hw) + return hw->phy.ops.get_phy_info(hw); + } + +-extern bool e1000_check_mng_mode(struct e1000_hw *hw); +-extern bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw); +-extern s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length); ++extern bool e1000e_check_mng_mode(struct e1000_hw *hw); ++extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw); ++extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length); + + static inline u32 __er32(struct e1000_hw *hw, unsigned long reg) + { +diff --git a/drivers/net/e1000e/es2lan.c b/drivers/net/e1000e/es2lan.c +index 8100d03..88657ad 100644 +--- a/drivers/net/e1000e/es2lan.c ++++ b/drivers/net/e1000e/es2lan.c +@@ -129,7 +129,7 @@ static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) + phy->type = e1000_phy_gg82563; + + /* This can only be done after all function pointers are setup. */ +- ret_val = e1000_get_phy_id(hw); ++ ret_val = e1000e_get_phy_id(hw); + + /* Verify phy id */ + if (phy->id != GG82563_E_PHY_ID) +@@ -215,15 +215,15 @@ static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter) + switch (hw->media_type) { + case e1000_media_type_copper: + func->setup_physical_interface = e1000_setup_copper_link_80003es2lan; +- func->check_for_link = e1000_check_for_copper_link; ++ func->check_for_link = e1000e_check_for_copper_link; + break; + case e1000_media_type_fiber: +- func->setup_physical_interface = e1000_setup_fiber_serdes_link; +- func->check_for_link = e1000_check_for_fiber_link; ++ func->setup_physical_interface = e1000e_setup_fiber_serdes_link; ++ func->check_for_link = e1000e_check_for_fiber_link; + break; + case e1000_media_type_internal_serdes: +- func->setup_physical_interface = e1000_setup_fiber_serdes_link; +- func->check_for_link = e1000_check_for_serdes_link; ++ func->setup_physical_interface = e1000e_setup_fiber_serdes_link; ++ func->check_for_link = e1000e_check_for_serdes_link; + break; + default: + return -E1000_ERR_CONFIG; +@@ -299,7 +299,7 @@ static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) + if (ret_val) + return ret_val; + +- ret_val = e1000_acquire_nvm(hw); ++ ret_val = e1000e_acquire_nvm(hw); + + if (ret_val) + e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); +@@ -316,7 +316,7 @@ static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) + **/ + static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw) + { +- e1000_release_nvm(hw); ++ e1000e_release_nvm(hw); + e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); + } + +@@ -337,7 +337,7 @@ static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) + s32 timeout = 200; + + while (i < timeout) { +- if (e1000_get_hw_semaphore(hw)) ++ if (e1000e_get_hw_semaphore(hw)) + return -E1000_ERR_SWFW_SYNC; + + swfw_sync = er32(SW_FW_SYNC); +@@ -346,7 +346,7 @@ static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) + + /* Firmware currently using resource (fwmask) + * or other software thread using resource (swmask) */ +- e1000_put_hw_semaphore(hw); ++ e1000e_put_hw_semaphore(hw); + mdelay(5); + i++; + } +@@ -360,7 +360,7 @@ static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) + swfw_sync |= swmask; + ew32(SW_FW_SYNC, swfw_sync); + +- e1000_put_hw_semaphore(hw); ++ e1000e_put_hw_semaphore(hw); + + return 0; + } +@@ -377,14 +377,14 @@ static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) + { + u32 swfw_sync; + +- while (e1000_get_hw_semaphore(hw) != 0); ++ while (e1000e_get_hw_semaphore(hw) != 0); + /* Empty */ + + swfw_sync = er32(SW_FW_SYNC); + swfw_sync &= ~mask; + ew32(SW_FW_SYNC, swfw_sync); + +- e1000_put_hw_semaphore(hw); ++ e1000e_put_hw_semaphore(hw); + } + + /** +@@ -413,7 +413,7 @@ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, + page_select = GG82563_PHY_PAGE_SELECT_ALT; + + temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); +- ret_val = e1000_write_phy_reg_m88(hw, page_select, temp); ++ ret_val = e1000e_write_phy_reg_m88(hw, page_select, temp); + if (ret_val) + return ret_val; + +@@ -424,7 +424,7 @@ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, + udelay(200); + + /* ...and verify the command was successful. */ +- ret_val = e1000_read_phy_reg_m88(hw, page_select, &temp); ++ ret_val = e1000e_read_phy_reg_m88(hw, page_select, &temp); + + if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { + ret_val = -E1000_ERR_PHY; +@@ -433,7 +433,7 @@ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, + + udelay(200); + +- ret_val = e1000_read_phy_reg_m88(hw, ++ ret_val = e1000e_read_phy_reg_m88(hw, + MAX_PHY_REG_ADDRESS & offset, + data); + +@@ -468,7 +468,7 @@ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, + page_select = GG82563_PHY_PAGE_SELECT_ALT; + + temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); +- ret_val = e1000_write_phy_reg_m88(hw, page_select, temp); ++ ret_val = e1000e_write_phy_reg_m88(hw, page_select, temp); + if (ret_val) + return ret_val; + +@@ -480,14 +480,14 @@ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, + udelay(200); + + /* ...and verify the command was successful. */ +- ret_val = e1000_read_phy_reg_m88(hw, page_select, &temp); ++ ret_val = e1000e_read_phy_reg_m88(hw, page_select, &temp); + + if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) + return -E1000_ERR_PHY; + + udelay(200); + +- ret_val = e1000_write_phy_reg_m88(hw, ++ ret_val = e1000e_write_phy_reg_m88(hw, + MAX_PHY_REG_ADDRESS & offset, + data); + +@@ -509,7 +509,7 @@ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, + static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, + u16 words, u16 *data) + { +- return e1000_write_nvm_spi(hw, offset, words, data); ++ return e1000e_write_nvm_spi(hw, offset, words, data); + } + + /** +@@ -572,7 +572,7 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) + if (ret_val) + return ret_val; + +- e1000_phy_force_speed_duplex_setup(hw, &phy_data); ++ e1000e_phy_force_speed_duplex_setup(hw, &phy_data); + + /* Reset the phy to commit changes. */ + phy_data |= MII_CR_RESET; +@@ -587,7 +587,7 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) + hw_dbg(hw, "Waiting for forced speed/duplex link " + "on GG82563 phy.\n"); + +- ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, ++ ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, + 100000, &link); + if (ret_val) + return ret_val; +@@ -596,13 +596,13 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) + /* We didn't get link. + * Reset the DSP and cross our fingers. + */ +- ret_val = e1000_phy_reset_dsp(hw); ++ ret_val = e1000e_phy_reset_dsp(hw); + if (ret_val) + return ret_val; + } + + /* Try once more */ +- ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, ++ ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, + 100000, &link); + if (ret_val) + return ret_val; +@@ -672,7 +672,7 @@ static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, + s32 ret_val; + + if (hw->media_type == e1000_media_type_copper) { +- ret_val = e1000_get_speed_and_duplex_copper(hw, ++ ret_val = e1000e_get_speed_and_duplex_copper(hw, + speed, + duplex); + if (ret_val) +@@ -683,7 +683,7 @@ static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, + ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, + *duplex); + } else { +- ret_val = e1000_get_speed_and_duplex_fiber_serdes(hw, ++ ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw, + speed, + duplex); + } +@@ -707,7 +707,7 @@ static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) + /* Prevent the PCI-E bus from sticking if there is no TLP connection + * on the last TLP read/write transaction when MAC is reset. + */ +- ret_val = e1000_disable_pcie_master(hw); ++ ret_val = e1000e_disable_pcie_master(hw); + if (ret_val) + hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); + +@@ -725,7 +725,7 @@ static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) + hw_dbg(hw, "Issuing a global reset to MAC\n"); + ew32(CTRL, ctrl | E1000_CTRL_RST); + +- ret_val = e1000_get_auto_rd_done(hw); ++ ret_val = e1000e_get_auto_rd_done(hw); + if (ret_val) + /* We don't want to continue accessing MAC registers. */ + return ret_val; +@@ -754,7 +754,7 @@ static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) + e1000_initialize_hw_bits_80003es2lan(hw); + + /* Initialize identification LED */ +- ret_val = e1000_id_led_init(hw); ++ ret_val = e1000e_id_led_init(hw); + if (ret_val) { + hw_dbg(hw, "Error initializing identification LED\n"); + return ret_val; +@@ -762,10 +762,10 @@ static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) + + /* Disabling VLAN filtering */ + hw_dbg(hw, "Initializing the IEEE VLAN\n"); +- e1000_clear_vfta(hw); ++ e1000e_clear_vfta(hw); + + /* Setup the receive address. */ +- e1000_init_rx_addrs(hw, mac->rar_entry_count); ++ e1000e_init_rx_addrs(hw, mac->rar_entry_count); + + /* Zero out the Multicast HASH table */ + hw_dbg(hw, "Zeroing the MTA\n"); +@@ -773,7 +773,7 @@ static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); + + /* Setup link and flow control */ +- ret_val = e1000_setup_link(hw); ++ ret_val = e1000e_setup_link(hw); + + /* Set the transmit descriptor write-back policy */ + reg_data = er32(TXDCTL); +@@ -922,14 +922,14 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) + return ret_val; + + /* SW Reset the PHY so all changes take effect */ +- ret_val = e1000_commit_phy(hw); ++ ret_val = e1000e_commit_phy(hw); + if (ret_val) { + hw_dbg(hw, "Error Resetting the PHY\n"); + return ret_val; + } + + /* Bypass RX and TX FIFO's */ +- ret_val = e1000_write_kmrn_reg(hw, ++ ret_val = e1000e_write_kmrn_reg(hw, + E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL, + E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | + E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); +@@ -957,7 +957,7 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) + * firmware will have already initialized them. We only initialize + * them if the HW is not in IAMT mode. + */ +- if (!e1000_check_mng_mode(hw)) { ++ if (!e1000e_check_mng_mode(hw)) { + /* Enable Electrical Idle on the PHY */ + data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; + ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data); +@@ -1010,23 +1010,23 @@ static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) + /* Set the mac to wait the maximum time between each + * iteration and increase the max iterations when + * polling the phy; this fixes erroneous timeouts at 10Mbps. */ +- ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); ++ ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); + if (ret_val) + return ret_val; +- ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); ++ ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); + if (ret_val) + return ret_val; + reg_data |= 0x3F; +- ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); ++ ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); + if (ret_val) + return ret_val; +- ret_val = e1000_read_kmrn_reg(hw, ++ ret_val = e1000e_read_kmrn_reg(hw, + E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, + ®_data); + if (ret_val) + return ret_val; + reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; +- ret_val = e1000_write_kmrn_reg(hw, ++ ret_val = e1000e_write_kmrn_reg(hw, + E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, + reg_data); + if (ret_val) +@@ -1036,7 +1036,7 @@ static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) + if (ret_val) + return ret_val; + +- ret_val = e1000_setup_copper_link(hw); ++ ret_val = e1000e_setup_copper_link(hw); + + return 0; + } +@@ -1056,7 +1056,7 @@ static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) + u16 reg_data; + + reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; +- ret_val = e1000_write_kmrn_reg(hw, ++ ret_val = e1000e_write_kmrn_reg(hw, + E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, + reg_data); + if (ret_val) +@@ -1096,7 +1096,7 @@ static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) + u32 tipg; + + reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; +- ret_val = e1000_write_kmrn_reg(hw, ++ ret_val = e1000e_write_kmrn_reg(hw, + E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, + reg_data); + if (ret_val) +@@ -1128,7 +1128,7 @@ static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) + { + u32 temp; + +- e1000_clear_hw_cntrs_base(hw); ++ e1000e_clear_hw_cntrs_base(hw); + + temp = er32(PRC64); + temp = er32(PRC127); +@@ -1169,42 +1169,42 @@ static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) + static struct e1000_mac_operations es2_mac_ops = { + .mng_mode_enab = E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT, + /* check_for_link dependent on media type */ +- .cleanup_led = e1000_cleanup_led_generic, ++ .cleanup_led = e1000e_cleanup_led_generic, + .clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan, +- .get_bus_info = e1000_get_bus_info_pcie, ++ .get_bus_info = e1000e_get_bus_info_pcie, + .get_link_up_info = e1000_get_link_up_info_80003es2lan, +- .led_on = e1000_led_on_generic, +- .led_off = e1000_led_off_generic, +- .mc_addr_list_update = e1000_mc_addr_list_update_generic, ++ .led_on = e1000e_led_on_generic, ++ .led_off = e1000e_led_off_generic, ++ .mc_addr_list_update = e1000e_mc_addr_list_update_generic, + .reset_hw = e1000_reset_hw_80003es2lan, + .init_hw = e1000_init_hw_80003es2lan, +- .setup_link = e1000_setup_link, ++ .setup_link = e1000e_setup_link, + /* setup_physical_interface dependent on media type */ + }; + + static struct e1000_phy_operations es2_phy_ops = { + .acquire_phy = e1000_acquire_phy_80003es2lan, +- .check_reset_block = e1000_check_reset_block_generic, +- .commit_phy = e1000_phy_sw_reset, ++ .check_reset_block = e1000e_check_reset_block_generic, ++ .commit_phy = e1000e_phy_sw_reset, + .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan, + .get_cfg_done = e1000_get_cfg_done_80003es2lan, + .get_cable_length = e1000_get_cable_length_80003es2lan, +- .get_phy_info = e1000_get_phy_info_m88, ++ .get_phy_info = e1000e_get_phy_info_m88, + .read_phy_reg = e1000_read_phy_reg_gg82563_80003es2lan, + .release_phy = e1000_release_phy_80003es2lan, +- .reset_phy = e1000_phy_hw_reset_generic, ++ .reset_phy = e1000e_phy_hw_reset_generic, + .set_d0_lplu_state = NULL, +- .set_d3_lplu_state = e1000_set_d3_lplu_state, ++ .set_d3_lplu_state = e1000e_set_d3_lplu_state, + .write_phy_reg = e1000_write_phy_reg_gg82563_80003es2lan, + }; + + static struct e1000_nvm_operations es2_nvm_ops = { + .acquire_nvm = e1000_acquire_nvm_80003es2lan, +- .read_nvm = e1000_read_nvm_eerd, ++ .read_nvm = e1000e_read_nvm_eerd, + .release_nvm = e1000_release_nvm_80003es2lan, +- .update_nvm = e1000_update_nvm_checksum_generic, +- .valid_led_default = e1000_valid_led_default, +- .validate_nvm = e1000_validate_nvm_checksum_generic, ++ .update_nvm = e1000e_update_nvm_checksum_generic, ++ .valid_led_default = e1000e_valid_led_default, ++ .validate_nvm = e1000e_validate_nvm_checksum_generic, + .write_nvm = e1000_write_nvm_80003es2lan, + }; + +diff --git a/drivers/net/e1000e/ethtool.c b/drivers/net/e1000e/ethtool.c +index a8fa1db..c9d74a8 100644 +--- a/drivers/net/e1000e/ethtool.c ++++ b/drivers/net/e1000e/ethtool.c +@@ -246,10 +246,10 @@ static int e1000_set_settings(struct net_device *netdev, + /* reset the link */ + + if (netif_running(adapter->netdev)) { +- e1000_down(adapter); +- e1000_up(adapter); ++ e1000e_down(adapter); ++ e1000e_up(adapter); + } else { +- e1000_reset(adapter); ++ e1000e_reset(adapter); + } + + clear_bit(__E1000_RESETTING, &adapter->state); +@@ -300,14 +300,14 @@ static int e1000_set_pauseparam(struct net_device *netdev, + + if (adapter->fc_autoneg == AUTONEG_ENABLE) { + if (netif_running(adapter->netdev)) { +- e1000_down(adapter); +- e1000_up(adapter); ++ e1000e_down(adapter); ++ e1000e_up(adapter); + } else { +- e1000_reset(adapter); ++ e1000e_reset(adapter); + } + } else { + retval = ((hw->media_type == e1000_media_type_fiber) ? +- hw->mac.ops.setup_link(hw) : e1000_force_mac_fc(hw)); ++ hw->mac.ops.setup_link(hw) : e1000e_force_mac_fc(hw)); + } + + clear_bit(__E1000_RESETTING, &adapter->state); +@@ -330,9 +330,9 @@ static int e1000_set_rx_csum(struct net_device *netdev, u32 data) + adapter->flags &= ~FLAG_RX_CSUM_ENABLED; + + if (netif_running(netdev)) +- e1000_reinit_locked(adapter); ++ e1000e_reinit_locked(adapter); + else +- e1000_reset(adapter); ++ e1000e_reset(adapter); + return 0; + } + +@@ -549,7 +549,7 @@ static int e1000_set_eeprom(struct net_device *netdev, + * and flush shadow RAM for 82573 controllers */ + if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG) || + (hw->mac.type == e1000_82573))) +- e1000_update_nvm_checksum(hw); ++ e1000e_update_nvm_checksum(hw); + + kfree(eeprom_buff); + return ret_val; +@@ -562,8 +562,8 @@ static void e1000_get_drvinfo(struct net_device *netdev, + char firmware_version[32]; + u16 eeprom_data; + +- strncpy(drvinfo->driver, e1000_driver_name, 32); +- strncpy(drvinfo->version, e1000_driver_version, 32); ++ strncpy(drvinfo->driver, e1000e_driver_name, 32); ++ strncpy(drvinfo->version, e1000e_driver_version, 32); + + /* EEPROM image version # is reported as firmware version # for + * PCI-E controllers */ +@@ -613,7 +613,7 @@ static int e1000_set_ringparam(struct net_device *netdev, + msleep(1); + + if (netif_running(adapter->netdev)) +- e1000_down(adapter); ++ e1000e_down(adapter); + + tx_old = adapter->tx_ring; + rx_old = adapter->rx_ring; +@@ -640,10 +640,10 @@ static int e1000_set_ringparam(struct net_device *netdev, + + if (netif_running(adapter->netdev)) { + /* Try to get new resources before deleting old */ +- err = e1000_setup_rx_resources(adapter); ++ err = e1000e_setup_rx_resources(adapter); + if (err) + goto err_setup_rx; +- err = e1000_setup_tx_resources(adapter); ++ err = e1000e_setup_tx_resources(adapter); + if (err) + goto err_setup_tx; + +@@ -651,13 +651,13 @@ static int e1000_set_ringparam(struct net_device *netdev, + * then restore the new back again */ + adapter->rx_ring = rx_old; + adapter->tx_ring = tx_old; +- e1000_free_rx_resources(adapter); +- e1000_free_tx_resources(adapter); ++ e1000e_free_rx_resources(adapter); ++ e1000e_free_tx_resources(adapter); + kfree(tx_old); + kfree(rx_old); + adapter->rx_ring = rx_ring; + adapter->tx_ring = tx_ring; +- err = e1000_up(adapter); ++ err = e1000e_up(adapter); + if (err) + goto err_setup; + } +@@ -665,7 +665,7 @@ static int e1000_set_ringparam(struct net_device *netdev, + clear_bit(__E1000_RESETTING, &adapter->state); + return 0; + err_setup_tx: +- e1000_free_rx_resources(adapter); ++ e1000e_free_rx_resources(adapter); + err_setup_rx: + adapter->rx_ring = rx_old; + adapter->tx_ring = tx_old; +@@ -673,7 +673,7 @@ err_setup_rx: + err_alloc_rx: + kfree(tx_ring); + err_alloc_tx: +- e1000_up(adapter); ++ e1000e_up(adapter); + err_setup: + clear_bit(__E1000_RESETTING, &adapter->state); + return err; +@@ -1326,7 +1326,7 @@ static void e1000_loopback_cleanup(struct e1000_adapter *adapter) + if (phy_reg & MII_CR_LOOPBACK) { + phy_reg &= ~MII_CR_LOOPBACK; + e1e_wphy(hw, PHY_CONTROL, phy_reg); +- e1000_commit_phy(hw); ++ e1000e_commit_phy(hw); + } + break; + } +@@ -1517,22 +1517,22 @@ static void e1000_diag_test(struct net_device *netdev, + /* indicate we're in test mode */ + dev_close(netdev); + else +- e1000_reset(adapter); ++ e1000e_reset(adapter); + + if (e1000_reg_test(adapter, &data[0])) + eth_test->flags |= ETH_TEST_FL_FAILED; + +- e1000_reset(adapter); ++ e1000e_reset(adapter); + if (e1000_eeprom_test(adapter, &data[1])) + eth_test->flags |= ETH_TEST_FL_FAILED; + +- e1000_reset(adapter); ++ e1000e_reset(adapter); + if (e1000_intr_test(adapter, &data[2])) + eth_test->flags |= ETH_TEST_FL_FAILED; + +- e1000_reset(adapter); ++ e1000e_reset(adapter); + /* make sure the phy is powered up */ +- e1000_power_up_phy(adapter); ++ e1000e_power_up_phy(adapter); + if (e1000_loopback_test(adapter, &data[3])) + eth_test->flags |= ETH_TEST_FL_FAILED; + +@@ -1543,7 +1543,7 @@ static void e1000_diag_test(struct net_device *netdev, + + /* force this routine to wait until autoneg complete/timeout */ + adapter->hw.phy.wait_for_link = 1; +- e1000_reset(adapter); ++ e1000e_reset(adapter); + adapter->hw.phy.wait_for_link = 0; + + clear_bit(__E1000_TESTING, &adapter->state); +@@ -1663,7 +1663,7 @@ static int e1000_phys_id(struct net_device *netdev, u32 data) + e1e_wphy(&adapter->hw, + IFE_PHY_SPECIAL_CONTROL_LED, 0); + } else { +- e1000_blink_led(&adapter->hw); ++ e1000e_blink_led(&adapter->hw); + msleep_interruptible(data * 1000); + } + +@@ -1678,7 +1678,7 @@ static int e1000_nway_reset(struct net_device *netdev) + { + struct e1000_adapter *adapter = netdev_priv(netdev); + if (netif_running(netdev)) +- e1000_reinit_locked(adapter); ++ e1000e_reinit_locked(adapter); + return 0; + } + +@@ -1694,7 +1694,7 @@ static void e1000_get_ethtool_stats(struct net_device *netdev, + struct e1000_adapter *adapter = netdev_priv(netdev); + int i; + +- e1000_update_stats(adapter); ++ e1000e_update_stats(adapter); + for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) { + char *p = (char *)adapter+e1000_gstrings_stats[i].stat_offset; + data[i] = (e1000_gstrings_stats[i].sizeof_stat == +@@ -1758,7 +1758,7 @@ static const struct ethtool_ops e1000_ethtool_ops = { + .get_ethtool_stats = e1000_get_ethtool_stats, + }; + +-void e1000_set_ethtool_ops(struct net_device *netdev) ++void e1000e_set_ethtool_ops(struct net_device *netdev) + { + SET_ETHTOOL_OPS(netdev, &e1000_ethtool_ops); + } +diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c +index 85095af..8f8139d 100644 +--- a/drivers/net/e1000e/ich8lan.c ++++ b/drivers/net/e1000e/ich8lan.c +@@ -199,10 +199,10 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) + phy->reset_delay_us = 100; + + phy->id = 0; +- while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) && ++ while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && + (i++ < 100)) { + msleep(1); +- ret_val = e1000_get_phy_id(hw); ++ ret_val = e1000e_get_phy_id(hw); + if (ret_val) + return ret_val; + } +@@ -308,7 +308,7 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter) + + /* Enable PCS Lock-loss workaround for ICH8 */ + if (mac->type == e1000_ich8lan) +- e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, 1); ++ e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1); + + return 0; + } +@@ -420,7 +420,7 @@ static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw) + bool link; + + if (phy->type != e1000_phy_ife) { +- ret_val = e1000_phy_force_speed_duplex_igp(hw); ++ ret_val = e1000e_phy_force_speed_duplex_igp(hw); + return ret_val; + } + +@@ -428,7 +428,7 @@ static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw) + if (ret_val) + return ret_val; + +- e1000_phy_force_speed_duplex_setup(hw, &data); ++ e1000e_phy_force_speed_duplex_setup(hw, &data); + + ret_val = e1e_wphy(hw, PHY_CONTROL, data); + if (ret_val) +@@ -453,7 +453,7 @@ static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw) + if (phy->wait_for_link) { + hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n"); + +- ret_val = e1000_phy_has_link_generic(hw, ++ ret_val = e1000e_phy_has_link_generic(hw, + PHY_FORCE_LIMIT, + 100000, + &link); +@@ -464,7 +464,7 @@ static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw) + hw_dbg(hw, "Link taking longer than expected.\n"); + + /* Try once more */ +- ret_val = e1000_phy_has_link_generic(hw, ++ ret_val = e1000e_phy_has_link_generic(hw, + PHY_FORCE_LIMIT, + 100000, + &link); +@@ -492,7 +492,7 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) + u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT; + u16 word_addr, reg_data, reg_addr, phy_page = 0; + +- ret_val = e1000_phy_hw_reset_generic(hw); ++ ret_val = e1000e_phy_hw_reset_generic(hw); + if (ret_val) + return ret_val; + +@@ -604,7 +604,7 @@ static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw) + u16 data; + bool link; + +- ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); ++ ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); + if (ret_val) + return ret_val; + +@@ -658,7 +658,7 @@ static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw) + return e1000_get_phy_info_ife_ich8lan(hw); + break; + case e1000_phy_igp_3: +- return e1000_get_phy_info_igp(hw); ++ return e1000e_get_phy_info_igp(hw); + break; + default: + break; +@@ -735,7 +735,7 @@ static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) + * any PHY registers */ + if ((hw->mac.type == e1000_ich8lan) && + (hw->phy.type == e1000_phy_igp_3)) +- e1000_gig_downshift_workaround_ich8lan(hw); ++ e1000e_gig_downshift_workaround_ich8lan(hw); + + /* When LPLU is enabled, we should disable SmartSpeed */ + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); +@@ -845,7 +845,7 @@ static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) + * any PHY registers */ + if ((hw->mac.type == e1000_ich8lan) && + (hw->phy.type == e1000_phy_igp_3)) +- e1000_gig_downshift_workaround_ich8lan(hw); ++ e1000e_gig_downshift_workaround_ich8lan(hw); + + /* When LPLU is enabled, we should disable SmartSpeed */ + ret_val = e1e_rphy(hw, +@@ -1166,7 +1166,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) + s32 ret_val; + u16 data; + +- ret_val = e1000_update_nvm_checksum_generic(hw); ++ ret_val = e1000e_update_nvm_checksum_generic(hw); + if (ret_val) + return ret_val;; + +@@ -1275,7 +1275,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) + /* Reload the EEPROM, or else modifications will not appear + * until after the next adapter reset. + */ +- e1000_reload_nvm(hw); ++ e1000e_reload_nvm(hw); + msleep(10); + + return ret_val; +@@ -1308,12 +1308,12 @@ static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) + ret_val = e1000_write_nvm(hw, 0x19, 1, &data); + if (ret_val) + return ret_val; +- ret_val = e1000_update_nvm_checksum(hw); ++ ret_val = e1000e_update_nvm_checksum(hw); + if (ret_val) + return ret_val; + } + +- return e1000_validate_nvm_checksum_generic(hw); ++ return e1000e_validate_nvm_checksum_generic(hw); + } + + /** +@@ -1583,7 +1583,7 @@ static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) + struct e1000_bus_info *bus = &hw->bus; + s32 ret_val; + +- ret_val = e1000_get_bus_info_pcie(hw); ++ ret_val = e1000e_get_bus_info_pcie(hw); + + /* ICH devices are "PCI Express"-ish. They have + * a configuration space, but do not contain +@@ -1611,7 +1611,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) + /* Prevent the PCI-E bus from sticking if there is no TLP connection + * on the last TLP read/write transaction when MAC is reset. + */ +- ret_val = e1000_disable_pcie_master(hw); ++ ret_val = e1000e_disable_pcie_master(hw); + if (ret_val) { + hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); + } +@@ -1651,7 +1651,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) + ew32(CTRL, (ctrl | E1000_CTRL_RST)); + msleep(20); + +- ret_val = e1000_get_auto_rd_done(hw); ++ ret_val = e1000e_get_auto_rd_done(hw); + if (ret_val) { + /* + * When auto config read does not complete, do not +@@ -1693,14 +1693,14 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) + e1000_initialize_hw_bits_ich8lan(hw); + + /* Initialize identification LED */ +- ret_val = e1000_id_led_init(hw); ++ ret_val = e1000e_id_led_init(hw); + if (ret_val) { + hw_dbg(hw, "Error initializing identification LED\n"); + return ret_val; + } + + /* Setup the receive address. */ +- e1000_init_rx_addrs(hw, mac->rar_entry_count); ++ e1000e_init_rx_addrs(hw, mac->rar_entry_count); + + /* Zero out the Multicast HASH table */ + hw_dbg(hw, "Zeroing the MTA\n"); +@@ -1730,7 +1730,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) + snoop = PCIE_ICH8_SNOOP_ALL; + else + snoop = (u32) ~(PCIE_NO_SNOOP_ALL); +- e1000_set_pcie_no_snoop(hw, snoop); ++ e1000e_set_pcie_no_snoop(hw, snoop); + + ctrl_ext = er32(CTRL_EXT); + ctrl_ext |= E1000_CTRL_EXT_RO_DIS; +@@ -1831,7 +1831,7 @@ static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) + + ew32(FCTTV, mac->fc_pause_time); + +- return e1000_set_fc_watermarks(hw); ++ return e1000e_set_fc_watermarks(hw); + } + + /** +@@ -1856,24 +1856,24 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) + /* Set the mac to wait the maximum time between each iteration + * and increase the max iterations when polling the phy; + * this fixes erroneous timeouts at 10Mbps. */ +- ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); ++ ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); + if (ret_val) + return ret_val; +- ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); ++ ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); + if (ret_val) + return ret_val; + reg_data |= 0x3F; +- ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); ++ ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); + if (ret_val) + return ret_val; + + if (hw->phy.type == e1000_phy_igp_3) { +- ret_val = e1000_copper_link_setup_igp(hw); ++ ret_val = e1000e_copper_link_setup_igp(hw); + if (ret_val) + return ret_val; + } + +- return e1000_setup_copper_link(hw); ++ return e1000e_setup_copper_link(hw); + } + + /** +@@ -1891,7 +1891,7 @@ static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, + { + s32 ret_val; + +- ret_val = e1000_get_speed_and_duplex_copper(hw, speed, duplex); ++ ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); + if (ret_val) + return ret_val; + +@@ -1933,7 +1933,7 @@ static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) + /* Make sure link is up before proceeding. If not just return. + * Attempting this while link is negotiating fouled up link + * stability */ +- ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); ++ ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); + if (!link) + return 0; + +@@ -1963,7 +1963,7 @@ static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) + + /* Call gig speed drop workaround on Giga disable before accessing + * any PHY registers */ +- e1000_gig_downshift_workaround_ich8lan(hw); ++ e1000e_gig_downshift_workaround_ich8lan(hw); + + /* unable to acquire PCS lock */ + return -E1000_ERR_PHY; +@@ -1977,7 +1977,7 @@ static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) + * If ICH8, set the current Kumeran workaround state (enabled - TRUE + * /disabled - FALSE). + **/ +-void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, ++void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, + bool state) + { + struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; +@@ -2000,7 +2000,7 @@ void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, + * 3) read it back + * Continue if successful, else issue LCD reset and repeat + **/ +-void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) ++void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) + { + u32 reg; + u16 data; +@@ -2020,7 +2020,7 @@ void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) + /* Call gig speed drop workaround on Giga disable before + * accessing any PHY registers */ + if (hw->mac.type == e1000_ich8lan) +- e1000_gig_downshift_workaround_ich8lan(hw); ++ e1000e_gig_downshift_workaround_ich8lan(hw); + + /* Write VR power-down enable */ + e1e_rphy(hw, IGP3_VR_CTRL, &data); +@@ -2041,7 +2041,7 @@ void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) + } + + /** +- * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working ++ * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working + * @hw: pointer to the HW structure + * + * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), +@@ -2050,7 +2050,7 @@ void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) + * 2) Clear Kumeran Near-end loopback + * Should only be called for ICH8[m] devices with IGP_3 Phy. + **/ +-void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) ++void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) + { + s32 ret_val; + u16 reg_data; +@@ -2059,17 +2059,17 @@ void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) + (hw->phy.type != e1000_phy_igp_3)) + return; + +- ret_val = e1000_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, ++ ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, + ®_data); + if (ret_val) + return; + reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; +- ret_val = e1000_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, ++ ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, + reg_data); + if (ret_val) + return; + reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; +- ret_val = e1000_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, ++ ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, + reg_data); + } + +@@ -2131,7 +2131,7 @@ static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) + { + u32 temp; + +- e1000_clear_hw_cntrs_base(hw); ++ e1000e_clear_hw_cntrs_base(hw); + + temp = er32(ALGNERRC); + temp = er32(RXERRC); +@@ -2151,14 +2151,14 @@ static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) + + static struct e1000_mac_operations ich8_mac_ops = { + .mng_mode_enab = E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT, +- .check_for_link = e1000_check_for_copper_link, ++ .check_for_link = e1000e_check_for_copper_link, + .cleanup_led = e1000_cleanup_led_ich8lan, + .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, + .get_bus_info = e1000_get_bus_info_ich8lan, + .get_link_up_info = e1000_get_link_up_info_ich8lan, + .led_on = e1000_led_on_ich8lan, + .led_off = e1000_led_off_ich8lan, +- .mc_addr_list_update = e1000_mc_addr_list_update_generic, ++ .mc_addr_list_update = e1000e_mc_addr_list_update_generic, + .reset_hw = e1000_reset_hw_ich8lan, + .init_hw = e1000_init_hw_ich8lan, + .setup_link = e1000_setup_link_ich8lan, +@@ -2170,15 +2170,15 @@ static struct e1000_phy_operations ich8_phy_ops = { + .check_reset_block = e1000_check_reset_block_ich8lan, + .commit_phy = NULL, + .force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan, +- .get_cfg_done = e1000_get_cfg_done, +- .get_cable_length = e1000_get_cable_length_igp_2, ++ .get_cfg_done = e1000e_get_cfg_done, ++ .get_cable_length = e1000e_get_cable_length_igp_2, + .get_phy_info = e1000_get_phy_info_ich8lan, +- .read_phy_reg = e1000_read_phy_reg_igp, ++ .read_phy_reg = e1000e_read_phy_reg_igp, + .release_phy = e1000_release_swflag_ich8lan, + .reset_phy = e1000_phy_hw_reset_ich8lan, + .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, + .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, +- .write_phy_reg = e1000_write_phy_reg_igp, ++ .write_phy_reg = e1000e_write_phy_reg_igp, + }; + + static struct e1000_nvm_operations ich8_nvm_ops = { +diff --git a/drivers/net/e1000e/lib.c b/drivers/net/e1000e/lib.c +index c92ea77..a04c1e4 100644 +--- a/drivers/net/e1000e/lib.c ++++ b/drivers/net/e1000e/lib.c +@@ -47,14 +47,14 @@ enum e1000_mng_mode { + * Technology signature */ + + /** +- * e1000_get_bus_info_pcie - Get PCIe bus information ++ * e1000e_get_bus_info_pcie - Get PCIe bus information + * @hw: pointer to the HW structure + * + * Determines and stores the system bus information for a particular + * network interface. The following bus information is determined and stored: + * bus speed, bus width, type (PCIe), and PCIe function. + **/ +-s32 e1000_get_bus_info_pcie(struct e1000_hw *hw) ++s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw) + { + struct e1000_bus_info *bus = &hw->bus; + struct e1000_adapter *adapter = hw->adapter; +@@ -87,7 +87,7 @@ s32 e1000_get_bus_info_pcie(struct e1000_hw *hw) + } + + /** +- * e1000_write_vfta - Write value to VLAN filter table ++ * e1000e_write_vfta - Write value to VLAN filter table + * @hw: pointer to the HW structure + * @offset: register offset in VLAN filter table + * @value: register value written to VLAN filter table +@@ -95,14 +95,14 @@ s32 e1000_get_bus_info_pcie(struct e1000_hw *hw) + * Writes value at the given offset in the register array which stores + * the VLAN filter table. + **/ +-void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) ++void e1000e_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) + { + E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); + e1e_flush(); + } + + /** +- * e1000_init_rx_addrs - Initialize receive address's ++ * e1000e_init_rx_addrs - Initialize receive address's + * @hw: pointer to the HW structure + * @rar_count: receive address registers + * +@@ -110,14 +110,14 @@ void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) + * register to the devices MAC address and clearing all the other receive + * address registers to 0. + **/ +-void e1000_init_rx_addrs(struct e1000_hw *hw, u16 rar_count) ++void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count) + { + u32 i; + + /* Setup the receive address */ + hw_dbg(hw, "Programming MAC Address into RAR[0]\n"); + +- e1000_rar_set(hw, hw->mac.addr, 0); ++ e1000e_rar_set(hw, hw->mac.addr, 0); + + /* Zero out the other (rar_entry_count - 1) receive addresses */ + hw_dbg(hw, "Clearing RAR[1-%u]\n", rar_count-1); +@@ -130,7 +130,7 @@ void e1000_init_rx_addrs(struct e1000_hw *hw, u16 rar_count) + } + + /** +- * e1000_rar_set - Set receive address register ++ * e1000e_rar_set - Set receive address register + * @hw: pointer to the HW structure + * @addr: pointer to the receive address + * @index: receive address array register +@@ -138,7 +138,7 @@ void e1000_init_rx_addrs(struct e1000_hw *hw, u16 rar_count) + * Sets the receive address array register at index to the address passed + * in by addr. + **/ +-void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) ++void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) + { + u32 rar_low, rar_high; + +@@ -260,7 +260,7 @@ static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) + } + + /** +- * e1000_mc_addr_list_update_generic - Update Multicast addresses ++ * e1000e_mc_addr_list_update_generic - Update Multicast addresses + * @hw: pointer to the HW structure + * @mc_addr_list: array of multicast addresses to program + * @mc_addr_count: number of multicast addresses to program +@@ -272,7 +272,7 @@ static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) + * The parameter rar_count will usually be hw->mac.rar_entry_count + * unless there are workarounds that change this. + **/ +-void e1000_mc_addr_list_update_generic(struct e1000_hw *hw, ++void e1000e_mc_addr_list_update_generic(struct e1000_hw *hw, + u8 *mc_addr_list, u32 mc_addr_count, + u32 rar_used_count, u32 rar_count) + { +@@ -285,7 +285,7 @@ void e1000_mc_addr_list_update_generic(struct e1000_hw *hw, + */ + for (i = rar_used_count; i < rar_count; i++) { + if (mc_addr_count) { +- e1000_rar_set(hw, mc_addr_list, i); ++ e1000e_rar_set(hw, mc_addr_list, i); + mc_addr_count--; + mc_addr_list += ETH_ALEN; + } else { +@@ -313,12 +313,12 @@ void e1000_mc_addr_list_update_generic(struct e1000_hw *hw, + } + + /** +- * e1000_clear_hw_cntrs_base - Clear base hardware counters ++ * e1000e_clear_hw_cntrs_base - Clear base hardware counters + * @hw: pointer to the HW structure + * + * Clears the base hardware counters by reading the counter registers. + **/ +-void e1000_clear_hw_cntrs_base(struct e1000_hw *hw) ++void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw) + { + u32 temp; + +@@ -362,14 +362,14 @@ void e1000_clear_hw_cntrs_base(struct e1000_hw *hw) + } + + /** +- * e1000_check_for_copper_link - Check for link (Copper) ++ * e1000e_check_for_copper_link - Check for link (Copper) + * @hw: pointer to the HW structure + * + * Checks to see of the link status of the hardware has changed. If a + * change in link status has been detected, then we read the PHY registers + * to get the current speed/duplex if link exists. + **/ +-s32 e1000_check_for_copper_link(struct e1000_hw *hw) ++s32 e1000e_check_for_copper_link(struct e1000_hw *hw) + { + struct e1000_mac_info *mac = &hw->mac; + s32 ret_val; +@@ -387,7 +387,7 @@ s32 e1000_check_for_copper_link(struct e1000_hw *hw) + * link. If so, then we want to get the current speed/duplex + * of the PHY. + */ +- ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); ++ ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); + if (ret_val) + return ret_val; + +@@ -398,7 +398,7 @@ s32 e1000_check_for_copper_link(struct e1000_hw *hw) + + /* Check if there was DownShift, must be checked + * immediately after link-up */ +- e1000_check_downshift(hw); ++ e1000e_check_downshift(hw); + + /* If we are forcing speed/duplex, then we simply return since + * we have already determined whether we have link or not. +@@ -412,14 +412,14 @@ s32 e1000_check_for_copper_link(struct e1000_hw *hw) + * of MAC speed/duplex configuration. So we only need to + * configure Collision Distance in the MAC. + */ +- e1000_config_collision_dist(hw); ++ e1000e_config_collision_dist(hw); + + /* Configure Flow Control now that Auto-Neg has completed. + * First, we need to restore the desired flow control + * settings because we may have had to re-autoneg with a + * different link partner. + */ +- ret_val = e1000_config_fc_after_link_up(hw); ++ ret_val = e1000e_config_fc_after_link_up(hw); + if (ret_val) { + hw_dbg(hw, "Error configuring flow control\n"); + } +@@ -428,13 +428,13 @@ s32 e1000_check_for_copper_link(struct e1000_hw *hw) + } + + /** +- * e1000_check_for_fiber_link - Check for link (Fiber) ++ * e1000e_check_for_fiber_link - Check for link (Fiber) + * @hw: pointer to the HW structure + * + * Checks for link up on the hardware. If link is not up and we have + * a signal, then we need to force link up. + **/ +-s32 e1000_check_for_fiber_link(struct e1000_hw *hw) ++s32 e1000e_check_for_fiber_link(struct e1000_hw *hw) + { + struct e1000_mac_info *mac = &hw->mac; + u32 rxcw; +@@ -471,7 +471,7 @@ s32 e1000_check_for_fiber_link(struct e1000_hw *hw) + ew32(CTRL, ctrl); + + /* Configure Flow Control after forcing link up. */ +- ret_val = e1000_config_fc_after_link_up(hw); ++ ret_val = e1000e_config_fc_after_link_up(hw); + if (ret_val) { + hw_dbg(hw, "Error configuring flow control\n"); + return ret_val; +@@ -493,13 +493,13 @@ s32 e1000_check_for_fiber_link(struct e1000_hw *hw) + } + + /** +- * e1000_check_for_serdes_link - Check for link (Serdes) ++ * e1000e_check_for_serdes_link - Check for link (Serdes) + * @hw: pointer to the HW structure + * + * Checks for link up on the hardware. If link is not up and we have + * a signal, then we need to force link up. + **/ +-s32 e1000_check_for_serdes_link(struct e1000_hw *hw) ++s32 e1000e_check_for_serdes_link(struct e1000_hw *hw) + { + struct e1000_mac_info *mac = &hw->mac; + u32 rxcw; +@@ -534,7 +534,7 @@ s32 e1000_check_for_serdes_link(struct e1000_hw *hw) + ew32(CTRL, ctrl); + + /* Configure Flow Control after forcing link up. */ +- ret_val = e1000_config_fc_after_link_up(hw); ++ ret_val = e1000e_config_fc_after_link_up(hw); + if (ret_val) { + hw_dbg(hw, "Error configuring flow control\n"); + return ret_val; +@@ -619,7 +619,7 @@ static s32 e1000_set_default_fc_generic(struct e1000_hw *hw) + } + + /** +- * e1000_setup_link - Setup flow control and link settings ++ * e1000e_setup_link - Setup flow control and link settings + * @hw: pointer to the HW structure + * + * Determines which flow control settings to use, then configures flow +@@ -628,7 +628,7 @@ static s32 e1000_set_default_fc_generic(struct e1000_hw *hw) + * should be established. Assumes the hardware has previously been reset + * and the transmitter and receiver are not enabled. + **/ +-s32 e1000_setup_link(struct e1000_hw *hw) ++s32 e1000e_setup_link(struct e1000_hw *hw) + { + struct e1000_mac_info *mac = &hw->mac; + s32 ret_val; +@@ -668,7 +668,7 @@ s32 e1000_setup_link(struct e1000_hw *hw) + + ew32(FCTTV, mac->fc_pause_time); + +- return e1000_set_fc_watermarks(hw); ++ return e1000e_set_fc_watermarks(hw); + } + + /** +@@ -786,13 +786,13 @@ static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) + } + + /** +- * e1000_setup_fiber_serdes_link - Setup link for fiber/serdes ++ * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes + * @hw: pointer to the HW structure + * + * Configures collision distance and flow control for fiber and serdes + * links. Upon successful setup, poll for link. + **/ +-s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw) ++s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw) + { + u32 ctrl; + s32 ret_val; +@@ -802,7 +802,7 @@ s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw) + /* Take the link out of reset */ + ctrl &= ~E1000_CTRL_LRST; + +- e1000_config_collision_dist(hw); ++ e1000e_config_collision_dist(hw); + + ret_val = e1000_commit_fc_settings_generic(hw); + if (ret_val) +@@ -835,14 +835,14 @@ s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw) + } + + /** +- * e1000_config_collision_dist - Configure collision distance ++ * e1000e_config_collision_dist - Configure collision distance + * @hw: pointer to the HW structure + * + * Configures the collision distance to the default value and is used + * during link setup. Currently no func pointer exists and all + * implementations are handled in the generic version of this function. + **/ +-void e1000_config_collision_dist(struct e1000_hw *hw) ++void e1000e_config_collision_dist(struct e1000_hw *hw) + { + u32 tctl; + +@@ -856,14 +856,14 @@ void e1000_config_collision_dist(struct e1000_hw *hw) + } + + /** +- * e1000_set_fc_watermarks - Set flow control high/low watermarks ++ * e1000e_set_fc_watermarks - Set flow control high/low watermarks + * @hw: pointer to the HW structure + * + * Sets the flow control high/low threshold (watermark) registers. If + * flow control XON frame transmission is enabled, then set XON frame + * tansmission as well. + **/ +-s32 e1000_set_fc_watermarks(struct e1000_hw *hw) ++s32 e1000e_set_fc_watermarks(struct e1000_hw *hw) + { + struct e1000_mac_info *mac = &hw->mac; + u32 fcrtl = 0, fcrth = 0; +@@ -890,7 +890,7 @@ s32 e1000_set_fc_watermarks(struct e1000_hw *hw) + } + + /** +- * e1000_force_mac_fc - Force the MAC's flow control settings ++ * e1000e_force_mac_fc - Force the MAC's flow control settings + * @hw: pointer to the HW structure + * + * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the +@@ -899,7 +899,7 @@ s32 e1000_set_fc_watermarks(struct e1000_hw *hw) + * autonegotiation is managed by the PHY rather than the MAC. Software must + * also configure these bits when link is forced on a fiber connection. + **/ +-s32 e1000_force_mac_fc(struct e1000_hw *hw) ++s32 e1000e_force_mac_fc(struct e1000_hw *hw) + { + struct e1000_mac_info *mac = &hw->mac; + u32 ctrl; +@@ -951,7 +951,7 @@ s32 e1000_force_mac_fc(struct e1000_hw *hw) + } + + /** +- * e1000_config_fc_after_link_up - Configures flow control after link ++ * e1000e_config_fc_after_link_up - Configures flow control after link + * @hw: pointer to the HW structure + * + * Checks the status of auto-negotiation after link up to ensure that the +@@ -960,7 +960,7 @@ s32 e1000_force_mac_fc(struct e1000_hw *hw) + * and did not fail, then we configure flow control based on our link + * partner. + **/ +-s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) ++s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw) + { + struct e1000_mac_info *mac = &hw->mac; + s32 ret_val = 0; +@@ -974,10 +974,10 @@ s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) + if (mac->autoneg_failed) { + if (hw->media_type == e1000_media_type_fiber || + hw->media_type == e1000_media_type_internal_serdes) +- ret_val = e1000_force_mac_fc(hw); ++ ret_val = e1000e_force_mac_fc(hw); + } else { + if (hw->media_type == e1000_media_type_copper) +- ret_val = e1000_force_mac_fc(hw); ++ ret_val = e1000e_force_mac_fc(hw); + } + + if (ret_val) { +@@ -1147,7 +1147,7 @@ s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) + /* Now we call a subroutine to actually force the MAC + * controller to use the correct flow control settings. + */ +- ret_val = e1000_force_mac_fc(hw); ++ ret_val = e1000e_force_mac_fc(hw); + if (ret_val) { + hw_dbg(hw, "Error forcing flow control settings\n"); + return ret_val; +@@ -1158,7 +1158,7 @@ s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) + } + + /** +- * e1000_get_speed_and_duplex_copper - Retreive current speed/duplex ++ * e1000e_get_speed_and_duplex_copper - Retreive current speed/duplex + * @hw: pointer to the HW structure + * @speed: stores the current speed + * @duplex: stores the current duplex +@@ -1166,7 +1166,7 @@ s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) + * Read the status register for the current speed/duplex and store the current + * speed and duplex for copper connections. + **/ +-s32 e1000_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex) ++s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex) + { + u32 status; + +@@ -1194,7 +1194,7 @@ s32 e1000_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *dupl + } + + /** +- * e1000_get_speed_and_duplex_fiber_serdes - Retreive current speed/duplex ++ * e1000e_get_speed_and_duplex_fiber_serdes - Retreive current speed/duplex + * @hw: pointer to the HW structure + * @speed: stores the current speed + * @duplex: stores the current duplex +@@ -1202,7 +1202,7 @@ s32 e1000_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *dupl + * Sets the speed and duplex to gigabit full duplex (the only possible option) + * for fiber/serdes links. + **/ +-s32 e1000_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex) ++s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex) + { + *speed = SPEED_1000; + *duplex = FULL_DUPLEX; +@@ -1211,12 +1211,12 @@ s32 e1000_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 + } + + /** +- * e1000_get_hw_semaphore - Acquire hardware semaphore ++ * e1000e_get_hw_semaphore - Acquire hardware semaphore + * @hw: pointer to the HW structure + * + * Acquire the HW semaphore to access the PHY or NVM + **/ +-s32 e1000_get_hw_semaphore(struct e1000_hw *hw) ++s32 e1000e_get_hw_semaphore(struct e1000_hw *hw) + { + u32 swsm; + s32 timeout = hw->nvm.word_size + 1; +@@ -1251,7 +1251,7 @@ s32 e1000_get_hw_semaphore(struct e1000_hw *hw) + + if (i == timeout) { + /* Release semaphores */ +- e1000_put_hw_semaphore(hw); ++ e1000e_put_hw_semaphore(hw); + hw_dbg(hw, "Driver can't access the NVM\n"); + return -E1000_ERR_NVM; + } +@@ -1260,12 +1260,12 @@ s32 e1000_get_hw_semaphore(struct e1000_hw *hw) + } + + /** +- * e1000_put_hw_semaphore - Release hardware semaphore ++ * e1000e_put_hw_semaphore - Release hardware semaphore + * @hw: pointer to the HW structure + * + * Release hardware semaphore used to access the PHY or NVM + **/ +-void e1000_put_hw_semaphore(struct e1000_hw *hw) ++void e1000e_put_hw_semaphore(struct e1000_hw *hw) + { + u32 swsm; + +@@ -1275,12 +1275,12 @@ void e1000_put_hw_semaphore(struct e1000_hw *hw) + } + + /** +- * e1000_get_auto_rd_done - Check for auto read completion ++ * e1000e_get_auto_rd_done - Check for auto read completion + * @hw: pointer to the HW structure + * + * Check EEPROM for Auto Read done bit. + **/ +-s32 e1000_get_auto_rd_done(struct e1000_hw *hw) ++s32 e1000e_get_auto_rd_done(struct e1000_hw *hw) + { + s32 i = 0; + +@@ -1300,14 +1300,14 @@ s32 e1000_get_auto_rd_done(struct e1000_hw *hw) + } + + /** +- * e1000_valid_led_default - Verify a valid default LED config ++ * e1000e_valid_led_default - Verify a valid default LED config + * @hw: pointer to the HW structure + * @data: pointer to the NVM (EEPROM) + * + * Read the EEPROM for the current default LED configuration. If the + * LED configuration is not valid, set to a valid LED configuration. + **/ +-s32 e1000_valid_led_default(struct e1000_hw *hw, u16 *data) ++s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data) + { + s32 ret_val; + +@@ -1324,11 +1324,11 @@ s32 e1000_valid_led_default(struct e1000_hw *hw, u16 *data) + } + + /** +- * e1000_id_led_init - ++ * e1000e_id_led_init - + * @hw: pointer to the HW structure + * + **/ +-s32 e1000_id_led_init(struct e1000_hw *hw) ++s32 e1000e_id_led_init(struct e1000_hw *hw) + { + struct e1000_mac_info *mac = &hw->mac; + s32 ret_val; +@@ -1388,25 +1388,25 @@ s32 e1000_id_led_init(struct e1000_hw *hw) + } + + /** +- * e1000_cleanup_led_generic - Set LED config to default operation ++ * e1000e_cleanup_led_generic - Set LED config to default operation + * @hw: pointer to the HW structure + * + * Remove the current LED configuration and set the LED configuration + * to the default value, saved from the EEPROM. + **/ +-s32 e1000_cleanup_led_generic(struct e1000_hw *hw) ++s32 e1000e_cleanup_led_generic(struct e1000_hw *hw) + { + ew32(LEDCTL, hw->mac.ledctl_default); + return 0; + } + + /** +- * e1000_blink_led - Blink LED ++ * e1000e_blink_led - Blink LED + * @hw: pointer to the HW structure + * + * Blink the led's which are set to be on. + **/ +-s32 e1000_blink_led(struct e1000_hw *hw) ++s32 e1000e_blink_led(struct e1000_hw *hw) + { + u32 ledctl_blink = 0; + u32 i; +@@ -1432,12 +1432,12 @@ s32 e1000_blink_led(struct e1000_hw *hw) + } + + /** +- * e1000_led_on_generic - Turn LED on ++ * e1000e_led_on_generic - Turn LED on + * @hw: pointer to the HW structure + * + * Turn LED on. + **/ +-s32 e1000_led_on_generic(struct e1000_hw *hw) ++s32 e1000e_led_on_generic(struct e1000_hw *hw) + { + u32 ctrl; + +@@ -1459,12 +1459,12 @@ s32 e1000_led_on_generic(struct e1000_hw *hw) + } + + /** +- * e1000_led_off_generic - Turn LED off ++ * e1000e_led_off_generic - Turn LED off + * @hw: pointer to the HW structure + * + * Turn LED off. + **/ +-s32 e1000_led_off_generic(struct e1000_hw *hw) ++s32 e1000e_led_off_generic(struct e1000_hw *hw) + { + u32 ctrl; + +@@ -1486,13 +1486,13 @@ s32 e1000_led_off_generic(struct e1000_hw *hw) + } + + /** +- * e1000_set_pcie_no_snoop - Set PCI-express capabilities ++ * e1000e_set_pcie_no_snoop - Set PCI-express capabilities + * @hw: pointer to the HW structure + * @no_snoop: bitmap of snoop events + * + * Set the PCI-express register to snoop for events enabled in 'no_snoop'. + **/ +-void e1000_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop) ++void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop) + { + u32 gcr; + +@@ -1505,7 +1505,7 @@ void e1000_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop) + } + + /** +- * e1000_disable_pcie_master - Disables PCI-express master access ++ * e1000e_disable_pcie_master - Disables PCI-express master access + * @hw: pointer to the HW structure + * + * Returns 0 if successful, else returns -10 +@@ -1515,7 +1515,7 @@ void e1000_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop) + * Disables PCI-Express master access and verifies there are no pending + * requests. + **/ +-s32 e1000_disable_pcie_master(struct e1000_hw *hw) ++s32 e1000e_disable_pcie_master(struct e1000_hw *hw) + { + u32 ctrl; + s32 timeout = MASTER_DISABLE_TIMEOUT; +@@ -1541,12 +1541,12 @@ s32 e1000_disable_pcie_master(struct e1000_hw *hw) + } + + /** +- * e1000_reset_adaptive - Reset Adaptive Interframe Spacing ++ * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing + * @hw: pointer to the HW structure + * + * Reset the Adaptive Interframe Spacing throttle to default values. + **/ +-void e1000_reset_adaptive(struct e1000_hw *hw) ++void e1000e_reset_adaptive(struct e1000_hw *hw) + { + struct e1000_mac_info *mac = &hw->mac; + +@@ -1561,13 +1561,13 @@ void e1000_reset_adaptive(struct e1000_hw *hw) + } + + /** +- * e1000_update_adaptive - Update Adaptive Interframe Spacing ++ * e1000e_update_adaptive - Update Adaptive Interframe Spacing + * @hw: pointer to the HW structure + * + * Update the Adaptive Interframe Spacing Throttle value based on the + * time between transmitted packets and time between collisions. + **/ +-void e1000_update_adaptive(struct e1000_hw *hw) ++void e1000e_update_adaptive(struct e1000_hw *hw) + { + struct e1000_mac_info *mac = &hw->mac; + +@@ -1704,14 +1704,14 @@ static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count) + } + + /** +- * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion ++ * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion + * @hw: pointer to the HW structure + * @ee_reg: EEPROM flag for polling + * + * Polls the EEPROM status bit for either read or write completion based + * upon the value of 'ee_reg'. + **/ +-s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) ++s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) + { + u32 attempts = 100000; + u32 i, reg = 0; +@@ -1732,14 +1732,14 @@ s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) + } + + /** +- * e1000_acquire_nvm - Generic request for access to EEPROM ++ * e1000e_acquire_nvm - Generic request for access to EEPROM + * @hw: pointer to the HW structure + * + * Set the EEPROM access request bit and wait for EEPROM access grant bit. + * Return successful if access grant bit set, else clear the request for + * EEPROM access and return -E1000_ERR_NVM (-1). + **/ +-s32 e1000_acquire_nvm(struct e1000_hw *hw) ++s32 e1000e_acquire_nvm(struct e1000_hw *hw) + { + u32 eecd = er32(EECD); + s32 timeout = E1000_NVM_GRANT_ATTEMPTS; +@@ -1808,12 +1808,12 @@ static void e1000_stop_nvm(struct e1000_hw *hw) + } + + /** +- * e1000_release_nvm - Release exclusive access to EEPROM ++ * e1000e_release_nvm - Release exclusive access to EEPROM + * @hw: pointer to the HW structure + * + * Stop any current commands to the EEPROM and clear the EEPROM request bit. + **/ +-void e1000_release_nvm(struct e1000_hw *hw) ++void e1000e_release_nvm(struct e1000_hw *hw) + { + u32 eecd; + +@@ -1870,7 +1870,7 @@ static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) + } + + /** +- * e1000_read_nvm_spi - Read EEPROM's using SPI ++ * e1000e_read_nvm_spi - Read EEPROM's using SPI + * @hw: pointer to the HW structure + * @offset: offset of word in the EEPROM to read + * @words: number of words to read +@@ -1878,7 +1878,7 @@ static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) + * + * Reads a 16 bit word from the EEPROM. + **/ +-s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) ++s32 e1000e_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) + { + struct e1000_nvm_info *nvm = &hw->nvm; + u32 i = 0; +@@ -1926,7 +1926,7 @@ s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) + } + + /** +- * e1000_read_nvm_eerd - Reads EEPROM using EERD register ++ * e1000e_read_nvm_eerd - Reads EEPROM using EERD register + * @hw: pointer to the HW structure + * @offset: offset of word in the EEPROM to read + * @words: number of words to read +@@ -1934,7 +1934,7 @@ s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) + * + * Reads a 16 bit word from the EEPROM using the EERD register. + **/ +-s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) ++s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) + { + struct e1000_nvm_info *nvm = &hw->nvm; + u32 i, eerd = 0; +@@ -1953,7 +1953,7 @@ s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) + E1000_NVM_RW_REG_START; + + ew32(EERD, eerd); +- ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); ++ ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); + if (ret_val) + break; + +@@ -1965,7 +1965,7 @@ s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) + } + + /** +- * e1000_write_nvm_spi - Write to EEPROM using SPI ++ * e1000e_write_nvm_spi - Write to EEPROM using SPI + * @hw: pointer to the HW structure + * @offset: offset within the EEPROM to be written to + * @words: number of words to write +@@ -1973,10 +1973,10 @@ s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) + * + * Writes data to EEPROM at offset using SPI interface. + * +- * If e1000_update_nvm_checksum is not called after this function , the ++ * If e1000e_update_nvm_checksum is not called after this function , the + * EEPROM will most likley contain an invalid checksum. + **/ +-s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) ++s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) + { + struct e1000_nvm_info *nvm = &hw->nvm; + s32 ret_val; +@@ -2042,14 +2042,14 @@ s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) + } + + /** +- * e1000_read_mac_addr - Read device MAC address ++ * e1000e_read_mac_addr - Read device MAC address + * @hw: pointer to the HW structure + * + * Reads the device MAC address from the EEPROM and stores the value. + * Since devices with two ports use the same EEPROM, we increment the + * last bit in the MAC address for the second port. + **/ +-s32 e1000_read_mac_addr(struct e1000_hw *hw) ++s32 e1000e_read_mac_addr(struct e1000_hw *hw) + { + s32 ret_val; + u16 offset, nvm_data, i; +@@ -2076,13 +2076,13 @@ s32 e1000_read_mac_addr(struct e1000_hw *hw) + } + + /** +- * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum ++ * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum + * @hw: pointer to the HW structure + * + * Calculates the EEPROM checksum by reading/adding each word of the EEPROM + * and then verifies that the sum of the EEPROM is equal to 0xBABA. + **/ +-s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw) ++s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw) + { + s32 ret_val; + u16 checksum = 0; +@@ -2106,14 +2106,14 @@ s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw) + } + + /** +- * e1000_update_nvm_checksum_generic - Update EEPROM checksum ++ * e1000e_update_nvm_checksum_generic - Update EEPROM checksum + * @hw: pointer to the HW structure + * + * Updates the EEPROM checksum by reading/adding each word of the EEPROM + * up to the checksum. Then calculates the EEPROM checksum and writes the + * value to the EEPROM. + **/ +-s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw) ++s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw) + { + s32 ret_val; + u16 checksum = 0; +@@ -2136,13 +2136,13 @@ s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw) + } + + /** +- * e1000_reload_nvm - Reloads EEPROM ++ * e1000e_reload_nvm - Reloads EEPROM + * @hw: pointer to the HW structure + * + * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the + * extended control register. + **/ +-void e1000_reload_nvm(struct e1000_hw *hw) ++void e1000e_reload_nvm(struct e1000_hw *hw) + { + u32 ctrl_ext; + +@@ -2213,13 +2213,13 @@ static s32 e1000_mng_enable_host_if(struct e1000_hw *hw) + } + + /** +- * e1000_check_mng_mode - check managament mode ++ * e1000e_check_mng_mode - check managament mode + * @hw: pointer to the HW structure + * + * Reads the firmware semaphore register and returns true (>0) if + * manageability is enabled, else false (0). + **/ +-bool e1000_check_mng_mode(struct e1000_hw *hw) ++bool e1000e_check_mng_mode(struct e1000_hw *hw) + { + u32 fwsm = er32(FWSM); + +@@ -2227,13 +2227,13 @@ bool e1000_check_mng_mode(struct e1000_hw *hw) + } + + /** +- * e1000_enable_tx_pkt_filtering - Enable packet filtering on TX ++ * e1000e_enable_tx_pkt_filtering - Enable packet filtering on TX + * @hw: pointer to the HW structure + * + * Enables packet filtering on transmit packets if manageability is enabled + * and host interface is enabled. + **/ +-bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) ++bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw) + { + struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie; + u32 *buffer = (u32 *)&hw->mng_cookie; +@@ -2242,7 +2242,7 @@ bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) + u8 i, len; + + /* No manageability, no filtering */ +- if (!e1000_check_mng_mode(hw)) { ++ if (!e1000e_check_mng_mode(hw)) { + hw->mac.tx_pkt_filtering = 0; + return 0; + } +@@ -2383,14 +2383,14 @@ static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, + } + + /** +- * e1000_mng_write_dhcp_info - Writes DHCP info to host interface ++ * e1000e_mng_write_dhcp_info - Writes DHCP info to host interface + * @hw: pointer to the HW structure + * @buffer: pointer to the host interface + * @length: size of the buffer + * + * Writes the DHCP information to the host interface. + **/ +-s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length) ++s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length) + { + struct e1000_host_mng_command_header hdr; + s32 ret_val; +@@ -2426,12 +2426,12 @@ s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length) + } + + /** +- * e1000_enable_mng_pass_thru - Enable processing of ARP's ++ * e1000e_enable_mng_pass_thru - Enable processing of ARP's + * @hw: pointer to the HW structure + * + * Verifies the hardware needs to allow ARPs to be processed by the host. + **/ +-bool e1000_enable_mng_pass_thru(struct e1000_hw *hw) ++bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw) + { + u32 manc; + u32 fwsm, factps; +diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c +index 01a9a4f..d711e14 100644 +--- a/drivers/net/e1000e/netdev.c ++++ b/drivers/net/e1000e/netdev.c +@@ -47,8 +47,8 @@ + #include "e1000.h" + + #define DRV_VERSION "0.2.0" +-char e1000_driver_name[] = "e1000e"; +-const char e1000_driver_version[] = DRV_VERSION; ++char e1000e_driver_name[] = "e1000e"; ++const char e1000e_driver_version[] = DRV_VERSION; + + static const struct e1000_info *e1000_info_tbl[] = { + [board_82571] = &e1000_82571_info, +@@ -64,7 +64,7 @@ static const struct e1000_info *e1000_info_tbl[] = { + * e1000_get_hw_dev_name - return device name string + * used by hardware layer to print debugging information + **/ +-char *e1000_get_hw_dev_name(struct e1000_hw *hw) ++char *e1000e_get_hw_dev_name(struct e1000_hw *hw) + { + struct e1000_adapter *adapter = hw->back; + struct net_device *netdev = adapter->netdev; +@@ -1108,7 +1108,7 @@ static irqreturn_t e1000_intr_msi(int irq, void *data) + * disconnect (LSC) before accessing any PHY registers */ + if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && + (!(er32(STATUS) & E1000_STATUS_LU))) +- e1000_gig_downshift_workaround_ich8lan(hw); ++ e1000e_gig_downshift_workaround_ich8lan(hw); + + /* 80003ES2LAN workaround-- For packet buffer work-around on + * link down event; disable receives here in the ISR and reset +@@ -1169,7 +1169,7 @@ static irqreturn_t e1000_intr(int irq, void *data) + * disconnect (LSC) before accessing any PHY registers */ + if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && + (!(er32(STATUS) & E1000_STATUS_LU))) +- e1000_gig_downshift_workaround_ich8lan(hw); ++ e1000e_gig_downshift_workaround_ich8lan(hw); + + /* 80003ES2LAN workaround-- + * For packet buffer work-around on link down event; +@@ -1352,12 +1352,12 @@ static int e1000_alloc_ring_dma(struct e1000_adapter *adapter, + } + + /** +- * e1000_setup_tx_resources - allocate Tx resources (Descriptors) ++ * e1000e_setup_tx_resources - allocate Tx resources (Descriptors) + * @adapter: board private structure + * + * Return 0 on success, negative on failure + **/ +-int e1000_setup_tx_resources(struct e1000_adapter *adapter) ++int e1000e_setup_tx_resources(struct e1000_adapter *adapter) + { + struct e1000_ring *tx_ring = adapter->tx_ring; + int err = -ENOMEM, size; +@@ -1389,12 +1389,12 @@ err: + } + + /** +- * e1000_setup_rx_resources - allocate Rx resources (Descriptors) ++ * e1000e_setup_rx_resources - allocate Rx resources (Descriptors) + * @adapter: board private structure + * + * Returns 0 on success, negative on failure + **/ +-int e1000_setup_rx_resources(struct e1000_adapter *adapter) ++int e1000e_setup_rx_resources(struct e1000_adapter *adapter) + { + struct e1000_ring *rx_ring = adapter->rx_ring; + int size, desc_len, err = -ENOMEM; +@@ -1464,12 +1464,12 @@ static void e1000_clean_tx_ring(struct e1000_adapter *adapter) + } + + /** +- * e1000_free_tx_resources - Free Tx Resources per Queue ++ * e1000e_free_tx_resources - Free Tx Resources per Queue + * @adapter: board private structure + * + * Free all transmit software resources + **/ +-void e1000_free_tx_resources(struct e1000_adapter *adapter) ++void e1000e_free_tx_resources(struct e1000_adapter *adapter) + { + struct pci_dev *pdev = adapter->pdev; + struct e1000_ring *tx_ring = adapter->tx_ring; +@@ -1484,13 +1484,13 @@ void e1000_free_tx_resources(struct e1000_adapter *adapter) + } + + /** +- * e1000_free_rx_resources - Free Rx Resources ++ * e1000e_free_rx_resources - Free Rx Resources + * @adapter: board private structure + * + * Free all receive software resources + **/ + +-void e1000_free_rx_resources(struct e1000_adapter *adapter) ++void e1000e_free_rx_resources(struct e1000_adapter *adapter) + { + struct pci_dev *pdev = adapter->pdev; + struct e1000_ring *rx_ring = adapter->rx_ring; +@@ -1693,7 +1693,7 @@ static void e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid) + index = (vid >> 5) & 0x7F; + vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); + vfta |= (1 << (vid & 0x1F)); +- e1000_write_vfta(hw, index, vfta); ++ e1000e_write_vfta(hw, index, vfta); + } + + static void e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) +@@ -1718,7 +1718,7 @@ static void e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) + index = (vid >> 5) & 0x7F; + vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); + vfta &= ~(1 << (vid & 0x1F)); +- e1000_write_vfta(hw, index, vfta); ++ e1000e_write_vfta(hw, index, vfta); + } + + static void e1000_update_mng_vlan(struct e1000_adapter *adapter) +@@ -1904,7 +1904,7 @@ static void e1000_configure_tx(struct e1000_adapter *adapter) + ew32(TARC1, tarc); + } + +- e1000_config_collision_dist(hw); ++ e1000e_config_collision_dist(hw); + + /* Setup Transmit Descriptor Settings for eop descriptor */ + adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; +@@ -2237,14 +2237,14 @@ static void e1000_configure(struct e1000_adapter *adapter) + } + + /** +- * e1000_power_up_phy - restore link in case the phy was powered down ++ * e1000e_power_up_phy - restore link in case the phy was powered down + * @adapter: address of board private structure + * + * The phy may be powered down to save power and turn off link when the + * driver is unloaded and wake on lan is not enabled (among others) +- * *** this routine MUST be followed by a call to e1000_reset *** ++ * *** this routine MUST be followed by a call to e1000e_reset *** + **/ +-void e1000_power_up_phy(struct e1000_adapter *adapter) ++void e1000e_power_up_phy(struct e1000_adapter *adapter) + { + u16 mii_reg = 0; + +@@ -2280,7 +2280,7 @@ static void e1000_power_down_phy(struct e1000_adapter *adapter) + return; + + /* reset is blocked because of a SoL/IDER session */ +- if (e1000_check_mng_mode(hw) || ++ if (e1000e_check_mng_mode(hw) || + e1000_check_reset_block(hw)) + return; + +@@ -2296,14 +2296,14 @@ static void e1000_power_down_phy(struct e1000_adapter *adapter) + } + + /** +- * e1000_reset - bring the hardware into a known good state ++ * e1000e_reset - bring the hardware into a known good state + * + * This function boots the hardware and enables some settings that + * require a configuration cycle of the hardware - those cannot be + * set/changed during runtime. After reset the device needs to be + * properly configured for rx, tx etc. + */ +-void e1000_reset(struct e1000_adapter *adapter) ++void e1000e_reset(struct e1000_adapter *adapter) + { + struct e1000_mac_info *mac = &adapter->hw.mac; + struct e1000_hw *hw = &adapter->hw; +@@ -2388,7 +2388,7 @@ void e1000_reset(struct e1000_adapter *adapter) + /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ + ew32(VET, ETH_P_8021Q); + +- e1000_reset_adaptive(hw); ++ e1000e_reset_adaptive(hw); + e1000_get_phy_info(hw); + + if (!(adapter->flags & FLAG_SMART_POWER_DOWN)) { +@@ -2404,7 +2404,7 @@ void e1000_reset(struct e1000_adapter *adapter) + e1000_release_manageability(adapter); + } + +-int e1000_up(struct e1000_adapter *adapter) ++int e1000e_up(struct e1000_adapter *adapter) + { + struct e1000_hw *hw = &adapter->hw; + +@@ -2421,7 +2421,7 @@ int e1000_up(struct e1000_adapter *adapter) + return 0; + } + +-void e1000_down(struct e1000_adapter *adapter) ++void e1000e_down(struct e1000_adapter *adapter) + { + struct net_device *netdev = adapter->netdev; + struct e1000_hw *hw = &adapter->hw; +@@ -2457,7 +2457,7 @@ void e1000_down(struct e1000_adapter *adapter) + adapter->link_speed = 0; + adapter->link_duplex = 0; + +- e1000_reset(adapter); ++ e1000e_reset(adapter); + e1000_clean_tx_ring(adapter); + e1000_clean_rx_ring(adapter); + +@@ -2467,13 +2467,13 @@ void e1000_down(struct e1000_adapter *adapter) + */ + } + +-void e1000_reinit_locked(struct e1000_adapter *adapter) ++void e1000e_reinit_locked(struct e1000_adapter *adapter) + { + might_sleep(); + while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) + msleep(1); +- e1000_down(adapter); +- e1000_up(adapter); ++ e1000e_down(adapter); ++ e1000e_up(adapter); + clear_bit(__E1000_RESETTING, &adapter->state); + } + +@@ -2544,16 +2544,16 @@ static int e1000_open(struct net_device *netdev) + return -EBUSY; + + /* allocate transmit descriptors */ +- err = e1000_setup_tx_resources(adapter); ++ err = e1000e_setup_tx_resources(adapter); + if (err) + goto err_setup_tx; + + /* allocate receive descriptors */ +- err = e1000_setup_rx_resources(adapter); ++ err = e1000e_setup_rx_resources(adapter); + if (err) + goto err_setup_rx; + +- e1000_power_up_phy(adapter); ++ e1000e_power_up_phy(adapter); + + adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; + if ((adapter->hw.mng_cookie.status & +@@ -2563,7 +2563,7 @@ static int e1000_open(struct net_device *netdev) + /* If AMT is enabled, let the firmware know that the network + * interface is now open */ + if ((adapter->flags & FLAG_HAS_AMT) && +- e1000_check_mng_mode(&adapter->hw)) ++ e1000e_check_mng_mode(&adapter->hw)) + e1000_get_hw_control(adapter); + + /* before we allocate an interrupt, we must be ready to handle it. +@@ -2576,7 +2576,7 @@ static int e1000_open(struct net_device *netdev) + if (err) + goto err_req_irq; + +- /* From here on the code is the same as e1000_up() */ ++ /* From here on the code is the same as e1000e_up() */ + clear_bit(__E1000_DOWN, &adapter->state); + + netif_poll_enable(netdev); +@@ -2591,11 +2591,11 @@ static int e1000_open(struct net_device *netdev) + err_req_irq: + e1000_release_hw_control(adapter); + e1000_power_down_phy(adapter); +- e1000_free_rx_resources(adapter); ++ e1000e_free_rx_resources(adapter); + err_setup_rx: +- e1000_free_tx_resources(adapter); ++ e1000e_free_tx_resources(adapter); + err_setup_tx: +- e1000_reset(adapter); ++ e1000e_reset(adapter); + + return err; + } +@@ -2616,12 +2616,12 @@ static int e1000_close(struct net_device *netdev) + struct e1000_adapter *adapter = netdev_priv(netdev); + + WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); +- e1000_down(adapter); ++ e1000e_down(adapter); + e1000_power_down_phy(adapter); + e1000_free_irq(adapter); + +- e1000_free_tx_resources(adapter); +- e1000_free_rx_resources(adapter); ++ e1000e_free_tx_resources(adapter); ++ e1000e_free_rx_resources(adapter); + + /* kill manageability vlan ID if supported, but not if a vlan with + * the same ID is registered on the host OS (let 8021q kill it) */ +@@ -2634,7 +2634,7 @@ static int e1000_close(struct net_device *netdev) + /* If AMT is enabled, let the firmware know that the network + * interface is now closed */ + if ((adapter->flags & FLAG_HAS_AMT) && +- e1000_check_mng_mode(&adapter->hw)) ++ e1000e_check_mng_mode(&adapter->hw)) + e1000_release_hw_control(adapter); + + return 0; +@@ -2657,11 +2657,11 @@ static int e1000_set_mac(struct net_device *netdev, void *p) + memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); + memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len); + +- e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); ++ e1000e_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); + + if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) { + /* activate the work around */ +- e1000_set_laa_state_82571(&adapter->hw, 1); ++ e1000e_set_laa_state_82571(&adapter->hw, 1); + + /* Hold a copy of the LAA in RAR[14] This is done so that + * between the time RAR[0] gets clobbered and the time it +@@ -2669,7 +2669,7 @@ static int e1000_set_mac(struct net_device *netdev, void *p) + * of the RARs and no incoming packets directed to this port + * are dropped. Eventually the LAA will be in RAR[0] and + * RAR[14] */ +- e1000_rar_set(&adapter->hw, ++ e1000e_rar_set(&adapter->hw, + adapter->hw.mac.addr, + adapter->hw.mac.rar_entry_count - 1); + } +@@ -2686,10 +2686,10 @@ static void e1000_update_phy_info(unsigned long data) + } + + /** +- * e1000_update_stats - Update the board statistics counters ++ * e1000e_update_stats - Update the board statistics counters + * @adapter: board private structure + **/ +-void e1000_update_stats(struct e1000_adapter *adapter) ++void e1000e_update_stats(struct e1000_adapter *adapter) + { + struct e1000_hw *hw = &adapter->hw; + struct pci_dev *pdev = adapter->pdev; +@@ -2903,7 +2903,7 @@ static void e1000_watchdog_task(struct work_struct *work) + "Gigabit has been disabled, downgrading speed\n"); + } + +- if ((e1000_enable_tx_pkt_filtering(hw)) && ++ if ((e1000e_enable_tx_pkt_filtering(hw)) && + (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)) + e1000_update_mng_vlan(adapter); + +@@ -3005,7 +3005,7 @@ static void e1000_watchdog_task(struct work_struct *work) + } + + link_up: +- e1000_update_stats(adapter); ++ e1000e_update_stats(adapter); + + mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; + adapter->tpt_old = adapter->stats.tpt; +@@ -3017,7 +3017,7 @@ link_up: + adapter->gotcl = adapter->stats.gotcl - adapter->gotcl_old; + adapter->gotcl_old = adapter->stats.gotcl; + +- e1000_update_adaptive(&adapter->hw); ++ e1000e_update_adaptive(&adapter->hw); + + if (!netif_carrier_ok(netdev)) { + tx_pending = (e1000_desc_unused(tx_ring) + 1 < +@@ -3040,8 +3040,8 @@ link_up: + + /* With 82571 controllers, LAA may be overwritten due to controller + * reset from the other port. Set the appropriate LAA in RAR[0] */ +- if (e1000_get_laa_state_82571(hw)) +- e1000_rar_set(hw, adapter->hw.mac.addr, 0); ++ if (e1000e_get_laa_state_82571(hw)) ++ e1000e_rar_set(hw, adapter->hw.mac.addr, 0); + + /* Reset the timer */ + if (!test_bit(__E1000_DOWN, &adapter->state)) +@@ -3358,7 +3358,7 @@ static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter, + + offset = (u8 *)udp + 8 - skb->data; + length = skb->len - offset; +- return e1000_mng_write_dhcp_info(hw, (u8 *)udp + 8, length); ++ return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length); + } + + return 0; +@@ -3540,7 +3540,7 @@ static void e1000_reset_task(struct work_struct *work) + struct e1000_adapter *adapter; + adapter = container_of(work, struct e1000_adapter, reset_task); + +- e1000_reinit_locked(adapter); ++ e1000e_reinit_locked(adapter); + } + + /** +@@ -3596,10 +3596,10 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu) + + while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) + msleep(1); +- /* e1000_down has a dependency on max_frame_size */ ++ /* e1000e_down has a dependency on max_frame_size */ + adapter->hw.mac.max_frame_size = max_frame; + if (netif_running(netdev)) +- e1000_down(adapter); ++ e1000e_down(adapter); + + /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN + * means we reserve 2 more, this pushes us to allocate from the next +@@ -3630,9 +3630,9 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu) + netdev->mtu = new_mtu; + + if (netif_running(netdev)) +- e1000_up(adapter); ++ e1000e_up(adapter); + else +- e1000_reset(adapter); ++ e1000e_reset(adapter); + + clear_bit(__E1000_RESETTING, &adapter->state); + +@@ -3696,7 +3696,7 @@ static int e1000_suspend(struct pci_dev *pdev, pm_message_t state) + + if (netif_running(netdev)) { + WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); +- e1000_down(adapter); ++ e1000e_down(adapter); + e1000_free_irq(adapter); + } + +@@ -3737,7 +3737,7 @@ static int e1000_suspend(struct pci_dev *pdev, pm_message_t state) + } + + /* Allow time for pending master requests to run */ +- e1000_disable_pcie_master(&adapter->hw); ++ e1000e_disable_pcie_master(&adapter->hw); + + ew32(WUC, E1000_WUC_PME_EN); + ew32(WUFC, wufc); +@@ -3759,7 +3759,7 @@ static int e1000_suspend(struct pci_dev *pdev, pm_message_t state) + } + + if (adapter->hw.phy.type == e1000_phy_igp_3) +- e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); ++ e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); + + /* Release control of h/w to f/w. If f/w is AMT enabled, this + * would have already happened in close and is redundant. */ +@@ -3800,21 +3800,21 @@ static int e1000_resume(struct pci_dev *pdev) + return err; + } + +- e1000_power_up_phy(adapter); +- e1000_reset(adapter); ++ e1000e_power_up_phy(adapter); ++ e1000e_reset(adapter); + ew32(WUS, ~0); + + e1000_init_manageability(adapter); + + if (netif_running(netdev)) +- e1000_up(adapter); ++ e1000e_up(adapter); + + netif_device_attach(netdev); + + /* If the controller has AMT, do not set DRV_LOAD until the interface + * is up. For all other cases, let the f/w know that the h/w is now + * under the control of the driver. */ +- if (!(adapter->flags & FLAG_HAS_AMT) || !e1000_check_mng_mode(&adapter->hw)) ++ if (!(adapter->flags & FLAG_HAS_AMT) || !e1000e_check_mng_mode(&adapter->hw)) + e1000_get_hw_control(adapter); + + return 0; +@@ -3862,7 +3862,7 @@ static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, + netif_device_detach(netdev); + + if (netif_running(netdev)) +- e1000_down(adapter); ++ e1000e_down(adapter); + pci_disable_device(pdev); + + /* Request a slot slot reset. */ +@@ -3892,7 +3892,7 @@ static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev) + pci_enable_wake(pdev, PCI_D3hot, 0); + pci_enable_wake(pdev, PCI_D3cold, 0); + +- e1000_reset(adapter); ++ e1000e_reset(adapter); + ew32(WUS, ~0); + + return PCI_ERS_RESULT_RECOVERED; +@@ -3914,7 +3914,7 @@ static void e1000_io_resume(struct pci_dev *pdev) + e1000_init_manageability(adapter); + + if (netif_running(netdev)) { +- if (e1000_up(adapter)) { ++ if (e1000e_up(adapter)) { + dev_err(&pdev->dev, + "can't bring device back up after reset\n"); + return; +@@ -3927,7 +3927,7 @@ static void e1000_io_resume(struct pci_dev *pdev) + * is up. For all other cases, let the f/w know that the h/w is now + * under the control of the driver. */ + if (!(adapter->flags & FLAG_HAS_AMT) || +- !e1000_check_mng_mode(&adapter->hw)) ++ !e1000e_check_mng_mode(&adapter->hw)) + e1000_get_hw_control(adapter); + + } +@@ -4001,7 +4001,7 @@ static int __devinit e1000_probe(struct pci_dev *pdev, + } + } + +- err = pci_request_regions(pdev, e1000_driver_name); ++ err = pci_request_regions(pdev, e1000e_driver_name); + if (err) + goto err_pci_reg; + +@@ -4053,7 +4053,7 @@ static int __devinit e1000_probe(struct pci_dev *pdev, + netdev->set_mac_address = &e1000_set_mac; + netdev->change_mtu = &e1000_change_mtu; + netdev->do_ioctl = &e1000_ioctl; +- e1000_set_ethtool_ops(netdev); ++ e1000e_set_ethtool_ops(netdev); + netdev->tx_timeout = &e1000_tx_timeout; + netdev->watchdog_timeo = 5 * HZ; + netdev->poll = &e1000_clean; +@@ -4119,7 +4119,7 @@ static int __devinit e1000_probe(struct pci_dev *pdev, + * it. */ + netdev->features |= NETIF_F_LLTX; + +- if (e1000_enable_mng_pass_thru(&adapter->hw)) ++ if (e1000e_enable_mng_pass_thru(&adapter->hw)) + adapter->flags |= FLAG_MNG_PT_ENABLED; + + /* before reading the NVM, reset the controller to +@@ -4141,7 +4141,7 @@ static int __devinit e1000_probe(struct pci_dev *pdev, + } + + /* copy the MAC address out of the NVM */ +- if (e1000_read_mac_addr(&adapter->hw)) ++ if (e1000e_read_mac_addr(&adapter->hw)) + ndev_err(netdev, "NVM Read Error while reading MAC address\n"); + + memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len); +@@ -4168,7 +4168,7 @@ static int __devinit e1000_probe(struct pci_dev *pdev, + INIT_WORK(&adapter->reset_task, e1000_reset_task); + INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task); + +- e1000_check_options(adapter); ++ e1000e_check_options(adapter); + + /* Initialize link parameters. User can change them with ethtool */ + adapter->hw.mac.autoneg = 1; +@@ -4214,13 +4214,13 @@ static int __devinit e1000_probe(struct pci_dev *pdev, + adapter->wol = adapter->eeprom_wol; + + /* reset the hardware with the new settings */ +- e1000_reset(adapter); ++ e1000e_reset(adapter); + + /* If the controller has AMT, do not set DRV_LOAD until the interface + * is up. For all other cases, let the f/w know that the h/w is now + * under the control of the driver. */ + if (!(adapter->flags & FLAG_HAS_AMT) || +- !e1000_check_mng_mode(&adapter->hw)) ++ !e1000e_check_mng_mode(&adapter->hw)) + e1000_get_hw_control(adapter); + + /* tell the stack to leave us alone until e1000_open() is called */ +@@ -4315,7 +4315,7 @@ static struct pci_error_handlers e1000_err_handler = { + .resume = e1000_io_resume, + }; + +-static struct pci_device_id e1000e_pci_tbl[] = { ++static struct pci_device_id e1000_pci_tbl[] = { + /* + * Support for 82571/2/3, es2lan and ich8 will be phased in + * stepwise. +@@ -4358,12 +4358,12 @@ static struct pci_device_id e1000e_pci_tbl[] = { + + { } /* terminate list */ + }; +-MODULE_DEVICE_TABLE(pci, e1000e_pci_tbl); ++MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); + + /* PCI Device API Driver */ + static struct pci_driver e1000_driver = { +- .name = e1000_driver_name, +- .id_table = e1000e_pci_tbl, ++ .name = e1000e_driver_name, ++ .id_table = e1000_pci_tbl, + .probe = e1000_probe, + .remove = __devexit_p(e1000_remove), + #ifdef CONFIG_PM +@@ -4381,17 +4381,17 @@ static struct pci_driver e1000_driver = { + * e1000_init_module is the first routine called when the driver is + * loaded. All it does is register with the PCI subsystem. + **/ +-static int __init e1000e_init_module(void) ++static int __init e1000_init_module(void) + { + int ret; + printk(KERN_INFO "Intel(R) PRO/1000 Network Driver - %s\n", +- e1000_driver_version); ++ e1000e_driver_version); + printk(KERN_INFO "Copyright (c) 1999-2007 Intel Corporation.\n"); + ret = pci_register_driver(&e1000_driver); + + return ret; + } +-module_init(e1000e_init_module); ++module_init(e1000_init_module); + + /** + * e1000_exit_module - Driver Exit Cleanup Routine +@@ -4399,11 +4399,11 @@ module_init(e1000e_init_module); + * e1000_exit_module is called just before the driver is removed + * from memory. + **/ +-static void __exit e1000e_exit_module(void) ++static void __exit e1000_exit_module(void) + { + pci_unregister_driver(&e1000_driver); + } +-module_exit(e1000e_exit_module); ++module_exit(e1000_exit_module); + + + MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); +diff --git a/drivers/net/e1000e/param.c b/drivers/net/e1000e/param.c +index 9a70d22..e4e655e 100644 +--- a/drivers/net/e1000e/param.c ++++ b/drivers/net/e1000e/param.c +@@ -192,7 +192,7 @@ static int __devinit e1000_validate_option(int *value, + } + + /** +- * e1000_check_options - Range Checking for Command Line Parameters ++ * e1000e_check_options - Range Checking for Command Line Parameters + * @adapter: board private structure + * + * This routine checks all command line parameters for valid user +@@ -200,7 +200,7 @@ static int __devinit e1000_validate_option(int *value, + * value exists, a default value is used. The final value is stored + * in a variable in the adapter structure. + **/ +-void __devinit e1000_check_options(struct e1000_adapter *adapter) ++void __devinit e1000e_check_options(struct e1000_adapter *adapter) + { + struct e1000_hw *hw = &adapter->hw; + struct net_device *netdev = adapter->netdev; +@@ -371,11 +371,11 @@ void __devinit e1000_check_options(struct e1000_adapter *adapter) + int kmrn_lock_loss = KumeranLockLoss[bd]; + e1000_validate_option(&kmrn_lock_loss, &opt, adapter); + if (hw->mac.type == e1000_ich8lan) +- e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, ++ e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, + kmrn_lock_loss); + } else { + if (hw->mac.type == e1000_ich8lan) +- e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, ++ e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, + opt.def); + } + } +diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c +index c9304d8..1efb47a 100644 +--- a/drivers/net/e1000e/phy.c ++++ b/drivers/net/e1000e/phy.c +@@ -53,14 +53,14 @@ static const u16 e1000_igp_2_cable_length_table[] = + sizeof(e1000_igp_2_cable_length_table[0])) + + /** +- * e1000_check_reset_block_generic - Check if PHY reset is blocked ++ * e1000e_check_reset_block_generic - Check if PHY reset is blocked + * @hw: pointer to the HW structure + * + * Read the PHY management control register and check whether a PHY reset + * is blocked. If a reset is not blocked return 0, otherwise + * return E1000_BLK_PHY_RESET (12). + **/ +-s32 e1000_check_reset_block_generic(struct e1000_hw *hw) ++s32 e1000e_check_reset_block_generic(struct e1000_hw *hw) + { + u32 manc; + +@@ -71,13 +71,13 @@ s32 e1000_check_reset_block_generic(struct e1000_hw *hw) + } + + /** +- * e1000_get_phy_id - Retrieve the PHY ID and revision ++ * e1000e_get_phy_id - Retrieve the PHY ID and revision + * @hw: pointer to the HW structure + * + * Reads the PHY registers and stores the PHY ID and possibly the PHY + * revision in the hardware structure. + **/ +-s32 e1000_get_phy_id(struct e1000_hw *hw) ++s32 e1000e_get_phy_id(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; +@@ -100,12 +100,12 @@ s32 e1000_get_phy_id(struct e1000_hw *hw) + } + + /** +- * e1000_phy_reset_dsp - Reset PHY DSP ++ * e1000e_phy_reset_dsp - Reset PHY DSP + * @hw: pointer to the HW structure + * + * Reset the digital signal processor. + **/ +-s32 e1000_phy_reset_dsp(struct e1000_hw *hw) ++s32 e1000e_phy_reset_dsp(struct e1000_hw *hw) + { + s32 ret_val; + +@@ -210,7 +210,7 @@ static s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) + } + + /** +- * e1000_read_phy_reg_m88 - Read m88 PHY register ++ * e1000e_read_phy_reg_m88 - Read m88 PHY register + * @hw: pointer to the HW structure + * @offset: register offset to be read + * @data: pointer to the read data +@@ -219,7 +219,7 @@ static s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) + * and storing the retrieved information in data. Release any acquired + * semaphores before exiting. + **/ +-s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) ++s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) + { + s32 ret_val; + +@@ -237,7 +237,7 @@ s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) + } + + /** +- * e1000_write_phy_reg_m88 - Write m88 PHY register ++ * e1000e_write_phy_reg_m88 - Write m88 PHY register + * @hw: pointer to the HW structure + * @offset: register offset to write to + * @data: data to write at register offset +@@ -245,7 +245,7 @@ s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) + * Acquires semaphore, if necessary, then writes the data to PHY register + * at the offset. Release any acquired semaphores before exiting. + **/ +-s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) ++s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) + { + s32 ret_val; + +@@ -263,7 +263,7 @@ s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) + } + + /** +- * e1000_read_phy_reg_igp - Read igp PHY register ++ * e1000e_read_phy_reg_igp - Read igp PHY register + * @hw: pointer to the HW structure + * @offset: register offset to be read + * @data: pointer to the read data +@@ -272,7 +272,7 @@ s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) + * and storing the retrieved information in data. Release any acquired + * semaphores before exiting. + **/ +-s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) ++s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) + { + s32 ret_val; + +@@ -300,7 +300,7 @@ s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) + } + + /** +- * e1000_write_phy_reg_igp - Write igp PHY register ++ * e1000e_write_phy_reg_igp - Write igp PHY register + * @hw: pointer to the HW structure + * @offset: register offset to write to + * @data: data to write at register offset +@@ -308,7 +308,7 @@ s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) + * Acquires semaphore, if necessary, then writes the data to PHY register + * at the offset. Release any acquired semaphores before exiting. + **/ +-s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) ++s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) + { + s32 ret_val; + +@@ -336,7 +336,7 @@ s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) + } + + /** +- * e1000_read_kmrn_reg - Read kumeran register ++ * e1000e_read_kmrn_reg - Read kumeran register + * @hw: pointer to the HW structure + * @offset: register offset to be read + * @data: pointer to the read data +@@ -345,7 +345,7 @@ s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) + * using the kumeran interface. The information retrieved is stored in data. + * Release any acquired semaphores before exiting. + **/ +-s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) ++s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) + { + u32 kmrnctrlsta; + s32 ret_val; +@@ -369,7 +369,7 @@ s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) + } + + /** +- * e1000_write_kmrn_reg - Write kumeran register ++ * e1000e_write_kmrn_reg - Write kumeran register + * @hw: pointer to the HW structure + * @offset: register offset to write to + * @data: data to write at register offset +@@ -378,7 +378,7 @@ s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) + * at the offset using the kumeran interface. Release any acquired semaphores + * before exiting. + **/ +-s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) ++s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) + { + u32 kmrnctrlsta; + s32 ret_val; +@@ -398,13 +398,13 @@ s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) + } + + /** +- * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link ++ * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link + * @hw: pointer to the HW structure + * + * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock + * and downshift values are set also. + **/ +-s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) ++s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; +@@ -484,7 +484,7 @@ s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) + } + + /* Commit the changes. */ +- ret_val = e1000_commit_phy(hw); ++ ret_val = e1000e_commit_phy(hw); + if (ret_val) + hw_dbg(hw, "Error committing the PHY changes\n"); + +@@ -492,13 +492,13 @@ s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) + } + + /** +- * e1000_copper_link_setup_igp - Setup igp PHY's for copper link ++ * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link + * @hw: pointer to the HW structure + * + * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for + * igp PHY's. + **/ +-s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) ++s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; +@@ -715,7 +715,7 @@ static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) + /* Since there really isn't a way to advertise that we are + * capable of RX Pause ONLY, we will advertise that we + * support both symmetric and asymmetric RX PAUSE. Later +- * (in e1000_config_fc_after_link_up) we will disable the ++ * (in e1000e_config_fc_after_link_up) we will disable the + * hw's ability to send PAUSE frames. + */ + mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); +@@ -816,7 +816,7 @@ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) + } + + /** +- * e1000_setup_copper_link - Configure copper link settings ++ * e1000e_setup_copper_link - Configure copper link settings + * @hw: pointer to the HW structure + * + * Calls the appropriate function to configure the link for auto-neg or forced +@@ -824,7 +824,7 @@ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) + * to configure collision distance and flow control are called. If link is + * not established, we return -E1000_ERR_PHY (-2). + **/ +-s32 e1000_setup_copper_link(struct e1000_hw *hw) ++s32 e1000e_setup_copper_link(struct e1000_hw *hw) + { + s32 ret_val; + bool link; +@@ -849,7 +849,7 @@ s32 e1000_setup_copper_link(struct e1000_hw *hw) + /* Check link status. Wait up to 100 microseconds for link to become + * valid. + */ +- ret_val = e1000_phy_has_link_generic(hw, ++ ret_val = e1000e_phy_has_link_generic(hw, + COPPER_LINK_UP_LIMIT, + 10, + &link); +@@ -858,8 +858,8 @@ s32 e1000_setup_copper_link(struct e1000_hw *hw) + + if (link) { + hw_dbg(hw, "Valid link established!!!\n"); +- e1000_config_collision_dist(hw); +- ret_val = e1000_config_fc_after_link_up(hw); ++ e1000e_config_collision_dist(hw); ++ ret_val = e1000e_config_fc_after_link_up(hw); + } else { + hw_dbg(hw, "Unable to establish link!!!\n"); + } +@@ -868,14 +868,14 @@ s32 e1000_setup_copper_link(struct e1000_hw *hw) + } + + /** +- * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY ++ * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY + * @hw: pointer to the HW structure + * + * Calls the PHY setup function to force speed and duplex. Clears the + * auto-crossover to force MDI manually. Waits for link and returns + * successful if link up is successful, else -E1000_ERR_PHY (-2). + **/ +-s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) ++s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; +@@ -886,7 +886,7 @@ s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) + if (ret_val) + return ret_val; + +- e1000_phy_force_speed_duplex_setup(hw, &phy_data); ++ e1000e_phy_force_speed_duplex_setup(hw, &phy_data); + + ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); + if (ret_val) +@@ -913,7 +913,7 @@ s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) + if (phy->wait_for_link) { + hw_dbg(hw, "Waiting for forced speed/duplex link on IGP phy.\n"); + +- ret_val = e1000_phy_has_link_generic(hw, ++ ret_val = e1000e_phy_has_link_generic(hw, + PHY_FORCE_LIMIT, + 100000, + &link); +@@ -924,7 +924,7 @@ s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) + hw_dbg(hw, "Link taking longer than expected.\n"); + + /* Try once more */ +- ret_val = e1000_phy_has_link_generic(hw, ++ ret_val = e1000e_phy_has_link_generic(hw, + PHY_FORCE_LIMIT, + 100000, + &link); +@@ -936,7 +936,7 @@ s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) + } + + /** +- * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY ++ * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY + * @hw: pointer to the HW structure + * + * Calls the PHY setup function to force speed and duplex. Clears the +@@ -945,7 +945,7 @@ s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) + * After reset, TX_CLK and CRS on TX must be set. Return successful upon + * successful completion, else return corresponding error code. + **/ +-s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) ++s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; +@@ -970,7 +970,7 @@ s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) + if (ret_val) + return ret_val; + +- e1000_phy_force_speed_duplex_setup(hw, &phy_data); ++ e1000e_phy_force_speed_duplex_setup(hw, &phy_data); + + /* Reset the phy to commit changes. */ + phy_data |= MII_CR_RESET; +@@ -984,7 +984,7 @@ s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) + if (phy->wait_for_link) { + hw_dbg(hw, "Waiting for forced speed/duplex link on M88 phy.\n"); + +- ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, ++ ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, + 100000, &link); + if (ret_val) + return ret_val; +@@ -996,13 +996,13 @@ s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) + ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT, 0x001d); + if (ret_val) + return ret_val; +- ret_val = e1000_phy_reset_dsp(hw); ++ ret_val = e1000e_phy_reset_dsp(hw); + if (ret_val) + return ret_val; + } + + /* Try once more */ +- ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, ++ ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, + 100000, &link); + if (ret_val) + return ret_val; +@@ -1035,7 +1035,7 @@ s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) + } + + /** +- * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex ++ * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex + * @hw: pointer to the HW structure + * @phy_ctrl: pointer to current value of PHY_CONTROL + * +@@ -1046,7 +1046,7 @@ s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) + * caller must write to the PHY_CONTROL register for these settings to + * take affect. + **/ +-void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) ++void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) + { + struct e1000_mac_info *mac = &hw->mac; + u32 ctrl; +@@ -1089,13 +1089,13 @@ void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) + hw_dbg(hw, "Forcing 10mb\n"); + } + +- e1000_config_collision_dist(hw); ++ e1000e_config_collision_dist(hw); + + ew32(CTRL, ctrl); + } + + /** +- * e1000_set_d3_lplu_state - Sets low power link up state for D3 ++ * e1000e_set_d3_lplu_state - Sets low power link up state for D3 + * @hw: pointer to the HW structure + * @active: boolean used to enable/disable lplu + * +@@ -1108,7 +1108,7 @@ void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) + * During driver activity, SmartSpeed should be enabled so performance is + * maintained. + **/ +-s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) ++s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; +@@ -1173,14 +1173,14 @@ s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) + } + + /** +- * e1000_check_downshift - Checks whether a downshift in speed occured ++ * e1000e_check_downshift - Checks whether a downshift in speed occured + * @hw: pointer to the HW structure + * + * Success returns 0, Failure returns 1 + * + * A downshift is detected by querying the PHY link health. + **/ +-s32 e1000_check_downshift(struct e1000_hw *hw) ++s32 e1000e_check_downshift(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; +@@ -1310,7 +1310,7 @@ static s32 e1000_wait_autoneg(struct e1000_hw *hw) + } + + /** +- * e1000_phy_has_link_generic - Polls PHY for link ++ * e1000e_phy_has_link_generic - Polls PHY for link + * @hw: pointer to the HW structure + * @iterations: number of times to poll for link + * @usec_interval: delay between polling attempts +@@ -1318,7 +1318,7 @@ static s32 e1000_wait_autoneg(struct e1000_hw *hw) + * + * Polls the PHY status register for link, 'iterations' number of times. + **/ +-s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, ++s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, + u32 usec_interval, bool *success) + { + s32 ret_val; +@@ -1349,7 +1349,7 @@ s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, + } + + /** +- * e1000_get_cable_length_m88 - Determine cable length for m88 PHY ++ * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY + * @hw: pointer to the HW structure + * + * Reads the PHY specific status register to retrieve the cable length +@@ -1363,7 +1363,7 @@ s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, + * 3 110 - 140 meters + * 4 > 140 meters + **/ +-s32 e1000_get_cable_length_m88(struct e1000_hw *hw) ++s32 e1000e_get_cable_length_m88(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; +@@ -1384,7 +1384,7 @@ s32 e1000_get_cable_length_m88(struct e1000_hw *hw) + } + + /** +- * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY ++ * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY + * @hw: pointer to the HW structure + * + * The automatic gain control (agc) normalizes the amplitude of the +@@ -1394,7 +1394,7 @@ s32 e1000_get_cable_length_m88(struct e1000_hw *hw) + * into a lookup table to obtain the approximate cable length + * for each channel. + **/ +-s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw) ++s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; +@@ -1451,7 +1451,7 @@ s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw) + } + + /** +- * e1000_get_phy_info_m88 - Retrieve PHY information ++ * e1000e_get_phy_info_m88 - Retrieve PHY information + * @hw: pointer to the HW structure + * + * Valid for only copper links. Read the PHY status register (sticky read) +@@ -1460,7 +1460,7 @@ s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw) + * special status register to determine MDI/MDIx and current speed. If + * speed is 1000, then determine cable length, local and remote receiver. + **/ +-s32 e1000_get_phy_info_m88(struct e1000_hw *hw) ++s32 e1000e_get_phy_info_m88(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; +@@ -1472,7 +1472,7 @@ s32 e1000_get_phy_info_m88(struct e1000_hw *hw) + return -E1000_ERR_CONFIG; + } + +- ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); ++ ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); + if (ret_val) + return ret_val; + +@@ -1525,7 +1525,7 @@ s32 e1000_get_phy_info_m88(struct e1000_hw *hw) + } + + /** +- * e1000_get_phy_info_igp - Retrieve igp PHY information ++ * e1000e_get_phy_info_igp - Retrieve igp PHY information + * @hw: pointer to the HW structure + * + * Read PHY status to determine if link is up. If link is up, then +@@ -1533,14 +1533,14 @@ s32 e1000_get_phy_info_m88(struct e1000_hw *hw) + * PHY port status to determine MDI/MDIx and speed. Based on the speed, + * determine on the cable length, local and remote receiver. + **/ +-s32 e1000_get_phy_info_igp(struct e1000_hw *hw) ++s32 e1000e_get_phy_info_igp(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; + u16 data; + bool link; + +- ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); ++ ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); + if (ret_val) + return ret_val; + +@@ -1588,13 +1588,13 @@ s32 e1000_get_phy_info_igp(struct e1000_hw *hw) + } + + /** +- * e1000_phy_sw_reset - PHY software reset ++ * e1000e_phy_sw_reset - PHY software reset + * @hw: pointer to the HW structure + * + * Does a software reset of the PHY by reading the PHY control register and + * setting/write the control register reset bit to the PHY. + **/ +-s32 e1000_phy_sw_reset(struct e1000_hw *hw) ++s32 e1000e_phy_sw_reset(struct e1000_hw *hw) + { + s32 ret_val; + u16 phy_ctrl; +@@ -1614,7 +1614,7 @@ s32 e1000_phy_sw_reset(struct e1000_hw *hw) + } + + /** +- * e1000_phy_hw_reset_generic - PHY hardware reset ++ * e1000e_phy_hw_reset_generic - PHY hardware reset + * @hw: pointer to the HW structure + * + * Verify the reset block is not blocking us from resetting. Acquire +@@ -1622,7 +1622,7 @@ s32 e1000_phy_sw_reset(struct e1000_hw *hw) + * bit in the PHY. Wait the appropriate delay time for the device to + * reset and relase the semaphore (if necessary). + **/ +-s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw) ++s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw) + { + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val; +@@ -1653,13 +1653,13 @@ s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw) + } + + /** +- * e1000_get_cfg_done - Generic configuration done ++ * e1000e_get_cfg_done - Generic configuration done + * @hw: pointer to the HW structure + * + * Generic function to wait 10 milli-seconds for configuration to complete + * and return success. + **/ +-s32 e1000_get_cfg_done(struct e1000_hw *hw) ++s32 e1000e_get_cfg_done(struct e1000_hw *hw) + { + mdelay(10); + return 0; +@@ -1698,12 +1698,12 @@ static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) + } + + /** +- * e1000_get_phy_type_from_id - Get PHY type from id ++ * e1000e_get_phy_type_from_id - Get PHY type from id + * @phy_id: phy_id read from the phy + * + * Returns the phy type from the id. + **/ +-enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id) ++enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id) + { + enum e1000_phy_type phy_type = e1000_phy_unknown; + +@@ -1736,13 +1736,13 @@ enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id) + } + + /** +- * e1000_commit_phy - Soft PHY reset ++ * e1000e_commit_phy - Soft PHY reset + * @hw: pointer to the HW structure + * + * Performs a soft PHY reset on those that apply. This is a function pointer + * entry point called by drivers. + **/ +-s32 e1000_commit_phy(struct e1000_hw *hw) ++s32 e1000e_commit_phy(struct e1000_hw *hw) + { + if (hw->phy.ops.commit_phy) + return hw->phy.ops.commit_phy(hw); diff --git a/trunk/2.6.21/21356_linux-2.6-netdev-e1000e-07.patch b/trunk/2.6.21/21356_linux-2.6-netdev-e1000e-07.patch new file mode 100644 index 0000000..496df79 --- /dev/null +++ b/trunk/2.6.21/21356_linux-2.6-netdev-e1000e-07.patch @@ -0,0 +1,93 @@ +From: Auke Kok <auke-jan.h.kok@intel.com> +Date: Fri, 10 Aug 2007 20:00:52 +0000 (-0700) +Subject: e1000e: Use dma_alloc_coherent where possible +X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fjgarzik%2Fnetdev-2.6.git;a=commitdiff_plain;h=5c0904d729b2161ab7559c5683832cb075c8e81d + +e1000e: Use dma_alloc_coherent where possible + +Instead of using pci_alloc_consistent at GFP_ATOMIC we can be +more reliable at startup and use dma_alloc_coherent instead with +GFP_KERNEL. + +Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> +Signed-off-by: Jeff Garzik <jeff@garzik.org> +--- + +diff --git a/drivers/net/e1000e/ethtool.c b/drivers/net/e1000e/ethtool.c +index c9d74a8..d184116 100644 +--- a/drivers/net/e1000e/ethtool.c ++++ b/drivers/net/e1000e/ethtool.c +@@ -962,13 +962,13 @@ static void e1000_free_desc_rings(struct e1000_adapter *adapter) + } + + if (tx_ring->desc) { +- pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, +- tx_ring->dma); ++ dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc, ++ tx_ring->dma); + tx_ring->desc = NULL; + } + if (rx_ring->desc) { +- pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, +- rx_ring->dma); ++ dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc, ++ rx_ring->dma); + rx_ring->desc = NULL; + } + +@@ -1004,8 +1004,8 @@ static int e1000_setup_desc_rings(struct e1000_adapter *adapter) + + tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); + tx_ring->size = ALIGN(tx_ring->size, 4096); +- tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, +- &tx_ring->dma); ++ tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size, ++ &tx_ring->dma, GFP_KERNEL); + if (!tx_ring->desc) { + ret_val = 2; + goto err_nomem; +@@ -1065,8 +1065,8 @@ static int e1000_setup_desc_rings(struct e1000_adapter *adapter) + memset(rx_ring->buffer_info, 0, size); + + rx_ring->size = rx_ring->count * sizeof(struct e1000_rx_desc); +- rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, +- &rx_ring->dma); ++ rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size, ++ &rx_ring->dma, GFP_KERNEL); + if (!rx_ring->desc) { + ret_val = 5; + goto err_nomem; +diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c +index d711e14..51c9024 100644 +--- a/drivers/net/e1000e/netdev.c ++++ b/drivers/net/e1000e/netdev.c +@@ -1344,7 +1344,8 @@ static int e1000_alloc_ring_dma(struct e1000_adapter *adapter, + { + struct pci_dev *pdev = adapter->pdev; + +- ring->desc = pci_alloc_consistent(pdev, ring->size, &ring->dma); ++ ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma, ++ GFP_KERNEL); + if (!ring->desc) + return -ENOMEM; + +@@ -1479,7 +1480,8 @@ void e1000e_free_tx_resources(struct e1000_adapter *adapter) + vfree(tx_ring->buffer_info); + tx_ring->buffer_info = NULL; + +- pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma); ++ dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc, ++ tx_ring->dma); + tx_ring->desc = NULL; + } + +@@ -1503,7 +1505,8 @@ void e1000e_free_rx_resources(struct e1000_adapter *adapter) + kfree(rx_ring->ps_pages); + rx_ring->ps_pages = NULL; + +- pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); ++ dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc, ++ rx_ring->dma); + rx_ring->desc = NULL; + } + diff --git a/trunk/2.6.21/21357_linux-2.6-netdev-e1000e-08.patch b/trunk/2.6.21/21357_linux-2.6-netdev-e1000e-08.patch new file mode 100644 index 0000000..22e748e --- /dev/null +++ b/trunk/2.6.21/21357_linux-2.6-netdev-e1000e-08.patch @@ -0,0 +1,24 @@ +From: Auke Kok <auke-jan.h.kok@intel.com> +Date: Fri, 10 Aug 2007 20:00:57 +0000 (-0700) +Subject: e1000e: Use time_after to account for jiffies wrapping +X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fjgarzik%2Fnetdev-2.6.git;a=commitdiff_plain;h=363baa32cd1993c241cf16c862ec958fcaebe77e + +e1000e: Use time_after to account for jiffies wrapping + +Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> +Signed-off-by: Jeff Garzik <jeff@garzik.org> +--- + +diff --git a/drivers/net/e1000e/ethtool.c b/drivers/net/e1000e/ethtool.c +index d184116..d14cc4b 100644 +--- a/drivers/net/e1000e/ethtool.c ++++ b/drivers/net/e1000e/ethtool.c +@@ -1411,7 +1411,7 @@ static int e1000_run_loopback_test(struct e1000_adapter *adapter) + * enough time to complete the receives, if it's + * exceeded, break and error off + */ +- } while (good_cnt < 64 && jiffies < (time + 20)); ++ } while ((good_cnt < 64) && !time_after(jiffies, time + 20)); + if (good_cnt != 64) { + ret_val = 13; /* ret_val is the same as mis-compare */ + break; diff --git a/trunk/2.6.21/21358_linux-2.6-netdev-e1000e-09.patch b/trunk/2.6.21/21358_linux-2.6-netdev-e1000e-09.patch new file mode 100644 index 0000000..44a8726 --- /dev/null +++ b/trunk/2.6.21/21358_linux-2.6-netdev-e1000e-09.patch @@ -0,0 +1,197 @@ +From: Auke Kok <auke-jan.h.kok@intel.com> +Date: Fri, 10 Aug 2007 20:01:02 +0000 (-0700) +Subject: e1000e: error handling for pci_map_single calls. +X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fjgarzik%2Fnetdev-2.6.git;a=commitdiff_plain;h=8136b0db9be68942380cac6925cf6dd6a2be9a8f + +e1000e: error handling for pci_map_single calls. + +Add proper error handling for various callers of pci_map_single. + +Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> +Signed-off-by: Jeff Garzik <jeff@garzik.org> +--- + +diff --git a/drivers/net/e1000e/e1000.h b/drivers/net/e1000e/e1000.h +index 3475e48..e3cd877 100644 +--- a/drivers/net/e1000e/e1000.h ++++ b/drivers/net/e1000e/e1000.h +@@ -220,6 +220,7 @@ struct e1000_adapter { + u32 tx_fifo_head; + u32 tx_head_addr; + u32 tx_fifo_size; ++ u32 tx_dma_failed; + + /* + * RX +@@ -241,6 +242,7 @@ struct e1000_adapter { + u64 gorcl_old; + u32 gorcl; + u32 alloc_rx_buff_failed; ++ u32 rx_dma_failed; + + unsigned int rx_ps_pages; + u16 rx_ps_bsize0; +diff --git a/drivers/net/e1000e/ethtool.c b/drivers/net/e1000e/ethtool.c +index d14cc4b..0e80406 100644 +--- a/drivers/net/e1000e/ethtool.c ++++ b/drivers/net/e1000e/ethtool.c +@@ -91,6 +91,8 @@ static const struct e1000_stats e1000_gstrings_stats[] = { + { "tx_smbus", E1000_STAT(stats.mgptc) }, + { "rx_smbus", E1000_STAT(stats.mgprc) }, + { "dropped_smbus", E1000_STAT(stats.mgpdc) }, ++ { "rx_dma_failed", E1000_STAT(rx_dma_failed) }, ++ { "tx_dma_failed", E1000_STAT(tx_dma_failed) }, + }; + + #define E1000_GLOBAL_STATS_LEN \ +@@ -1042,6 +1044,10 @@ static int e1000_setup_desc_rings(struct e1000_adapter *adapter) + tx_ring->buffer_info[i].dma = + pci_map_single(pdev, skb->data, skb->len, + PCI_DMA_TODEVICE); ++ if (pci_dma_mapping_error(tx_ring->buffer_info[i].dma)) { ++ ret_val = 4; ++ goto err_nomem; ++ } + tx_desc->buffer_addr = cpu_to_le64( + tx_ring->buffer_info[i].dma); + tx_desc->lower.data = cpu_to_le32(skb->len); +@@ -1059,7 +1065,7 @@ static int e1000_setup_desc_rings(struct e1000_adapter *adapter) + size = rx_ring->count * sizeof(struct e1000_buffer); + rx_ring->buffer_info = kmalloc(size, GFP_KERNEL); + if (!rx_ring->buffer_info) { +- ret_val = 4; ++ ret_val = 5; + goto err_nomem; + } + memset(rx_ring->buffer_info, 0, size); +@@ -1068,7 +1074,7 @@ static int e1000_setup_desc_rings(struct e1000_adapter *adapter) + rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size, + &rx_ring->dma, GFP_KERNEL); + if (!rx_ring->desc) { +- ret_val = 5; ++ ret_val = 6; + goto err_nomem; + } + memset(rx_ring->desc, 0, rx_ring->size); +@@ -1093,7 +1099,7 @@ static int e1000_setup_desc_rings(struct e1000_adapter *adapter) + + skb = alloc_skb(2048 + NET_IP_ALIGN, GFP_KERNEL); + if (!skb) { +- ret_val = 6; ++ ret_val = 7; + goto err_nomem; + } + skb_reserve(skb, NET_IP_ALIGN); +@@ -1101,6 +1107,10 @@ static int e1000_setup_desc_rings(struct e1000_adapter *adapter) + rx_ring->buffer_info[i].dma = + pci_map_single(pdev, skb->data, 2048, + PCI_DMA_FROMDEVICE); ++ if (pci_dma_mapping_error(rx_ring->buffer_info[i].dma)) { ++ ret_val = 8; ++ goto err_nomem; ++ } + rx_desc->buffer_addr = + cpu_to_le64(rx_ring->buffer_info[i].dma); + memset(skb->data, 0x00, skb->len); +diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c +index 51c9024..8ebe238 100644 +--- a/drivers/net/e1000e/netdev.c ++++ b/drivers/net/e1000e/netdev.c +@@ -195,6 +195,11 @@ map_skb: + buffer_info->dma = pci_map_single(pdev, skb->data, + adapter->rx_buffer_len, + PCI_DMA_FROMDEVICE); ++ if (pci_dma_mapping_error(buffer_info->dma)) { ++ dev_err(&pdev->dev, "RX DMA map failed\n"); ++ adapter->rx_dma_failed++; ++ break; ++ } + + rx_desc = E1000_RX_DESC(*rx_ring, i); + rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); +@@ -255,6 +260,13 @@ static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter, + ps_page->page, + 0, PAGE_SIZE, + PCI_DMA_FROMDEVICE); ++ if (pci_dma_mapping_error( ++ ps_page->dma)) { ++ dev_err(&adapter->pdev->dev, ++ "RX DMA page map failed\n"); ++ adapter->rx_dma_failed++; ++ goto no_buffers; ++ } + } + /* + * Refresh the desc even if buffer_addrs +@@ -286,6 +298,14 @@ static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter, + buffer_info->dma = pci_map_single(pdev, skb->data, + adapter->rx_ps_bsize0, + PCI_DMA_FROMDEVICE); ++ if (pci_dma_mapping_error(buffer_info->dma)) { ++ dev_err(&pdev->dev, "RX DMA map failed\n"); ++ adapter->rx_dma_failed++; ++ /* cleanup skb */ ++ dev_kfree_skb_any(skb); ++ buffer_info->skb = NULL; ++ break; ++ } + + rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma); + +@@ -374,6 +394,11 @@ check_page: + buffer_info->page, 0, + PAGE_SIZE, + PCI_DMA_FROMDEVICE); ++ if (pci_dma_mapping_error(buffer_info->dma)) { ++ dev_err(&adapter->pdev->dev, "RX DMA page map failed\n"); ++ adapter->rx_dma_failed++; ++ break; ++ } + + rx_desc = E1000_RX_DESC(*rx_ring, i); + rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); +@@ -3214,6 +3239,11 @@ static int e1000_tx_map(struct e1000_adapter *adapter, + skb->data + offset, + size, + PCI_DMA_TODEVICE); ++ if (pci_dma_mapping_error(buffer_info->dma)) { ++ dev_err(&adapter->pdev->dev, "TX DMA map failed\n"); ++ adapter->tx_dma_failed++; ++ return -1; ++ } + buffer_info->next_to_watch = i; + + len -= size; +@@ -3247,6 +3277,13 @@ static int e1000_tx_map(struct e1000_adapter *adapter, + offset, + size, + PCI_DMA_TODEVICE); ++ if (pci_dma_mapping_error(buffer_info->dma)) { ++ dev_err(&adapter->pdev->dev, ++ "TX DMA page map failed\n"); ++ adapter->tx_dma_failed++; ++ return -1; ++ } ++ + buffer_info->next_to_watch = i; + + len -= size; +@@ -3512,9 +3549,15 @@ static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev) + if (skb->protocol == htons(ETH_P_IP)) + tx_flags |= E1000_TX_FLAGS_IPV4; + +- e1000_tx_queue(adapter, tx_flags, +- e1000_tx_map(adapter, skb, first, +- max_per_txd, nr_frags, mss)); ++ count = e1000_tx_map(adapter, skb, first, max_per_txd, nr_frags, mss); ++ if (count < 0) { ++ /* handle pci_map_single() error in e1000_tx_map */ ++ dev_kfree_skb_any(skb); ++ spin_unlock_irqrestore(&adapter->tx_queue_lock, irq_flags); ++ return NETDEV_TX_BUSY; ++ } ++ ++ e1000_tx_queue(adapter, tx_flags, count); + + netdev->trans_start = jiffies; + diff --git a/trunk/2.6.21/21359_linux-2.6-netdev-e1000e-10.patch b/trunk/2.6.21/21359_linux-2.6-netdev-e1000e-10.patch new file mode 100644 index 0000000..dffe619 --- /dev/null +++ b/trunk/2.6.21/21359_linux-2.6-netdev-e1000e-10.patch @@ -0,0 +1,46 @@ +From: Auke Kok <auke-jan.h.kok@intel.com> +Date: Fri, 10 Aug 2007 20:01:07 +0000 (-0700) +Subject: e1000e: Remove two compile warnings +X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fjgarzik%2Fnetdev-2.6.git;a=commitdiff_plain;h=3e4346712d03162af6b570aa17efb1201c4bf023 + +e1000e: Remove two compile warnings + +CC [M] drivers/net/e1000e/lib.o +drivers/net/e1000e/lib.c: In function 'e1000e_read_nvm_eerd': +drivers/net/e1000e/lib.c:1941: warning: 'ret_val' may be used uninitialized +in this function + CC [M] drivers/net/e1000e/phy.o +drivers/net/e1000e/phy.c: In function 'e1000e_phy_has_link_generic': +drivers/net/e1000e/phy.c:1324: warning: 'ret_val' may be used +uninitialized in this function + +Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> +Signed-off-by: Jeff Garzik <jeff@garzik.org> +--- + +diff --git a/drivers/net/e1000e/lib.c b/drivers/net/e1000e/lib.c +index a04c1e4..6645c21 100644 +--- a/drivers/net/e1000e/lib.c ++++ b/drivers/net/e1000e/lib.c +@@ -1938,7 +1938,7 @@ s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) + { + struct e1000_nvm_info *nvm = &hw->nvm; + u32 i, eerd = 0; +- s32 ret_val; ++ s32 ret_val = 0; + + /* A check for invalid values: offset too large, too many words, + * and not enough words. */ +diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c +index 1efb47a..7932318 100644 +--- a/drivers/net/e1000e/phy.c ++++ b/drivers/net/e1000e/phy.c +@@ -1321,7 +1321,7 @@ static s32 e1000_wait_autoneg(struct e1000_hw *hw) + s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, + u32 usec_interval, bool *success) + { +- s32 ret_val; ++ s32 ret_val = 0; + u16 i, phy_status; + + for (i = 0; i < iterations; i++) { diff --git a/trunk/2.6.21/21360_linux-2.6-netdev-e1000e-backport.patch b/trunk/2.6.21/21360_linux-2.6-netdev-e1000e-backport.patch new file mode 100644 index 0000000..d855438 --- /dev/null +++ b/trunk/2.6.21/21360_linux-2.6-netdev-e1000e-backport.patch @@ -0,0 +1,97 @@ +diff -up ./include/linux/if_ether.h.netdev-e1000e-backport ./include/linux/if_ether.h +--- ./include/linux/if_ether.h.netdev-e1000e-backport 2008-02-15 00:38:38.000000000 +0000 ++++ ./include/linux/if_ether.h 2008-02-15 01:34:08.000000000 +0000 +@@ -33,6 +33,7 @@ + #define ETH_ZLEN 60 /* Min. octets in frame sans FCS */ + #define ETH_DATA_LEN 1500 /* Max. octets in payload */ + #define ETH_FRAME_LEN 1514 /* Max. octets in frame sans FCS */ ++#define ETH_FCS_LEN 4 /* Octets in the FCS */ + + /* + * These are the defined Ethernet Protocol ID's. +diff -up ./drivers/net/e1000e/netdev.c.netdev-e1000e-backport ./drivers/net/e1000e/netdev.c +--- ./drivers/net/e1000e/netdev.c.netdev-e1000e-backport 2008-02-15 01:30:25.000000000 +0000 ++++ ./drivers/net/e1000e/netdev.c 2008-02-15 01:35:38.000000000 +0000 +@@ -806,7 +806,7 @@ static bool e1000_clean_rx_irq_jumbo(str + u8 *vaddr; + vaddr = kmap_atomic(buffer_info->page, + KM_SKB_DATA_SOFTIRQ); +- memcpy(skb_tail_pointer(skb), ++ memcpy(skb->tail, + vaddr, length); + kunmap_atomic(vaddr, + KM_SKB_DATA_SOFTIRQ); +@@ -963,7 +963,7 @@ static bool e1000_clean_rx_irq_ps(struct + pci_dma_sync_single_for_cpu(pdev, ps_page->dma, + PAGE_SIZE, PCI_DMA_FROMDEVICE); + vaddr = kmap_atomic(ps_page->page, KM_SKB_DATA_SOFTIRQ); +- memcpy(skb_tail_pointer(skb), vaddr, l1); ++ memcpy(skb->tail, vaddr, l1); + kunmap_atomic(vaddr, KM_SKB_DATA_SOFTIRQ); + pci_dma_sync_single_for_device(pdev, ps_page->dma, + PAGE_SIZE, PCI_DMA_FROMDEVICE); +@@ -3103,30 +3103,29 @@ static int e1000_tso(struct e1000_adapte + return err; + } + +- hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); ++ hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2)); + mss = skb_shinfo(skb)->gso_size; + if (skb->protocol == htons(ETH_P_IP)) { +- struct iphdr *iph = ip_hdr(skb); +- iph->tot_len = 0; +- iph->check = 0; +- tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, +- iph->daddr, 0, +- IPPROTO_TCP, +- 0); ++ skb->nh.iph->tot_len = 0; ++ skb->nh.iph->check = 0; ++ skb->h.th->check = ~csum_tcpudp_magic(skb->nh.iph->saddr, ++ skb->nh.iph->daddr, 0, ++ IPPROTO_TCP, ++ 0); + cmd_length = E1000_TXD_CMD_IP; +- ipcse = skb_transport_offset(skb) - 1; ++ ipcse = skb->h.raw - skb->data - 1; + } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) { +- ipv6_hdr(skb)->payload_len = 0; +- tcp_hdr(skb)->check = +- ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, +- &ipv6_hdr(skb)->daddr, ++ skb->nh.ipv6h->payload_len = 0; ++ skb->h.th->check = ++ ~csum_ipv6_magic(&skb->nh.ipv6h->saddr, ++ &skb->nh.ipv6h->daddr, + 0, IPPROTO_TCP, 0); + ipcse = 0; + } +- ipcss = skb_network_offset(skb); +- ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data; +- tucss = skb_transport_offset(skb); +- tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data; ++ ipcss = skb->nh.raw - skb->data; ++ ipcso = (void *)&(skb->nh.iph->check) - (void *)skb->data; ++ tucss = skb->h.raw - skb->data; ++ tucso = (void *)&(skb->h.th->check) - (void *)skb->data; + tucse = 0; + + cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE | +@@ -3169,7 +3168,7 @@ static bool e1000_tx_csum(struct e1000_a + u8 css; + + if (skb->ip_summed == CHECKSUM_PARTIAL) { +- css = skb_transport_offset(skb); ++ css = skb->h.raw - skb->data; + + i = tx_ring->next_to_use; + buffer_info = &tx_ring->buffer_info[i]; +@@ -3477,7 +3476,7 @@ static int e1000_xmit_frame(struct sk_bu + /* TSO Workaround for 82571/2/3 Controllers -- if skb->data + * points to just header, pull a few bytes of payload from + * frags into skb->data */ +- hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); ++ hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2)); + if (skb->data_len && (hdr_len == (skb->len - skb->data_len))) { + unsigned int pull_size; + |