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| author |   Alfredo Tupone <tupone@gentoo.org> | 2024-01-23 20:48:25 +0100 |
|---|---|---|
| committer | Alfredo Tupone <tupone@gentoo.org> | 2024-01-23 20:49:22 +0100 |
| commit | e0312de38c6fe743ecae9ed06c6309c9bf047dff (patch) | |
| tree | a246b7fa15731bccae9be9babd75a12bece3db7c | |
| parent | app-portage/gpyutils: Keyword 0.12 hppa, #922115 (diff) | |
| download | gentoo-e0312de38c6fe743ecae9ed06c6309c9bf047dff.tar.gz gentoo-e0312de38c6fe743ecae9ed06c6309c9bf047dff.tar.bz2 gentoo-e0312de38c6fe743ecae9ed06c6309c9bf047dff.zip | |
dev-libs/dynolog: build on riscv
Closes: https://bugs.gentoo.org/922515
Signed-off-by: Alfredo Tupone <tupone@gentoo.org>
| -rw-r--r-- | dev-libs/dynolog/dynolog-0.3.1_p20230126-r1.ebuild | 1 | ||||
| -rw-r--r-- | dev-libs/dynolog/files/dynolog-0.3.1_p20230126-riscv.patch | 18 |
2 files changed, 19 insertions, 0 deletions
diff --git a/dev-libs/dynolog/dynolog-0.3.1_p20230126-r1.ebuild b/dev-libs/dynolog/dynolog-0.3.1_p20230126-r1.ebuild index 501e5dee74d8..b1c6480f24db 100644 --- a/dev-libs/dynolog/dynolog-0.3.1_p20230126-r1.ebuild +++ b/dev-libs/dynolog/dynolog-0.3.1_p20230126-r1.ebuild @@ -68,6 +68,7 @@ PATCHES=( "${FILESDIR}"/${P}-gcc13.patch "${FILESDIR}"/${P}-unbundling.patch "${FILESDIR}"/${P}-noWerror.patch + "${FILESDIR}"/${P}-riscv.patch ) CMAKE_SKIP_TESTS=( "Defs.CpuSet" ) diff --git a/dev-libs/dynolog/files/dynolog-0.3.1_p20230126-riscv.patch b/dev-libs/dynolog/files/dynolog-0.3.1_p20230126-riscv.patch new file mode 100644 index 000000000000..7038dbfe7b12 --- /dev/null +++ b/dev-libs/dynolog/files/dynolog-0.3.1_p20230126-riscv.patch @@ -0,0 +1,18 @@ +diff -Naur a/hbt/src/common/System.h b/hbt/src/common/System.h +--- a/hbt/src/common/System.h 2024-01-21 15:26:26.940486370 +0000 ++++ b/hbt/src/common/System.h 2024-01-21 22:22:36.713134358 +0000 +@@ -445,6 +445,14 @@ + asm volatile("mrs %0, cntvct_el0" : "=r"(tstamp)); + cpu = getCpu(); + return tstamp; ++#elif defined(__riscv) ++inline TimeStamp rdtscp(CpuId& cpu) { ++ TimeStamp tstamp; ++ // Use the RDCYCLE instruction for RISC-V. ++ asm volatile("rdcycle %0" : "=r"(tstamp)); ++ cpu = getCpu(); ++ return tstamp; ++ + } + #endif + |