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| author |   Huang Rui <vowstar@gmail.com> | 2020-04-07 16:01:32 +0800 |
|---|---|---|
| committer | Huang Rui <vowstar@gmail.com> | 2020-04-07 16:01:33 +0800 |
| commit | eb6f3704b14ff8a2dd909ffd406887e605bbd3af (patch) | |
| tree | 82cd3a98bd4734e1a850717eeffb001948b7a137 | |
| parent | x11-themes/obsidian-icon-theme: add live build (diff) | |
| download | guru-eb6f3704b14ff8a2dd909ffd406887e605bbd3af.tar.gz guru-eb6f3704b14ff8a2dd909ffd406887e605bbd3af.tar.bz2 guru-eb6f3704b14ff8a2dd909ffd406887e605bbd3af.zip | |
sci-electronics/verilator: add upstream to metadata.xml
Add github remote-id verilator/verilator
Package-Manager: Portage-2.3.96, Repoman-2.3.22
Signed-off-by: Huang Rui <vowstar@gmail.com>
| -rw-r--r-- | sci-electronics/verilator/metadata.xml | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/sci-electronics/verilator/metadata.xml b/sci-electronics/verilator/metadata.xml index 626ddc8c8..7756cca21 100644 --- a/sci-electronics/verilator/metadata.xml +++ b/sci-electronics/verilator/metadata.xml @@ -5,6 +5,9 @@ <email>vowstar@gmail.com</email> <name>Huang Rui</name> </maintainer> + <upstream> + <remote-id type="github">verilator/verilator</remote-id> + </upstream> <longdescription> Verilator, the fastest free Verilog HDL simulator. Accepts synthesizable Verilog or SystemVerilog |